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FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F 2 MC-16LX 16-BIT MICROCONTROLLER MB90420G/425G Series HARDWARE MANUAL CM44-10113-3E

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  • FUJITSU SEMICONDUCTORCONTROLLER MANUAL

    F2MC-16LX16-BIT MICROCONTROLLER

    MB90420G/425G SeriesHARDWARE MANUAL

    CM44-10113-3E

  • F2MC-16LX16-BIT MICROCONTROLLER

    MB90420G/425G SeriesHARDWARE MANUAL

    “Check Sheet” is seen at the following support page

    URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

    “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.

    Be sure to refer to the “Check Sheet” for the latest cautions on development.

    FUJITSU LIMITED

  • PREFACE

    ■ Objectives and Intended Reader

    The MB90420G/425G series of products has been developed as a general-purpose product of

    the F2MC-16LX family of 16-bit one-chip microcontrollers, which can support application-specificIC (ASIC).

    This manual, intended for engineers who develop and design products using MB90420G/425Gseries microcontrollers, describes their features, and explains the operation of the MB90420G/425G series of products.

    Be sure to read this manual before using this product.

    Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

    ■ Trademarks

    The company names and brand names herein are the trademarks or registered trademarks oftheir respective owners.

    i

  • ■ Structure of This Manual

    This manual has 26 chapters and an appendix:

    CHAPTER 1 "OUTLINE"

    This chapter describes features and provides the basic specification of the MB90420G/425Gseries.

    CHAPTER 2 "CPU"

    This Chapter describes the CPU of the F2MC-16LX.

    CHAPTER 3 "INTERRUPTS"

    This chapter describes the relationships between interrupts and the extended intelligent I/O

    service (EI2OS).

    CHAPTER 4 "RESET"

    This chapter describes the reset operation.

    CHAPTER 5 "CLOCK"

    This chapter describes the clock of the MB90420G/425G series.

    CHAPTER 6 "LOW-POWER CONSUMPTION MODE"

    This chapter describes the low-power consumption mode.

    CHAPTER 7 "MODE SETTINGS"

    This chapter describes the operation mode and memory access mode.

    CHAPTER 8 "I/O PORTS"

    This chapter describes the functions and operation of the I/O ports.

    CHAPTER 9 "WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)"

    This chapter describes the functions and operation of the watchdog timer, timebase timer,and watch timer (used as sub-clock).

    CHAPTER 10 "INPUT CAPTURE"

    This chapter describes the input capture operation.

    CHAPTER 11 "16-BIT RELOAD TIMER"

    This chapter describes the functions and operations of the 16-bit reload timer.

    CHAPTER 12 "REAL-TIME WATCH TIMER"

    This chapter describes the functions and operations of the real-time watch timer.

    CHAPTER 13 "PPG TIMER"

    This chapter describes the PPG timer.

    CHAPTER 14 "DELAY INTERRUPT GENERATION MODULE"

    This chapter describes the functions and operations of the delay interrupt generationmodule.

    CHAPTER 15 "DTP/EXTERNAL INTERRUPT CIRCUIT"

    This chapter describes the functions and operations of the DTP/external interrupt circuit.

    CHAPTER 16 "8/10-BIT A/D CONVERTER"

    This chapter describes the functions and operations of the 8/10-bit A/D converter.

    ii

  • CHAPTER 17 "UART"

    This chapter describes the functions and operations of UART.

    CHAPTER 18 "CAN CONTROLLER"

    This chapter describes an overview of the CAN controller and its functions.

    CHAPTER 19 "LCD CONTROLLER/DRIVER"

    This chapter describes the functions and operations of the LCD controller/driver.

    CHAPTER 20 "LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT"

    This chapter describes the functions and operations of the low-voltage/CPU operationdetection reset circuit.

    CHAPTER 21 "STEPPING MOTOR CONTROLLER"

    This chapter describes the functions and operation of the stepping motor controller.

    CHAPTER 22 "SOUND GENERATOR"

    This chapter describes the functions and operation of the sound generator.

    CHAPTER 23 "ADDRESS MATCH DETECTION FUNCTION"

    This chapter describes functions and operations of the address match detection.

    CHAPTER 24 "ROM MIRROR FUNCTION SELECTION MODULE"

    This chapter describes the ROM mirror function selection module.

    CHAPTER 25 "1M BIT FLASH MEMORY"

    This chapter describe functions and operation of the 1M bit flash memory.

    CHAPTER 26 "EXAMPLE OF SERIAL PROGRAMMING CONNECTION"

    This chapter shows an example of a serial programming connection using the AF220/AF210/AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital ComputerCorporation.

    APPENDIX

    The Appendix provides the I/O map and describes the instructions of the F2MC-16LX.

    iii

  • Copyright ©2002-2007 FUJITSU LIMITED All rights reserved.

    • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSUsales representatives before ordering.

    • The information, such as descriptions of function and application circuit examples, in this document are presentedsolely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;FUJITSU does not warrant proper operation of the device with respect to use based on such information. When youdevelop equipment incorporating the device based on such information, you must assume any responsibility arisingout of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the useof the information.

    • Any information in this document, including descriptions of function and schematic diagrams, shall not be construedas license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other rightof FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual propertyright or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectualproperty rights or other rights of third parties which would result from the use of information contained herein.

    • The products described in this document are designed, developed and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and household use, but arenot designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that,unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death,personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flightcontrol, air traffic control, mass transport control, medical life support system, missile launch control in weaponsystem), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Pleasenote that FUJITSU will not be liable against you and/or any third party for any claims or damages arising inconnection with above-mentioned uses of the products.

    • Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss fromsuch failures by incorporating safety design measures into your facility and equipment such as redundancy, fireprotection, and prevention of over-current levels and other abnormal operating conditions.

    • If any products described in this document represent goods or technologies subject to certain restrictions on exportunder the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government willbe required for export of those products from Japan.

    iv

  • CONTENTS

    CHAPTER 1 OUTLINE ...................................................................................................... 11.1 Product Outline ................................................................................................................................... 21.2 Features .............................................................................................................................................. 41.3 Block Diagram .................................................................................................................................... 61.4 Diagram Showing Package Dimensions ............................................................................................. 81.5 Pin Assignment Diagram .................................................................................................................. 101.6 Description of Pin Functions ............................................................................................................. 121.7 Types of Input/Output Circuits .......................................................................................................... 161.8 Precautions for Device Handling ...................................................................................................... 18

    CHAPTER 2 CPU ............................................................................................................ 212.1 Outline of CPU .................................................................................................................................. 222.2 Memory Space .................................................................................................................................. 242.3 Memory Map ..................................................................................................................................... 262.4 Addressing ........................................................................................................................................ 28

    2.4.1 Addressing with Linear Scheme .................................................................................................. 292.4.2 Addressing with Bank Scheme .................................................................................................... 30

    2.5 Allocation of Multiple-Byte Data in the Memory ................................................................................ 322.6 Registers ........................................................................................................................................... 342.7 Dedicated Registers ......................................................................................................................... 35

    2.7.1 Accumulator (A) ........................................................................................................................... 372.7.2 Stack Pointers (USP, SSP) ......................................................................................................... 402.7.3 Processor Status (PS) ................................................................................................................. 422.7.4 Program Counter (PC) ................................................................................................................. 462.7.5 Direct Page Register (DPR) ........................................................................................................ 472.7.6 Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................ 48

    2.8 General-Purpose Register ................................................................................................................ 492.9 Prefix Codes ..................................................................................................................................... 51

    CHAPTER 3 INTERRUPTS ............................................................................................. 573.1 Outline of Interrupts .......................................................................................................................... 583.2 Interrupt Sources and Interrupt Vectors ............................................................................................ 603.3 Interrupt Control Registers and Peripheral Functions ....................................................................... 63

    3.3.1 Interrupt Control Registers (ICR00 to ICR15) .............................................................................. 653.3.2 Function of Interrupt Control Registers ........................................................................................ 67

    3.4 Hardware Interrupts .......................................................................................................................... 703.4.1 Hardware Interrupt Operation ...................................................................................................... 733.4.2 Operation Flow for Hardware Interrupts ...................................................................................... 753.4.3 Procedure for Using Hardware Interrupts .................................................................................... 763.4.4 Multiple Interrupts ........................................................................................................................ 773.4.5 Time for Handling Hardware Interrupts ....................................................................................... 79

    3.5 Software Interrupts ........................................................................................................................... 813.6 Interrupt by Extended Intelligent I/O Service (EI2OS) ....................................................................... 83

    v

  • 3.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .......................................................... 853.6.2 Registers of the Extended intelligent I/O Service (EI2OS) Descriptor (ISD) ................................ 873.6.3 Operation of the Extended intelligent I/O Service (EI2OS) .......................................................... 903.6.4 Procedure for Using the Extended Intelligent I/O Service (EI2OS) .............................................. 913.6.5 Processing Time for the Extended intelligent I/O Service (EI2OS) .............................................. 92

    3.7 Exception Processing Interrupts when Executing Undefined Instructions ........................................ 953.8 Stack Operations of Interrupt Handling ............................................................................................. 963.9 Example Program for Interrupt Handling .......................................................................................... 98

    CHAPTER 4 RESET ...................................................................................................... 1034.1 Outline of Reset Operation ............................................................................................................. 1044.2 Reset Sources and Oscillation Stabilization Wait Time .................................................................. 1074.3 External Reset Pin .......................................................................................................................... 1094.4 Reset Operation .............................................................................................................................. 1104.5 Reset Source Bit ............................................................................................................................. 1124.6 State of Each Pin after Reset ......................................................................................................... 116

    CHAPTER 5 CLOCK ..................................................................................................... 1175.1 Outline of Clock Unit ....................................................................................................................... 1185.2 Block Diagram of the Clock Generation Section ............................................................................. 1215.3 Clock Selection Register (CKSCR) ................................................................................................. 1235.4 Clock Mode ..................................................................................................................................... 1265.5 Oscillation Stabilization Wait Time .................................................................................................. 1305.6 Connection of Resonator and External Clock ................................................................................. 131

    CHAPTER 6 LOW-POWER CONSUMPTION MODE ................................................... 1336.1 Outline of Low-Power Consumption Mode ..................................................................................... 1346.2 Block Diagram of Low-Power Consumption Control Circuit ........................................................... 1376.3 Low-Power Consumption Mode Control Register (LPMCR) ........................................................... 1396.4 CPU Intermittent Operation Mode .................................................................................................. 1426.5 Standby Modes ............................................................................................................................... 143

    6.5.1 Sleep Mode ............................................................................................................................... 1446.5.2 Timebase Timer Mode ............................................................................................................... 1466.5.3 Watch Mode .............................................................................................................................. 1486.5.4 Stop Mode ................................................................................................................................. 150

    6.6 State Transition Diagram ................................................................................................................ 1526.7 Pin States in Standby Mode and During Reset .............................................................................. 1546.8 Notes on Using the Low-Power Consumption Mode ...................................................................... 156

    CHAPTER 7 MODE SETTINGS .................................................................................... 1617.1 Setting the Mode ............................................................................................................................. 1627.2 Mode pins (MD2 to MD0) ................................................................................................................ 1637.3 Mode Data ...................................................................................................................................... 164

    CHAPTER 8 I/O PORTS ................................................................................................ 1678.1 I/O Ports .......................................................................................................................................... 1688.2 Assignment of Registers and Pins Shared with External Pins ........................................................ 170

    vi

  • 8.3 Port 0 .............................................................................................................................................. 1718.3.1 Port 0 registers (PDR0, DDR0) ................................................................................................. 1738.3.2 Description of Port 0 Operation ................................................................................................. 174

    8.4 Port 1 .............................................................................................................................................. 1768.4.1 Port 1 Registers (PDR1, DDR1) ................................................................................................ 1788.4.2 Description of Port 1 Operation ................................................................................................. 179

    8.5 Port 3 .............................................................................................................................................. 1818.5.1 Port 3 Registers (PDR3, DDR3) ................................................................................................ 1838.5.2 Description of Port 3 Operation ................................................................................................. 184

    8.6 Port 4 .............................................................................................................................................. 1868.6.1 Port 4 Registers (PDR4, DDR4) ................................................................................................ 1888.6.2 Description of Port 4 Operation ................................................................................................. 189

    8.7 Port 5 .............................................................................................................................................. 1918.7.1 Port 5 Registers (PDR5, DDR5) ................................................................................................ 1938.7.2 Description of Port 5 Operation ................................................................................................. 194

    8.8 Port 6 .............................................................................................................................................. 1968.8.1 Port 6 Registers (PDR6, DDR6, ADER) .................................................................................... 1988.8.2 Description of Port 6 Operation ................................................................................................. 200

    8.9 Port 7 .............................................................................................................................................. 2028.9.1 Port 7 Registers (PDR7, DDR7) ................................................................................................ 2048.9.2 Description of Port 7 Operation ................................................................................................. 205

    8.10 Port 8 .............................................................................................................................................. 2078.10.1 Port 8 Registers (PDR8, DDR8) ................................................................................................ 2098.10.2 Description of Port 8 Operation ................................................................................................. 210

    8.11 Port 9 .............................................................................................................................................. 2128.11.1 Functions of Port 9 Registers (PDR9, DDR9) ........................................................................... 2148.11.2 Description of Port 9 Operation ................................................................................................. 215

    8.12 Example Program for I/O Port ........................................................................................................ 217

    CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK) ............................................................................................................... 219

    9.1 Outline of Watchdog Timer/Timebase Timer/Watch Timer ............................................................. 2209.2 Block Diagrams of Watchdog Timer/Timebase Timer/Watch Timer ............................................... 2219.3 List of Registers for Watchdog Timer/Timebase Timer/Watch Timer ............................................. 222

    9.3.1 Watchdog Timer Control Register (WDTC) ............................................................................... 2239.3.2 Timebase Timer Control Register (TBTC) ................................................................................. 2259.3.3 Watch Timer Control Register (WTC) ........................................................................................ 227

    9.4 Operation of Watchdog Timer/Timebase Timer/Watch Timer ........................................................ 2299.4.1 Watchdog Timer Operation ....................................................................................................... 2309.4.2 Timebase Timer Operation ........................................................................................................ 2329.4.3 Watch Timer Operation ............................................................................................................. 234

    9.5 Notes on Using the Watchdog Timer/Timebase Timer ................................................................... 2369.6 Example Program for Watchdog Timer/Timebase Timer ............................................................... 238

    CHAPTER 10 INPUT CAPTURE ..................................................................................... 24110.1 Outline of Input Capture .................................................................................................................. 24210.2 Block Diagram of Input Capture ...................................................................................................... 243

    vii

  • 10.3 List of Input Capture Registers ....................................................................................................... 24410.3.1 Detailed Description of the Input Capture Registers ................................................................. 24610.3.2 Detailed Description of 16-bit Free-run Timer Register ............................................................. 248

    10.4 Description of Operations ............................................................................................................... 25310.4.1 16-bit Input Capture ................................................................................................................... 25410.4.2 16-bit Free-run Timer Section .................................................................................................... 256

    CHAPTER 11 16-BIT RELOAD TIMER ........................................................................... 25911.1 Overview of 16-Bit Reload Timer .................................................................................................... 26011.2 Configuration of 16-Bit Reload Timer ............................................................................................. 26311.3 Pins of 16-Bit Reload Timer ............................................................................................................ 26511.4 Registers of 16-Bit Reload Timer .................................................................................................... 267

    11.4.1 Upper Bits of Timer Control Status Registers (TMCSR0H/TMCSR1H) ..................................... 26811.4.2 Lower Bits of Timer Control Status Registers (TMCSR0L/TMCSR1L) ...................................... 27011.4.3 16-Bit Timer Registers (TMR0, TMR1) ...................................................................................... 27211.4.4 16-Bit Reload Registers (TMRLR0, TMRLR1) .......................................................................... 273

    11.5 Interrupts of 16-Bit Reload Timer .................................................................................................... 27411.6 Operation of 16-Bit Reload Timer ................................................................................................... 275

    11.6.1 Internal Clock Mode (Reload Mode) .......................................................................................... 27711.6.2 Internal Clock Mode (One-Shot Mode) ...................................................................................... 27911.6.3 Event Count Mode ..................................................................................................................... 282

    11.7 Notes on Using the 16-Bit Reload Timer ........................................................................................ 28411.8 Sample Programs for the 16-Bit Reload Timer ............................................................................... 285

    CHAPTER 12 REAL-TIME WATCH TIMER .................................................................... 28912.1 Overview of Real-Time Watch Timer .............................................................................................. 29012.2 Registers of Real-Time Watch Timer .............................................................................................. 291

    12.2.1 Real-Time Watch Timer Control Register .................................................................................. 29312.2.2 Sub-Second Data Register ........................................................................................................ 29512.2.3 Second/Minute/Hour Data Registers ......................................................................................... 296

    CHAPTER 13 PPG TIMER .............................................................................................. 29713.1 Overview of PPG Timer .................................................................................................................. 29813.2 Block Diagram of PPG Timer .......................................................................................................... 30013.3 Registers of PPG Timer .................................................................................................................. 301

    13.3.1 Detailed Description of the PPG Timer ...................................................................................... 30213.4 Operation of PPG Timer ................................................................................................................. 307

    CHAPTER 14 DELAY INTERRUPT GENERATION MODULE ....................................... 31114.1 Overview of Delay Interrupt Generation Module ............................................................................. 31214.2 Operation of Delay Interrupt Generation Module ............................................................................ 314

    CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT ................................................. 31515.1 Overview of DTP/External Interrupt Circuit ..................................................................................... 31615.2 Configuration of DTP/External Interrupt Circuit .............................................................................. 31815.3 Pins of DTP/External Interrupt Circuit ............................................................................................. 32015.4 Registers of DTP/External Interrupt Circuit ..................................................................................... 322

    viii

  • 15.4.1 DTP/Interrupt source Register (EIRR) ....................................................................................... 32315.4.2 DTP/Interrupt Enable Register (ENIR) ...................................................................................... 32415.4.3 Request Level Setting Register (ELVRH/ELVRL) ..................................................................... 326

    15.5 Operation of the DTP/External Interrupt Circuit .............................................................................. 32815.5.1 External Interrupt Function ........................................................................................................ 33115.5.2 DTP Function ............................................................................................................................. 332

    15.6 Notes on Using the DTP/External Interrupt Circuit ......................................................................... 33415.7 Sample Programs for the DTP/External Interrupt Circuit ................................................................ 336

    CHAPTER 16 8/10-BIT A/D CONVERTER ..................................................................... 33916.1 Overview of 8/10-Bit A/D Converter ................................................................................................ 34016.2 Configuration of 8/10-Bit A/D Converter ......................................................................................... 34216.3 Pins of 8/10-Bit A/D Converter ........................................................................................................ 34416.4 Registers of 8/10-Bit A/D Converter ............................................................................................... 346

    16.4.1 Upper Bits of A/D Control Status Register (ADCSH) ................................................................. 34716.4.2 Lower bits of A/D Control Status Register (ADCSL) .................................................................. 35016.4.3 A/D Data Registers (ADCRH/ADCRL) ...................................................................................... 353

    16.5 Interrupts of 8/10-Bit A/D Converter ............................................................................................... 35516.6 Operation of 8/10-Bit A/D Converter ............................................................................................... 356

    16.6.1 Conversion Operation Using EI2OS .......................................................................................... 35816.6.2 A/D Conversion Data Protect Function ...................................................................................... 359

    16.7 Notes on Using the 8/10-Bit A/D Converter .................................................................................... 36116.8 Sample Program 1 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Single Mode) ....... 36216.9 Sample Program 2 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Continuous Mode)

    ...................................................................................................................................................... 36416.10 Sample Program 3 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Stop Mode) .......... 367

    CHAPTER 17 UART ........................................................................................................ 36917.1 Overview of UART .......................................................................................................................... 37017.2 Configuration of UART .................................................................................................................... 37217.3 Pins of UART .................................................................................................................................. 37517.4 Registers of UART .......................................................................................................................... 377

    17.4.1 Control Registers (SCR0/SCR1) ............................................................................................... 37817.4.2 Mode Registers (SMR0/SMR1) ................................................................................................. 38117.4.3 Status Registers (SSR0/SSR1) ................................................................................................. 38317.4.4 Input Data Registers (SIDR0/SIDR1) and Output Data Registers (SODR0/SODR1) ................ 38517.4.5 Communication Prescaler Control Registers (CDCR0/CDCR1) ................................................ 387

    17.5 Interrupts of UART .......................................................................................................................... 38917.5.1 Timing of Receive Interrupt Generation and Flag Setting ......................................................... 39117.5.2 Timing of Send Interrupt Generation and Flag Setting .............................................................. 392

    17.6 Baud Rates of UART ...................................................................................................................... 39317.6.1 Baud Rate Selection by Dedicated Baud Rate Generator ......................................................... 39517.6.2 Baud Rate Selection by Internal Timer (16-Bit Reload Timer) .................................................. 39817.6.3 Baud Rate Selection by External Clock ..................................................................................... 400

    17.7 Operation of UART ......................................................................................................................... 40117.7.1 Asynchronous Mode Operation (Operation Modes 0, 1) ........................................................... 40317.7.2 Synchronous Mode Operation (Operation Mode 2) ................................................................... 406

    ix

  • 17.7.3 Bi-directional Communication Function (Normal Mode) ............................................................ 40817.7.4 Function for Master/Slave Communication (Multiprocessor Mode) ........................................... 410

    17.8 Notes on Using UART .................................................................................................................... 41317.9 Sample Program for UART ............................................................................................................. 414

    CHAPTER 18 CAN CONTROLLER ................................................................................ 41718.1 CAN Controller Features ................................................................................................................ 41818.2 Block Diagram of CAN Controller ................................................................................................... 41918.3 Types of CAN Controller Registers ................................................................................................. 420

    18.3.1 Control Status Register (CSR) .................................................................................................. 42918.3.2 Last Event Indication Register (LEIR) ....................................................................................... 43418.3.3 Receive and Transmit Error Counter (RTEC) ............................................................................ 43618.3.4 Bit Timing Register (BTR) .......................................................................................................... 43718.3.5 Message Buffer Valid Register (BVALR) ................................................................................... 44018.3.6 IDE Register (IDER) .................................................................................................................. 44118.3.7 Transmission Request Register (TREQR) ................................................................................ 44218.3.8 Transmission RTR Register (TRTRR) ....................................................................................... 44318.3.9 Remote Frame Receive Wait Register (RFWTR) ...................................................................... 44418.3.10 Transmission Cancel Register (TCANR) ................................................................................... 44518.3.11 Transmission Complete Register (TCR) .................................................................................... 44618.3.12 Transmission Interrupt Enable Register (TIER) ......................................................................... 44718.3.13 Receive Complete Register (RCR) ............................................................................................ 44818.3.14 Remote Request Transmission Register (RRTRR) ................................................................... 44918.3.15 Receive Overrun Register (ROVRR) ......................................................................................... 45018.3.16 Receive Interrupt Enable Register (RIER) ................................................................................. 45118.3.17 Acceptance Mask Selection Register (AMSR) .......................................................................... 45218.3.18 Acceptance mask Registers 0/1 (AMR0/AMR1) ........................................................................ 45418.3.19 Message Buffers ........................................................................................................................ 45618.3.20 ID Register x (x = 0 to 15) (IDRx) .............................................................................................. 45718.3.21 DLC Register x (x = 0 to 15) (DLCRx) ....................................................................................... 46018.3.22 Data Register x (x = 0 to 15) (DTRx) ......................................................................................... 46118.3.23 CAN Wake-up Control Register (CWUCR) ............................................................................... 463

    18.4 Transmission via CAN Controller .................................................................................................... 46418.5 Reception via CAN Controller ......................................................................................................... 46718.6 Notes on Using CAN Controller ...................................................................................................... 47118.7 Transmission via Message Buffer (x) ............................................................................................. 47218.8 Reception via Message Buffer (x) ................................................................................................... 47418.9 Specifying the Multi-Level Message Buffer Configuration .............................................................. 47618.10 CAN Wake-up Function ................................................................................................................. 47918.11 Precautions when Using CAN Controller ....................................................................................... 48118.12 Sample Program for CAN Controller ............................................................................................. 482

    CHAPTER 19 LCD CONTROLLER/DRIVER .................................................................. 48519.1 Outline of LCD Controller/Driver ..................................................................................................... 48619.2 Configuration of LCD Controller/Driver ........................................................................................... 487

    x

  • 19.2.1 LCD Controller/Driver’s Internal Divide Resistor ....................................................................... 48919.2.2 LCD Controller/Driver’s External Divide Resistor ...................................................................... 491

    19.3 LCD Controller/Driver Pins ............................................................................................................. 49319.4 LCD Controller/Driver Register ....................................................................................................... 495

    19.4.1 Lower Bits of LCD Control Register (LCRL) .............................................................................. 49619.4.2 Upper Bits of LCD Control Register (LCRH) ............................................................................. 498

    19.5 LCD Controller/Driver Display RAM ................................................................................................ 50019.6 Operation of LCD Controller/Driver ................................................................................................. 502

    19.6.1 Output Waveform during LCD Controller/Driver Operation (1/2 Duty) ....................................... 50419.6.2 Output Waveform in LCD Controller/Driver Operation (1/3 Duty) .............................................. 50719.6.3 Output Waveform in LCD Controller/Driver Operation (1/4 Duty) .............................................. 510

    CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT ................................................................................................................ 513

    20.1 Outline of the Low-voltage/CPU Operation Detection Reset Circuit ............................................... 51420.2 Configuration of the Low-Voltage/CPU Operation Detection Reset Circuit .................................... 51620.3 Registers of the Low-voltage/CPU Operation Detection Reset Circuit ........................................... 51820.4 Operation of the Low-voltage/CPU Operation Detection Reset Circuit .......................................... 52020.5 Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit ...................................... 52120.6 Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit .............................. 522

    CHAPTER 21 STEPPING MOTOR CONTROLLER ....................................................... 52321.1 Outline of the Stepping Motor Controller ........................................................................................ 52421.2 Registers of the Stepping Motor Controller ..................................................................................... 525

    21.2.1 PWM Control Register (PWC0 to PWC3) .................................................................................. 52721.2.2 PWM1 and PWM2 Compare Registers (PWC10 to PWC13, PWC20 to PWC23) .................... 52821.2.3 PWM1/PWM2 Selection Registers (PWS10 to PWS13, PWS20 to PWS23) ............................ 530

    21.3 Operation of the Stepping Motor Controller .................................................................................... 53221.4 Notes on Using the Stepping Motor Controller ............................................................................... 534

    CHAPTER 22 SOUND GENERATOR ............................................................................. 53522.1 Outline of the Sound Generator ...................................................................................................... 53622.2 Registers of the Sound Generator .................................................................................................. 537

    22.2.1 Sound Control Register (SGCRH, SGCRL) .............................................................................. 53822.2.2 Frequency Data Register (SGFR) ............................................................................................. 54022.2.3 Amplitude Data Register (SGAR) .............................................................................................. 54122.2.4 Decrement Grade Register (SGDR) .......................................................................................... 54222.2.5 Tone Count Register (SGTR) .................................................................................................... 543

    CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION ......................................... 54523.1 Outline of the Address Match Detection Function .......................................................................... 54623.2 Example Application of the Address Match Detection Function ..................................................... 549

    23.2.1 Example of Program Error Correction ....................................................................................... 55123.2.2 Example of Correction Processing ............................................................................................ 552

    xi

  • CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE ................................ 55524.1 Outline of the ROM Mirror Function Selection Module ................................................................... 55624.2 ROM Mirror Function Selection Register (ROMM) ......................................................................... 557

    CHAPTER 25 1M BIT FLASH MEMORY ........................................................................ 55925.1 Outline of 1M Bit Flash Memory ..................................................................................................... 56025.2 Overall Block Diagram of the Flash Memory and Its Sector Configuration ..................................... 56225.3 Write/Erase Mode ........................................................................................................................... 56425.4 Flash Memory Control Status Register (FMCS) ............................................................................. 56625.5 Starting the Flash Memory Automatic Algorithm ............................................................................ 56825.6 Confirming the Execution State of the Automatic Algorithm ........................................................... 569

    25.6.1 Data Polling Flag (DQ7) ............................................................................................................ 57125.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 57325.6.3 Timing Limit Excess Flag (DQ5) ................................................................................................ 57525.6.4 Sector Erasure Timer Flag (DQ3) .............................................................................................. 576

    25.7 Detailed Description of Writing/Erasing Flash Memory Data .......................................................... 57725.7.1 Setting the Flash Memory to Read/Reset State ........................................................................ 57825.7.2 Writing Data to the Flash Memory ............................................................................................. 57925.7.3 Erasing All Data in the Flash Memory (Chip Erase) .................................................................. 58125.7.4 Erasing Data from the Flash Memory (Sector erase) ................................................................ 58225.7.5 Suspending Flash Memory Sector Erasure ............................................................................... 58425.7.6 Restarting Flash Memory Sector Erasure ................................................................................. 585

    25.8 Notes on Using Flash Memory ....................................................................................................... 58625.9 Sample Program for the 1M Bit Flash Memory ............................................................................... 587

    CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION ...................... 59126.1 Basic Configuration ......................................................................................................................... 59226.2 Oscillator Clock Frequency and Serial Clock Input Frequency ....................................................... 59426.3 System Configuration of Flash Microcontroller Programmer .......................................................... 59526.4 Examples of Serial Programming Connection ................................................................................ 596

    APPENDIX ......................................................................................................................... 605APPENDIX A I/O Map ................................................................................................................................ 606APPENDIX B Instructions ........................................................................................................................... 614

    B.1 Instruction Types ............................................................................................................................ 615B.2 Addressing ..................................................................................................................................... 616B.3 Direct Addressing ........................................................................................................................... 618B.4 Indirect Addressing ........................................................................................................................ 624B.5 Execution Cycle Count ................................................................................................................... 632B.6 Effective address field .................................................................................................................... 635B.7 How to Read the Instruction List .................................................................................................... 636B.8 F2MC-16LX Instruction List ............................................................................................................ 639B.9 Instruction Map ............................................................................................................................... 653

    INDEX................................................................................................................................... 675

    xii

  • Main changes in this edition

    Page Changes (For details, refer to main body.)

    -

    Part number is deleted.(MB90F423GB, MB90F428GB, MB90423GB, MB90427GB, MB90428GB)

    Name is changed.(ELVR → ELVRH/ELVRL)(PCNTH0-2 → PCNTH0 to PCNTH2)(Lower bits of PPG control status register: PCNTH0-2 → PCNTL0 to PCNTL2)(Upper bits/lower bits of PPG down counter register: PDCRH0-2 → PDCR0 to PDCR2)(Upper bits/lower bits of PPG interval setting register: PCSRH0-2 → PCSR0 to PCSR2)(Upper bits of PPG duty setting register: PDUTH0-2 → PDUT0 to PDUT2)(Lower bits of PPG duty setting register: PDUTL0-2 → PDUT0 to PDUT2)(additional bank register → additional data bank register)(program bank register(PCB) → program counter bank register(PCB))(16-bit timer registers(TMR0/1L, TMR0/1H) → 16-bit timer registers(TMR0, TMR1))(16-bit reload registers(TMRLR0/1L, TMRLR0/1H) → 16-bit reload registers(TMRLR0, TMRLR1))(Timer control status registers(TMCSR0/1L, TMCSR0/1H) → Timer control status registers(TMCSR0L, TMCSR1L/TMCSR0H, TMCSR1H))

    2Table 1.1-1 Outline of MB90420G Series Products is changed.(*1: Being developed is deleted.)

    3Table 1.1-2 Outline of MB90425G Series Products is changed.(*1: Being developed is deleted.)

    17 Type E, F, G, H are changed in Table 1.7-1 Types of Input/Output Circuits.

    20■ Pull-up/Pull-down Resistor is changed.(internal pull-up nor pull-down resistors → internal pull-up nor pull-down resistors option)■ About the Terminal Processing when LCD Function is not Used is added.

    33Figure 2.5-3 Allocation of Multiple-byte Data on the Stack is changed.(*: Stack state after PUSH instruction is executed is deleted.)

    67Figure 3.3-3 Configuration of Interrupt Control Registers (ICR) is changed.(Access is added.)

    104Oscillation stabilization wait of Watchdog timer reset is changed in Table 4.1-1 Reset Source.(Used → None)

    107Oscillation stabilization wait time of Watchdog reset is changed in Table 4.2-1 Reset Sources and Oscillation Stabilization Wait Time.(Used: WS1 and WS0 bits initialized to "11" → Not used: WS1 and WS0 bits initialized to "11B")

    122

    ❍ Oscillation stabilization wait time selector is changed.( A circuit to select the oscillation stabilization wait time for the oscillation clock when the stopmode is cleared and the watchdog timer is reset. → A circuit to select the oscillation stabilization wait time for the oscillation clock when the stop mode is cleared.)

    123The access of bit14 in Figure 5.3-1 Configuration of Clock Selection Register (CKSCR).(R → R/W)

    xiii

  • 124

    The bit11 is changed in Table 5.3-1 Descriptions of Functions of Each Bit in the Clock Selection Register (CKSCR).("• Changing the SCS bit in the CKSCR register from "1" to "0" in the main clock mode changes the main clock to the sub-clock synchronizing the sub-clock (approx.130 µs)." is added.)

    126 ❍ Transition from main clock mode to sub-clock mode is changed.

    127, 136 Notes is changed.

    128 Figure 5.4-1 State Transition Diagram for the Machine Clock Selection is changed.

    139The bit7, bit6, bit4 are changed in Figure 6.3-1 Configuration of the Low-power Consumption Mode Control Register (LPMCR).(W → R/W)

    141■ Accessing the Low-Power Consumption Mode Control Register is changed.Table 6.3-2 Instructions Applicable in Transition to Low-power Consumption Mode is changed.

    152Figure 6.6-1 State Transition Diagram is changed.(Timebase timer mode → Main timebase timer mode)(Timebase timer mode → PLL timebase timer mode)

    153Table 6.6-1 Operation States of the Low-power Consumption Mode is changed.(Timebase timer → PLL timebase timer)(Timebase timer → Main timebase timer)

    154 Table 6.7-1 Pin States in Single-chip Mode is changed.

    158

    ■ Switching the Clock Mode is changed.("If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched." is added.)■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode is added.

    163 Table 7.2-1 Mode Pin Settings is changed.

    169 Table 8.1-1 Port Functions is changed.

    222Figure 9.3-1 Registers for Watchdog Timer, Timebase Timer and Watch Timer is changed.(Read/write is changed.)

    225Read/write of bit2 is changed in Figure 9.3-3 Bit Configuration of the Timebase Timer Control Register (TBTC).(W → R/W)

    227

    Read/write of bit3 is changed in Figure 9.3-4 Bit Configuration of the Watch Timer Control Register.(W → R/W)[bit7] WDCS is changed.("During operation in the subclock mode, set the WDCS bit to "0" to select the watch timer. If the mode tran-sits to the subclock mode with the WDCS bit setting to "1", the watchdog timer stops." is added.)

    235 ■ Clock Source for Watchdog Timer Specifying Function is added.

    236❍ Effects of clearing the timebase timer is changed.(• Use of the watchdog timer is deleted.)

    243Figure 10.2-1 Block Diagram of the Input Capture is changed.(MSI3 to 0 → MSI2 to MSI0)

    Page Changes (For details, refer to main body.)

    xiv

  • 244Figure 10.3-1 16-bit Free-run Timer Section Registers is changed.(TCCS → TCCSH)(TCCS → TCCSL)

    249 ■ Compare Clear Register (CPCLR) is changed.

    251

    [bit9]: ICLR is changed.(The ICLR bit is set to "1" if the compare clear register value and the value of the 16-bit free-run timer value match, and the counter is cleared. → The ICLR bit is set to "1" if the compare clear register value and the value of the 16-bit free-run timer value match.)

    252

    ■ Timer Control Status Register (TCCSH, TCCSL)[bit4]: MODE is changed.((bit 3: CLR) → (bit3: SCLR))(compare clear register → compare clear register (CPCLR))[bit3]: SCLR is changed.(Note is added.)

    255Figure 10.4-2 Capture Timing for Input Signal is changed.(N-1 → N+1)

    256

    ■ Explanation of 16-bit Free-run Timer Operation is changed.(• Setting the SCLR bit of the TCCS register to "1" during operation → • Setting the SCLR bit of the TCCSH and TCCSL registers to "1" during operation)( An interrupt may occur if an overflow is generated or the counter is cleared by matching with the compare clear register value → When the overflow is generated or when the compare clear register value and the free-run timer are matched by comparing, the interruption is generated.)

    265P11/TOT0/WOT is changed in Table 11.3-1 Pins of the 16-bit Reload Timer.( Setting to timer output enabled (TMCSR0L:OUTE=1) Sound generator output disabled → Real-time Watch timer output disabled (WTCRL:OE=1) when using the TOT0)

    285[Coding example] is changed.(MOVW I:TMRLR, #30D4H → MOVW I:TMRLR, #30D3H)

    291Summary of 12.2 Registers of Real-Time Watch Timer is changed.(• Real-time watch timer control register (WTCR) → • Real-time watch timer control register (WTCRL, WTCRH))

    307Figure 13.4-1 Timing of PWM Operation when Restart is Disabled is changed.( ➀ = T( n − 1 ) µs → ➀ = T( n + 1 ) µs)( ➁ = T( m − 1 ) µs → ➁ = T( m + 1 ) µs)

    308, 309Figure 13.4-2, Figure 13.4-3, Figure 13.4-4 are changed.( The meaning of ➀ , ➁ , T, m, n are added.)

    323 Notes is changed.

    324 Notes is changed.

    328■ Settings of the DTP/External Interrupt Circuit is changed.("1. The terminal used as an external interrupt input and the General-purpose I/O port usedcombinedly are set to the input port." is added.)

    349

    Table 16.4-1 Description of Bit Functions in the Upper 8 Bits of the A/D Control Status Register (ADCSH).The function of bit9 is changed.("• The byte-words command reads "1".• The read-modify-write type instructions read "0". " is added.)

    Page Changes (For details, refer to main body.)

    xv

  • 351

    Table 16.4-2 Description of Functions of Lower Bits of the A/D Control Status Register (ADCSL).The function of bit5 to bit3 is changed.("• And before A/D conversion starts, the preversion channel will be read even if these bits have already been set to the new value.• Upon a reset, these bits are initialized to "000B"." is added.)

    352Table 16.4-2 Description of Functions of Lower Bits of the A/D Control Status Register (ADCSL).The function of bit2, bit1, bit0 is changed .(Note is added.)

    379

    Table 17.4-1 Functions of Bits of the Control Registers (SCR0/SCR1)The function of bit10 is changed.(FRE, DRE or PE → FRE, ORE or PE)The function of bit9 is changed.("When either of RXE or TXE is set to "1" at the operation mode 2 (synchronous), both operating transmis-sion and reception is enabled." is added.)

    380Table 17.4-1 Functions of Bits of the Control Registers (SCR0/SCR1)The function of bit8 is changed.

    382Table 17.4-2 Functions of Bits in the Mode Registers (SMR0/SMR1)The function of bit5, bit4, bit3 is changed.(Notes is added.)

    384

    Table 17.4-3 Functions of Bits in the Status Registers (SSR0/SSR1)The function of bit15, bit14, bit13 is changed.(mode register (SMR) → control register (SCR))The function of bit10 is changed.(SDR → SIDR and SODR registers)

    387[bit15] MD (Machine clock divide mode select) is changed.(MS bit → MD bit)

    388 Note is changed.

    396

    Table 17.6-2 Selection of Synchronous Baud Rate and Divide Ratio is changed.(Table is changed.)(φ is derived from the machine cycle, with φ = 16 MHz and div = 4. → φ is derived from the machine cycle, with φ = 16 MHz and div = 2.)

    Table 17.6-3 Selection of Asynchronous Baud Rate Divide Ratio is changed.(SCKI is deleted.)❍ Internal timer is changed.(Note is changed.)

    399 Note is added.

    406 Figure 17.7-5 Transfer Data Format (in Operation Mode 2) is changed.

    407 Note is added.

    413 ❍ Clock setting at the clock synchronous mode is added.

    421Table 18.3-2 Message Buffer Control Registers is changed.((R/W) → (W))

    424Table 18.3-3 Message Buffers (ID Registers) is changed.(003A43H, 003B43H are added.)

    Page Changes (For details, refer to main body.)

    xvi

  • 425Table 18.3-3 Message Buffers (ID Registers) is changed.(003A5FH, 003B5FH are added.)

    429 Summary of 18.3.1 Control Status Register (CSR) is changed.

    431■ Bit Configuration of Control Status Register (CSR)[bit0] HALT: bus operation stop bit is changed.

    432 Example program is added.

    439 ❍ Sample setting is changed.

    455Figure 18.3-21 Bit Configuration of acceptance Mask Registers 0/1 (AMR0/AMR1) is changed.(AMR0 → AMR1)

    472❍ Setting the send data length code is changed.(DLC3 to DLC0 → ID3 to ID0)

    477Figure 18.9-1 Example of Multi-level Message Buffer Operation is changed.(AMS0 → AMR0)

    488❍ Display RAM is changed.(output from the segment output pin → output simultaneously with rewriting to display RAM)

    495LCRH (Upper bits of LCD control register) is changed in Figure 19.4-1 Bit Configuration of LCD Controller/Driver Related Registers.

    496■ Bit Configuration of the Lower Bits of the LCD Control Register (LCRL) is changed.(Figure 19.4-2 Bit Configuration of the Lower Bits of the LCD Control Register (LCRL) is changed.)

    497

    Table 19.4-1 Functional Description of Each Bit among the Lower Bits of the LCD Control Register (LCRL)The bit6 is changed.(Watch mode operation enable bit → Timebase timer mode operation enable bit)(in watch mode → in timebase timer mode)

    498 Figure 19.4-3 Bit Configuration of Upper Bits of LCD Control Register (LCRH) is changed.

    499Table 19.4-2 Functional Description of Each Bit among the Upper Bits of the LCD Control Register (LCRH)The bit12 is changed.

    502 LCRH is changed in Figure 19.6-1 Settings of LCD Controller/Driver.

    514■ Low-Voltage Detection Reset Circuit is changed.(During generation of an internal reset, reset output from this circuit is suppressed.)

    515■ CPU Operation Detection Reset Circuit is changed.("• Power-on reset" is added)

    568Notes is changed.(• PA: write address must be an even address only. → • PA: write address)

    575❍ Operation during write/chip sector erasure is changed.("Normal end might be done unusually as if "1" is written." is added.)

    579

    ❍ Address specification is changed.("Only even addresses can be specified as write address in the write data cycle. If an odd address is specified, the write operation will not be performed correctly. Writing must be performed to even addresses in word units." is deleted.)

    583 Figure 25.7-2 Sample Procedure for Erasing a Sector from Flash Memory is changed.

    Page Changes (For details, refer to main body.)

    xvii

  • The vertical lines marked in the left side of the page show the changes.

    584

    ■ Suspending Flash Memory Sector Erasure is changed.(15 µs or earlier → 20 µs or earlier)("Please issue the command after 20 µs or later has passed since the sector erase command or the sector erase restart command issued it." is added.)

    593Table 26.1-1 Function of Related Pins is changed.(If the programming voltage (VCC=5.0V±10%) is supplied from the user system, connection with the flash microcomputer programmer is not required. → If the programming voltage (VCC=5.0V±10%))

    607 to 610

    Table A-1 I/O Map (1) is changed.(Register is changed; WTCRL, WTCRH, SGDR, IPCP0, IPCP1, ROMM, LPMCR, WDTC, FMCS.)(Access is changed; ADCSH, ADCRL, ADCRH, SCR0, SIDR0/SODR0, SSR0, SCR1, SIDR1/SODR1, SSR1, TMR0/TMRLR0, TMR1/TMRLR1, SGCRH, LVRC, WDTC, WTC, FMCS.)

    639Table B.8-1 41 Transfer Instructions (Byte) is changed.(MOV @AL,AH/MOV @A,T → MOV @AL,AH)

    640Table B.8-2 38 Transfer Instructions (Word, Long Word) is changed.(MOVW @AL,AH/MOVW @A,T → MOVW @AL,AH)

    651Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) is changed.(SWAPW/XCHW A,T → SWAPW)

    Page Changes (For details, refer to main body.)

    xviii

  • CHAPTER 1 OUTLINE

    CHAPTER 1 OUTLINE

    This chapter describes features and provides the basic specification of the MB90420G/425G series.

    1.1 Product Outline

    1.2 Features

    1.3 Block Diagram

    1.4 Diagram Showing Package Dimensions

    1.5 Pin Assignment Diagram

    1.6 Description of Pin Functions

    1.7 Types of Input/Output Circuits

    1.8 Precautions for Device Handling

    1

  • CHAPTER 1 OUTLINE

    1.1 Product Outline

    This section gives an outline of MB90420G/425G series products.

    ■ Product Outline

    Table 1.1-1 gives an outline of MB90420G series products. Table 1.1-2 gives an outline ofMB90425G series products.

    Table 1.1-1 Outline of MB90420G Series Products

    Feature MB90V420G MB90F423GA MB90F423GC MB90423GA MB90423GC

    Product type Evaluation product Flash memory product Mask ROM product

    CPU F2MC-16LX CPU

    Clock 2 systems 1 system 2 systems 1 system 2 systems

    System clockOn-chip PLL clock multiplication scheme (×1, ×2, ×3, ×4, 1/2 for PLL stop) minimum instruction execution time 62.5 ns (4 MHz oscillation ×4)

    ROM External Flash ROM 128 Kbytes Mask ROM 128 Kbytes

    RAM 6 Kbytes

    CAN interface 2 channels

    Low-voltage/CPU operation detection reset

    Not used Used Not used Used Not used

    Package PGA-256 QFP100, LQFP100

    Emulator-dedicated power supply*

    Not used −

    *: Setting of dip-switch S2 for using the evaluation pod MB2145-507. For further information, refer to the "MB2145-507 Hardware Manual (Section 2.7 "Switching the Power Source" ) ".

    Table 1.1-2 Outline of MB90425G Series Products (1/2)

    Feature MB90F428GA MB90F428GC MB90427GA MB90427GC MB90428GA MB90428GC

    Product type Flash memory product Mask ROM product

    CPU F2MC-16LX CPU

    Clock 1 system 2 systems 1 system 2 systems 1 system 2 systems

    System clockOn-chip PLL clock multiplication scheme (✕1, ✕2, ✕3, ✕4, 1/2 for PLL stop) minimum instruction execution time: 62.5 ns (4 MHz oscillation ✕4)

    ROM Flash ROM 128 Kbytes Mask ROM 64 Kbytes Mask ROM 128 Kbytes

    RAM 6 Kbytes 4 Kbytes 6 Kbytes

    CAN interface 1 channel

    2

    Table 1.1-1 Outline of MB90420G Series Products is changed.(*1: Being developed is deleted.)

    Table 1.1-2 Outline of MB90425G Series Products is changed.(*1: Being developed is deleted.)

  • CHAPTER 1 OUTLINE

    Notes:

    • MB90V420G can be used as evaluation product for MB90420G/425G series.

    • For MB90420G/425G series other than MB90V420G, the initial state of the pin after reset is setto Output "L" for P70 to P77 and P80 to P87. For MB90V420G only, the initial state of the pinafter reset is set to high impedance for P70 to P77 and P80 to P87.

    Low-voltage/CPU operation detection reset

    Used Not used Used Not used Used Not used

    Package QFP100, LQFP100

    Emulator-dedicated power supply

    Table 1.1-2 Outline of MB90425G Series Products (2/2)

    Feature MB90F428GA MB90F428GC MB90427GA MB90427GC MB90428GA MB90428GC

    3

    Table 1.1-2 Outline of MB90425G Series Products is changed.(*1: Being developed is deleted.)

  • CHAPTER 1 OUTLINE

    1.2 Features

    This section describes the features of MB90420G/425G series products.

    ■ Features

    Table 1.2-1 indicates features of MB90420G/425G series products.

    Table 1.2-1 Features of MB90420G/425G Series Products (1/2)

    Function Feature

    16-bit input capture (4 channels)

    Detects rising edge, falling edge or both.16-bit capture register ×4Detecting a pin input edge latches the counter value of the 16-bit free-run timer and generates an interrupt request.

    16-bit reload timer (2 channels)Allows 16-bit reload timer operations (e.g., toggle output and one-shot output selectable) and event count function selection.

    Watch timer (main clock)

    Is directly driven by the oscillation clock.Supports the correction of oscillation deviations.Second/minute/hour registers allowing read/write operationsSignal interrupt

    16-bit PPG (3 channels)Output pin (×3), external trigger input pin (×1)Operation clock frequency: fcp, fcp/22, fcp/24, fcp/26

    Delayed interruptGenerates an interrupt for task switching.Interrupt requests to the CPU can be generated and canceled by software

    External interrupt (8 channels)8 independent channelsInterrupt source: Allowed selections are L --> H edge/H --> L edge/L level/H level.

    A/D converter

    10 bits or 8 bits resolution ×8 channels (input multiplex)Conversion time: 6.13 µs or less (fcp=16 MHz)External trigger activation allowed (P50/INT0/ADTG)Internal timer activation allowed (16-bit reload timer 1)

    UART(2 channels)

    Full-duplex double-buffer schemeSupports asynchronous/synchronous transfer (with start/stop bits).Selection of internal timer allowed as clock (16-bit reload timer 0)Asynchronous: 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bpsSynchronous: 500 kbps, 1 Mbps, 2 Mbps (when fcp=16 MHz)

    CAN interface *1

    Conforms to CAN specification version 2.0 part A and part B.Automatic retransmission is executed if an error occurs.Automatic transmission is executed in response to a remote frame.Supports data and multiple messages for prioritized 16 message buffers with ID.Flexible configuration of receiving filter:

    All bit compare/all bit mask/partial mask of two bits Supports up to 1 Mbps.CAN WAKEUP function (RX connected to INTO internally within the device).

    LCD controller / driver (1 channel)

    Segment driver and common driver directly drives LCD panel (LCD display).

    Low-voltage /CPU operation detection reset *2

    Automatically reset if low-voltage is detected.CPU operation detection function

    4

  • CHAPTER 1 OUTLINE

    Stepping motor controller (4 channels)

    high current output per channel ×4All synchronous channels, 8/10 bit PWM ×2

    Sound generator8-bit PWM signal is mixed with tone frequency from 8-bit reload counter.PWM frequency: 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (when fcp=16 MHz)Tone frequency: PWM frequency /2/ (reload value +1)

    Input/output portPush-pull output and Schmidt trigger inputProgrammable in units of individual bits as input/output or peripheral signal.

    Flash memory

    Supports automatic programming, Embedded Algorithm, write/delete/suspend deletion and restart deletion commands.Flag for indicating completion of algorithm processing.Flash writer made by Minato Electronics.Boot block configurationDelete can be executed in units of blocks.Block protection using the external programming voltage.

    *1: Two channels are built-in in the MB90420G series, one channel is built-in in the MB90425G series.*2: Mounted only in the MB90F423GA, MB90F428GA, MB90423GA, MB90427GA, MB90428GA, but not in the

    MB90F423GC, MB90F428GC, MB90423GC, MB90427GC, MB90428GC.

    Table 1.2-1 Features of MB90420G/425G Series Products (2/2)

    Function Feature

    5

  • CHAPTER 1 OUTLINE

    1.3 Block Diagram

    This section shows a block diagram of MB90420G/425G series products.

    ■ Block Diagram

    Figure 1.3-1 shows a block diagram of MB90420G/425G series products.

    Figure 1.3-1 Block Diagram

    RAM

    ROM

    Port 3

    F2 M

    C -

    16L

    X B

    US

    X0,X1 X0A,X1ARST

    ICU0/1/2/3

    PPG0/1/2

    Prescaler 0/1

    Port 5

    (8ch)P00/SIN0/INT4P01/SOT0/INT5P02/SCK0/INT6P03/SIN1/INT7P04/SOT1P05/SCK1/TRGP06/PPG0/TOT1P07/PPG1/TIN1

    P56/SGO/FRCKP55/RX0P54/TX0P53/INT3P52/INT2(/TX1) P51/INT1(/RX1)P50/INT0/ADTG

    P91, P90/SEG23, SEG22

    SEG11 to SEG0COM3 to COM0V3 to V0

    P47 to P40/SEG21 to SEG14

    Port 6

    (8ch)

    P67 to P60/AN7 to AN0AVCC/AVSSAVRH

    Port 8

    Port 7

    P77/PWM2M1P76/PWM2P1P75/PWM1M1P74/PWM1P1P73/PWM2M0P72/PWM2P0P71/PWM1M0P70/PWM1P0

    P87/PWM2M3P86/PWM2P3P85/PWM1M3P84/PWM1P3P83/PWM2M2P82/PWM2P2P81/PWM1M2P80/PWM1P2

    P10/PPG2P11/TOT0/WOTP12/TIN0/IN3P13/IN2P14/IN1P15/IN0 Port 4

    P37, P36/SEG13, SEG12

    UART 0/1

    Clock controlcircuit F2MC -16LX core

    CPU

    Sound generator

    CAN controller

    External interrupt

    Port 0

    Port 1

    Reload timer0/1

    Watch timer(main)

    Free-run timer

    InterruptcontrollerLow voltage/CPU operationdetect reset

    Stepping motor controller 0/1/2/3

    A/D converter

    Port 9

    LCDcontroller/driver

    Specification of evaluation device (MB90V420G)No built-in ROM provided.Built-in RAM has a capacity of 6 Kbytes.

    P57/SGA

    6

  • CHAPTER 1 OUTLINE

    Notes:

    • 2 channels and 1 channel of CAN interfaces are built-in in MB90420G and MB90425G seriesproducts, respectively.

    • Low-voltage/CPU operation detection reset is built-in in MB90F423GA, MB90F428GA,MB90423GA, MB90427GA, MB90428GA products only. It is not built-in in MB90F423GC,MB90F428GC, MB90423GC, MB90427GC, MB90428GC products.

    7

  • CHAPTER 1 OUTLINE

    1.4 Diagram Showing Package Dimensions

    Two types of packages are used for MB90420G/425G series products.This diagram showing package dimensions is for reference purposes only. For the formally correct version, contact us.

    ■ Package Dimensions (QFP100)

    Please confirm the latest Package dimension by following URL.http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

    100-pin plastic QFP Lead pitch 0.65 mm

    Package width ×package length

    14.00 × 20.00 mm

    Lead shape Gullwing

    Sealing method Plastic mold

    Mounting height 3.35 mm MAX

    Code(Reference)

    P-QFP100-14×20-0.65

    100-pin plastic QFP(FPT-100P-M06)

    (FPT-100P-M06 )

    C 2002 FUJITSU LIMITED F100008S-c-5-5

    1 30

    31

    50

    5180

    81

    100

    20.00±0.20(.787±.008)

    23.90±0.40(.941±.016)

    14.00±0.20(.551±.008)

    17.90±0.40(.705±.016)

    INDEX

    0.65(.026) 0.32±0.05(.013±.002)

    M0.13(.005)

    "A"

    0.17±0.06(.007±.002)

    0.10(.004)

    Details of "A" part

    (.035±.006)0.88±0.15

    (.031±.008)0.80±0.20

    0.25(.010)3.00

    +0.35–0.20+.014–.008.118

    (Mounting height)

    0.25±0.20(.010±.008)(Stand off)

    0~8°

    *

    *

    Dimensions in mm (inches).Note: The values in parentheses are reference values.

    Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.

    8

  • CHAPTER 1 OUTLINE

    ■ Package Dimensions (LQFP100)

    Please confirm the latest Package dimension by following URL.http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

    100-pin plastic LQFP Lead pitch 0.50 mm

    Package width ×package length

    14.0 × 14.0 mm

    Lead shape Gullwing

    Sealing method Plastic mold

    Mounting height 1.70 mm MAX

    Weight 0.65g

    Code(Reference)

    P-LFQFP100-14×14-0.50

    100-pin plastic LQFP(FPT-100P-M05)

    (FPT-100P-M05)

    C 2003 FUJITSU LIMITED F100007S-c-4-6

    14.00±0.10(.551±.004)SQ

    16.00±0.20(.630±.008)SQ

    1 25

    26

    51

    76 50

    75

    100

    0.50(.020) 0.20±0.05(.008±.002)

    M0.08(.003)0.145±0.055

    (.0057±.0022)

    0.08(.003)

    "A"

    INDEX.059 –.004

    +.008–0.10+0.20

    1.50(Mounting height)

    0~8°

    0.50±0.20(.020±.008)0.60±0.15

    (.024±.006)

    0.25(.010)

    0.10±0.10(.004±.004)

    Details of "A" part

    (Stand off)

    *

    Dimensions in mm (inches).Note: The values in parentheses are reference values.

    Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.

    9

  • CHAPTER 1 OUTLINE

    1.5 Pin Assignment Diagram

    This section presents the pin assignment diagram of MB90420G/425G series products.

    ■ Pin Assignment (QFP100)

    Figure 1.5-1 shows the pin assignment diagram for the plastic QFP100 type.

    Figure 1.5-1 Pin Assignment (QFP100)

    MD

    1M

    D0

    P52/IN

    T2 (/T

    X1)

    P51/IN

    T1 (/R

    X1)

    P67/A

    N7

    P66/A

    N6

    P65/A

    N5

    P64/A

    N4

    Vss

    P63/A

    N3

    P62/A

    N2

    P61/A

    N1

    P60/A

    N0

    AV

    ssP

    50/INT

    0/AD

    TG

    AV

    RH

    AV

    ccV

    3V

    2V

    1

    X0AX1AP57/SGARSTP56/SGO/FRCKP55/RX0P54/TX0DVssP87/PWM2M3P86/PWM2P3P85/PWM1M3P84/PWM1P3DVccP83/PWM2M2P82/PWM2P2P81/PWM1M2P80/PWM1P2DVssP77/PWM2M1P76/PWM2P1P75/PWM1M1P74/PWM1P1DVccP73/PWM2M0P72/PWM2P0P71/PWM1M0P70/PWM1P0DVSSP53/INT3MD2

    COM2COM3SEG0SEG1SEG2SEG3SEG4SEG5SEG6SEG7

    VssSEG8SEG9

    SEG10SEG11

    P36/SEG12P37/SEG13P40/SEG14P41/SEG15P42/SEG16P43/SEG17P44/SEG18

    VccP45/SEG19P46/SEG20P47/SEG21

    CP90/SEG22P91/SEG23

    V0

    MB90420G/425G Series

    TOP VIEW

    VssX

    0X

    1V

    ccP

    00/SIN

    0/INT

    4P

    01/SO

    T0/IN

    T5

    P02/S

    CK

    0/INT

    6P

    03/SIN

    1/INT

    7P

    04/SO

    T1

    P05/S

    CK

    1/TR

    GP

    06/PP

    G0/T

    OT

    1P

    07/PP

    G1/T

    IN1

    P10/P

    PG

    2P

    11/TO

    T0/W

    OT

    P12/T

    IN0/IN

    3P

    13/IN2

    P14/IN

    1P

    15/IN0

    CO

    M0

    CO

    M1

    81828384858687888990919293949596979899

    100

    123456789

    101112131415161718192021222324252627282930

    5049484746454443424140393837363534333231

    807978777675747372717069686766656463626160595857565554535251

    10

  • CHAPTER 1 OUTLINE

    ■ Pin Assignment (LQFP100)

    Figure 1.5-2 shows the pin assignment diagram for the plastic LQFP100 type.

    Figure 1.5-2 Pin Assignment (LQFP100)

    P57/S

    GA

    X1A

    X0A

    VssX

    0X

    1V

    ccP

    00/SIN

    0/INT

    4P

    01/SO

    T0/IN

    T5

    P02/S

    CK

    0/INT

    6P

    03/SIN

    1/INT

    7P

    04/SO

    T1

    P05/S

    CK

    1/TR

    GP

    06/PP

    G0/T

    OT

    1P

    07/PP

    G1/T

    IN1

    P10/P

    PG

    2P

    11/TO

    T0/W

    OT

    P12/T

    IN0/IN

    3P

    13/IN2

    P14/IN

    1P

    15/IN0

    CO

    M0

    CO

    M1

    CO

    M2

    CO

    M3

    P53/IN

    T3

    MD

    2M

    D1

    MD

    0P

    52/INT

    2 (/TX

    1)P

    51/INT

    1 (/RX

    1)P

    67/AN

    7P

    66/AN

    6P

    65/AN

    5P

    64/AN

    4V

    ssP

    63/AN

    3P

    62/AN

    2P

    61/AN

    1P

    60/AN

    0A

    Vss

    P50/IN

    T0/A

    DT

    GA

    VR

    HA

    Vcc

    V3

    V2

    V1

    V0

    P91/S

    EG

    23P

    90/SE

    G22

    RSTP56/SGO/FRCKP55/RX0P54/TX0DVssP87/PWM2M3P86/PWM2P3P85/PWM1M3P84/PWM1P3DVccP83/PWM2M2P82/PWM2P2P81/PWM1M2P80/PWM1P2DVssP77/PWM2M1P76/PWM2P1P75/PWM1M1P74/PWM1P1DVccP73/PWM2M0P72/PWM2P0P71/PWM1M0P70/PWM1P0DVss

    SEG0SEG1SEG2SEG3SEG4SEG5SEG6SEG7

    VssSEG8SEG9

    SEG10SEG11

    P36/SEG12P37/SEG13P40/SEG14P41/SEG15P42/SEG16P43/SEG17P44/SEG18

    VccP45/SEG19P46/SEG20P47/SEG21

    C

    MB90420G/425G series

    TOP VIEW

    767778798081828384858687888990919293949596979899100

    123456789

    10111213141516171819202122232425

    50494847464544434241403938373635343332313029282726

    747372717069686766656463626160595857565554535251

    11

  • CHAPTER 1 OUTLINE

    1.6 Description of Pin Functions

    This section describes the pin functions of MB90420G/425G series products.

    ■ Description of Pin Functions

    Table 1.6-1 describes the pin functions of MB90420G/425G series products.

    Table 1.6-1 Description of Pin Functions (1/4)

    Pin numberPin name

    I/O circuit type*5

    FunctionLQFP QFP

    80 82 X0A

    High-speed oscillation input pin

    81 83 X1 High-speed oscillation output pin

    78 80 X0AA

    Low-speed oscillation input pin *1

    77 79 X1A Low-speed oscillation output pin *2

    75 77 RST B Reset input pin

    83 85

    P00

    G

    General-purpose input/output port

    SIN0 Serial data input pin for UART ch.0

    INT4 External interrupt input pin for INT4

    84 86

    P01

    G

    General-purpose input/output port

    SOT0 Serial data output pin for UART ch.0

    INT5 External interrupt input pin for INT5

    85 87

    P02

    G

    general-purpose input/output port

    SCK0 Serial clock input/output pin for UART ch.0

    INT6 External interrupt input pin for INT6

    86 88

    P03

    G

    General-purpose input/output port

    SIN1 Serial data input pin for UART ch.1

    INT7 External interrupt input pin for INT7

    87 89P04

    GGeneral-purpose input/output port

    SOT1 Serial data output pin for UART ch.1

    88 90

    P05

    G

    General-purpose input/output port

    SCK1 Serial clock input/output pin for UART ch.1

    TRGExternal trigger input pin for 16-bit PPG ch.0 to ch.2

    12

  • CHAPTER 1 OUTLINE

    89 91

    P06

    G

    General-purpose input/output port

    PPG0 Output pin for 16-bit PPG ch.0

    TOT1 TOT output pin for 16-bit reload timer ch.1

    90 92

    P07

    G

    General-purpose input/output port

    PPG1 Output pin for 16-bit PPG ch.1

    TIN1 TIN input pin for 16-bit reload timer ch.1

    91 93P10

    GGeneral-purpose input/output port

    PPG2 Output pin for 16-bit PPG ch.2

    92 94

    P11

    G

    General-purpose input/output port

    TOT0 TOT output pin for 16-bit reload timer ch.0

    WOT WOT output pin for watch timer

    93 95

    P12

    G

    General-purpose input/output port

    TIN0 TIN input pin for 16-bit reload timer ch.0

    IN3 Trigger input pin for input capture ch.3

    94 to 96 96 to 98

    P13 to P15

    G

    General-purpose input/output port

    IN2 to IN0Trigger input pin for input capture ch.0 to ch.2

    97 to 100 99, 100, 1, 2COM0 to COM3

    I LCD controller / driver common output pin

    1 to 8, 10 to 13

    3 to 10, 12 to 15

    SEG0 to SEG11

    I LCD controller / driver segment output pin

    14, 15 16, 17

    P36, P37

    E

    General-purpose input/output port

    SEG12, SEG13

    LCD controller / driver segment output pin

    16 to 20, 22 to 24

    18 to 22, 24 to 26

    P40 to P47

    E

    General-purpose input/output port

    SEG14 to SEG21

    LCD controller / driver segment output pin

    26, 27 28, 29

    P90, P91

    E

    General-purpose input/output port

    SEG22, SEG23

    LCD controller / driver segment output pin

    34 36

    P50

    G

    General-purpose input/output port

    INT0 INT0 external interrupt input pin

    ADTG A/D converter external trigger input pin

    Table 1.6-1 Description of Pin Functions (2/4)

    Pin numberPin name

    I/O circuit type*5

    FunctionLQFP QFP

    13

  • CHAPTER 1 OUTLINE

    36 to 39, 41 to 44

    38 to 41, 43 to 46

    P60 to P67F

    General-purpose input/output port

    AN0 to AN7 A/D converter input pin

    45 47

    P51

    G

    General-purpose input/output port

    INT1 INT1 external interrupt input pin

    (RX1) *3 RX input pin for CAN interface 1

    46 48

    P52

    G

    General-purpose input/output port

    INT2 INT2 external interrupt input pin

    (TX1) *3 TX output pin for CAN interface 1

    50 52P53

    GGeneral-purpose input/output port

    INT3 External interrupt input pin for INT3

    52 to 55 54 to 57

    P70 to P73

    H

    General-purpose input/output port

    PWM1P0PWM1M0PWM2P0PWM2M0

    Output pin for stepping motor controller ch.0

    57 to 60 59 to 62

    P74 to P77

    H

    General-purpose input/output port

    PWM1P1PWM1M1PWM2P1PWM2M1

    Output pin for stepping motor controller ch.1

    62 to 65 64 to 67

    P80 to P83

    H

    General-purpose input/output port

    PWM1P2PWM1M2PWM2P2PWM2M2

    Output pin for stepping motor controller ch.2

    67 to 70 69 to 72

    P84 to P87

    H

    General-purpose input/output port

    PWM1P3PWM1M3PWM2P3PWM2M3

    Output pin for stepping motor controller ch.3

    72 74P54

    GGeneral-purpose input/output port

    TX0 TX output pin for CAN interface

    73 75P55

    GGeneral-purpose input/output port

    RX0 RX input pin for CAN interface 0

    Table 1.6-1 Description of Pin Fu