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Edition 5.0Jan. 2000
Fujitsu PLL Frequency Synthesizer
Evaluation Tool (Version 5.0)
User’s Manual
FUJITSU LIMITED
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PLL Evaluation tool (ver5.0)
CONTENTSCHAPTER 1 : HARDWARE DESCRIPTION
1.1. INTRODUCTION1.2. HARDWARE SETUP1.3. INTERFACE BOARD DESCRIPTION1.4. INTERFACE BOARD LAYOUT
CHAPTER 2 : SOFTWARE DESCRIPTION2.1.Windows 95 VERSION 2.1.1.STANDARD SYSNTHESIZER(except for MB15E/FxxSL series) 2.1.1.1. INTRODUCTION
2.1.1.2. USED ENVERNOMENT2.1.1.3. CONTENTS2.1.1.4. SET UP2.1.1.5. HOW TO USE THE PROGRAM
2.1.1.5.1. STARTING THE PROGRAM2.1.1.5.2. SETTING THE TEST CONDITIONS2.1.2.5.3. MEASUREMENT2.1.2.5.4. OTHERS
2.1.2.STANDARD SYSNTHESIZER(MB15E/FxxSL series) 2.1.2.1. INTRODUCTION
2.1.2.2. USED ENVERNOMENT2.1.2.3. CONTENTS2.1.2.4. SET UP2.1.2.5. HOW TO USE THE PROGRAM
CHAPTER 3 : EVALUATION BOARD DESCRIPTION3.1. OVERVIEW3.2. EVALUATION BOARD DESCRIPTION
3.2.1.MB1500EB013.2.2.MB1500EB01B3.2.3.MB1500EB023.2.4.MB1500EB113.2.5.MB1500EB123.2.6.MB1500EB133.2.7.MB1500EB13B3.2.8.MB1500EB143.2.9.MB1500EB163.2.10.MB1500EB16B
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PLL Evaluation tool (ver5.0)
CHAPTER 1. HARDWARE DESCRIPTION
1.1. INTRODUCTION
This evaluation tool is designed to demonstrate the operation of the FUJITSU MB15xx series PLL frequency
synthesizers. It will allow the user to investigate the operation capability of the IC and modify the loop parameters.
1.2. HARDWARE SETUP
This programming tool enables you to control FUJITSU PLL frequency synthesizers via a personal computer.
The personal computer is connected to the interface board via a parallel port. The programming software installed
generates signals to the interface board. Then, the signals are converted into control signals and sent to an IC on
the evaluation board.
Fig.1.1 Hardware constructure (image)
1.3. INTERFACE BOARD DESCRIPTION
Fig. 1.2 The interface board top view P/No. : MB1500EB00
Key board PC EvaluationBoard
InterfaceBoard
Programm Devicefile
Parallel Port
Connector
Ground
Delay control switch
Data output pins
Power source pins
Trigger switch
BNC connector
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PLL Evaluation tool (ver5.0)
Connectors
The personal computer and the interface board is connected with a cable. The connector should have 25-pin[
connector for the personal computer’s printer port and 36-pin connector for the interface port.
Trigger Switch
Logical level of the trigger signal can be switched by the trigger switch.
/Q : Active high Q : Active Low
Trigger Trigger
BNC Connector
This connector should be connected to a time interval analyzer. A trigger signal is output through this connector.
Delay Control Switch
The delay time between the trigger signal and the last LE signal outputs can be adjusted by the delay control switch.
Turning the white screw part, the delay time can be adjusted in the range from 5µs to 600µs.
Data Output Pin
Connect one side of the three wire (white, blue and yellow) connector to the data output pins on the interface board.
The other side is connected to the data input pins on the evaluation board.
Power Source Pin
Connect two wire (red and black) connector to the power source pins, and the other side to ground and Vcc
respectively. (Vcc = 3V to 5V (needs to be as same as supply voltage for the IC))
Ground
Connect to ground.
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PLL Evaluation tool (ver5.0)
1.4.INTERFACE BOARD LAYOUT
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PLL Evaluation tool (ver5.0)
CHAPTER 2. SOFTWARE DESCRIPTION
2.1. Windows95 VERSION
2.1.1. STANDARD SYNTHESIZERS (except for MB15E/FxxSL series)
2.1.1.1. INTRODUCTION
This program is designed to demonstrate the operation of the Fujitsu PLL frequency synthesizers. It will allow theuser to investigate the operation capability of the IC and modify the loop parameters.
2.1.1.2. USED ENVERNOMENT
OS: Windows95
2.1.1.3. CONTENTS
FiPLL.exe : Execution file to evaluate PLL series.fjPLL.ini : Initialization filefjpll.vxd : Virtual device driver
Applied deviceMB15E03, MB15E03L, MB15E05, MB15E05L, MB15E06, MB15E07, MB15E07L, MB1516A, MB1517A, MB15A01,MB15A02, MB15A16, MB15A17, MB15F02, MB15F02L, MB15F03, MB15F03L, MB15F04. MB15F05, MB15F05L,MB15B03, MB15U10, MB1551, MB15C03, MB15C03, MB15U32(The device file has to be housed in the directory "LIB" that locates under the same directory as FjPLL.exe does.Do not change a name of the directory "LIB".)
Only the device file for MB15U10, name its suffix as DT2.Name suffix for other device files as DT1.
2.1.1.4. SET UPThis programming tool consists of an interface board, a RF evaluation board and programming software.
1.Connect a parallel cable from the interface board to a printer port of a personal computer.
2.Connect the data input wire (three-wire; blue, yellow and white) from the interface board to
the Data, Clock and LE pins on the evaluation board. (Refer to CHAPTER 1.)
3.Insert the floppy disk into the floppy disk drive on the personal computer.
4.Change a disk drive from the current drive to the floppy disk drive.
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PLL Evaluation tool (ver5.0)
2.1.1.5. HOW TO USE THE PROGRAM
2.1.1.5.1. STARTING THE PROGRAM
Double clicking the FjPLL.exe on the windows explorer, and run the program. When you run the program using afloppy disk, please release a protector of the floppy disk. If a write protect is valid, the following message is appearedand the program does not run.
2.1.1.5.2. SETTING THE TEST CONDITIONSThe following window is opened on executing the FjPLL.exe.
1. Clicking exit program button, this program is quit.
2. Click the parallel port button and select a used port.
As is indicated below, you can select only valid parallel port.
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PLL Evaluation tool (ver5.0)
3. Select the device file and then click the button "OPEN".
The below shown parameter setting dialog window is opened. An usable parameter is different by the device file.Set each parameter.
Only for a programmable parameter, button becomes valid. Click each value. button and input data. If anyof the parameter is not filled in, you can not go to the next step.
FjPLL dialog Parameter setting
OSC Frequency input : ALT + O * Input a positive valueFrequency Range input : ALT + F * The value in the column "From" must be a positive number and less than that in the column "To".Channel Spacing input : ALT + S * Input a positive value.Current Channel input : ALT + C * Input an integer(0 or more)Hopping Channel input : ALT + H * The value in the column "From CH#" must be an integer(0 more) and less than the value in the column "To CH#".Number of repeat input : ALT + E * Input an integer(1 or more)
Note : As regards "Frequency Range" value, in the case that the display of data and real data differ, please confirm the value. The value be inputed in conformity with the calculation "[(MxN)+A] x fr(channel spacing)".
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PLL Evaluation tool (ver5.0)
2.1.1.5.3. MEASUREMENT
After test conditions are entered, the measurement can be done by sending the serial data to the testing sample
via the interface board.
Hopping enable progress -- ALT + E
Hopping is repeated at designated time by "Number of repeat"
It can be cancelled using a space key.
Click the button "Output current Ch Data", then the value of the present channel is automatically calculated andoutput through the port. Click the button "Output Next Ch Data", then the value of the next channel is automaticallycalculated and output through the port.
In the both cases, serial data and an trigger is output.
If the calculation is failed, the PLL Frequency Hopping mode can not be selected. Set parameters correctly.
2.1.1.5.4. OHTERS
When any of OSC Frequency, Frequency Range and Channel Spacing is changed, the PLL Frequency Hoppingmode can not be selected. In that case, click the button "Output Current Ch Data".
There is not a function to save the set data.
Certainly house the device files in the LIB directory that locates in the same directory as FjPLL.exe.
Do not change the name of LIB directory.
Only the device file for MB15U10, name its suffix as DT2. Name suffix for other device files as DT1.
Apply DOS 8.3 type for the name of the device file.
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PLL Evaluation tool (ver5.0)
2.1.2. STANDARD SYNTHESIZERS (MB15E/FxxSL/F7xSP series)
2.1.2.1. INTRODUCTION
This program is designed to demonstrate the operation of PLL(MB15E/FxxSL series). It will allow the user toinvestigate the operation capability of the IC and modify the loop parameters.
2.1.2.2. USED ENVERNOMENT
OS: Windows95
2.1.2.3. CONTENTS
FiPLL.exe : Execution file to evaluate PLL series. MB15ExxSL series -- version. 3.4.1
MB15FxxSL,F7xSP series -- version 3.3.2fjPLL.ini : Initialization filefjpll.vxd : Virtual device driver
Applied deviceVersion 3.4.1 -- MB15E03SL, MB15E05SL, MB15E07SL, Version 3.3.2 -- MB15F02SL, MB15F03SL, MB15F07SL, MB15F08SL
(The device file has to be housed in the directory "LIB" that locates under the same directory as FjPLL.exe does.Do not change a name of the directory "LIB".).
2.1.2.4. SET UPThis programming tool consists of an interface board, a RF evaluation board and programming software.
1.Connect a parallel cable from the interface board to a printer port of a personal computer.
2.Connect the data input wire (three-wire; blue, yellow and white) from the interface board to
the Data, Clock and LE pins on the evaluation board. (Refer to CHAPTER 1.)
3.Insert the floppy disk into the floppy disk drive on the personal computer.4.Change a disk drive from the current drive to the floppy disk drive
2.1.2.4. HOW TO USE THE PROGRAMIt conforms to chapter 2.1.1.5.
The bit configuration differs from MB15E/Fxx and MB15E/FxxL series.
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PLL Evaluation tool (ver5.0)
3.EVALUATION BOARD DESCRIPTION
3.1. OVERVIEW
Some synthesizers are pin compatible or similar pin assignment, so that an evaluation board is used for several
PLLs. The below table shows PLL part number and corresponding evaluation board numbers.
Table.1 P/No. of synthesizers and corresponding Evaluation board.
There are some components attached on a board. They are used for every synthesizers in common, and not so much influenceto loop characteristics (except for low pass filter components.) Accordingly, additional components such as VCO, a referenceoscillator, optimized loop filter etc. should be properly arranged by customers according to application.
Part No PKG type Eval. board No. Part No. PKG type Eval. board No.
MB15Axx series MB15Fxx series
MB15A01/A02/A03 SSOP-16 MB1500EB01 MB15F02/
F02L/F02SL SSOP-16 MB1500EB13
MB1516A SSOP-16 MB1500EB01 Bump Chip Carrier-16 MB1500EB13B
MB15A16 SSOP-16 MB1500EB01 MB15F03/F03L/F03SL
SSOP-16 MB1500EB13
MB1517A SSOP-16 MB1500EB01 Bump Chip Carrier-16 MB1500EB13B
MB15A17 SSOP-16 MB1500EB01 MB15F06 SSOP-16 MB1500EB13
MB15Bxx series MB15F07SL SSOP-16 MB1500EB13
MB15B01 SSOP-20 MB1500EB11 Bump Chip Carrier-16 MB1500EB13B
MB15B03 SSOP-16 MB1500EB13 MB15F08SL SSOP-16 MB1500EB13
MB15B11/B13 SSOP-20 MB1500EB11 Bump Chip
Carrier-16 MB1500EB13B
MB15Exx series MB15Uxx series
MB15E03/E03L/E03SL
SSOP-16 MB1500EB01 MB15U10 SSOP-20 MB1500EB12
Bump Chip Carrier-16 MB1500EB01B MB15U32 SSOP-20 MB1500EB14
MB15E05/E05L/E05SL
SSOP-16 MB1500EB01 MB15Cxxx series
Bump Chip Carrier-16 MB1500EB01B MB15C101 SSOP-8 MB1500EB02
MB15E06 SSOP-16 MB1500EB01 Bump Chip Carrier-16 MB1500EB02B
MB15E07/E07L/E07SL
SSOP-16 MB1500EB01 MB15C103 SSOP-8 MB1500EB02
Bump Chip Carrier-16 MB1500EB01B Bump Chip
Carrier-16 MB1500EB02B
MB15F7xSP series
MB15F72SP/F73SP/F78SP
TSSOP-20 MB1500EB16
Bump Chip Carrier-20 MB1500EB16B
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PLL Evaluation tool (ver5.0)
3.2. EVALUATION BOARD DESCRIPTION3.2.1 MB1500EB01
Fig.3.1 MB1500EB01 circuit image
Table.2 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 1000pF 9 R1 18Ω
2 C2 0.1µF 10 R2 18Ω
3 C3 0.1µF 11 R3 18Ω
4 C4 1000pF 12
5 C5 0.1µF 13
6 C’1 10µF 14
7 C’2 10µF 15
8 C’3 10µF 16
OSCin
OSCout
Vp
Vcc
Do
GND
(LD or Xfin)
fin
φR
φP
fout or LD/fout
NC or ZC
(FC or PS)
LE
Data
Clock
1
2
4
5
6
7
8
3
16
15
13
12
11
10
9
14
VCO
VVCO
Vp
Vcc Vcc
C1
SW
from a
connector
+
-
+
-
+
-
VCO output
From an
oscillator
C2
C3
C5
C4
R1
R2 R3
C’1
C’2
C’3
LPF
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PLL Evaluation tool (ver5.0)
Fig.3.2 MB1500EB01 board layout
(Top view)
(Bottom view)
Vcc
Vp
VCO
SW(PS)
13pin
OSCIN
Vvco
SW(PS)
LEDataClk
LPF
Connectordirection
Three pins
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PLL Evaluation tool (ver5.0)
3.2.2 MB1500EB01B
Fig.3.3 MB1500EB01B circuit image
Table.2 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 1000pF 9 R1 18Ω
2 C2 0.1µF 10 R2 18Ω
3 C3 0.1µF 11 R3 18Ω
4 C4 1000pF 12
5 C5 0.1µF 13
6 C’1 10µF 14
7 C’2 10µF 15
8 C’3 10µF 16
OSCin
OSCout
Vp
Vcc
Do
GND
(LD or Xfin)
fin
φR
φP
fout or LD/fout
NC or ZC
(FC or PS)
LE
Data
Clock
1
2
4
5
67 8
3
16 15
13
12
11
10
9
14
VCO
VVCO
Vp
VccVcc
C1
SW
from a
connector
+
-
+
-
+
-
VCO output
From an
oscillator
C2
C3
C5
C4
R1
R2 R3
C’1
C’2
C’3
LPF
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PLL Evaluation tool (ver5.0)
Fig.3.4 MB1500EB01B board layout
(Top view)
(Bottom view)
Vcc
Vp
VCO
SW(PS)
13pin
OSCIN
Vvco
SW(PS)
LEDataClk
LPF
Connectordirection
Three pins
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PLL Evaluation tool (ver5.0)
3.2.3 MB1500EB02
Fig.3.5 MB1500EB02 circuit image
Table.3 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 0.1µF 5 R1 18Ω
2 C2 1000pF 6 R2 18Ω
3 C3 1000pF 7 R3 18Ω
4 C’1 10µF
Vcc
Do
GND
fin
OSCin
LD
fout
Div
1
2
4
3
8
7
5
6
VCO
VccC1
from a TCXO
LPF
C3
C2
C’1
-
+
R1 R2
R3
Vcc
SW
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PLL Evaluation tool (ver5.0)
Fig.3.6 MB1500EB02 board layout
(Top view)
(Bottom view)
Vcc
VCO
LD
Div
Vvco
SW
LPF
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PLL Evaluation tool (ver5.0)
3.2.4 MB1500EB11
Fig.3.7 MB1500EB11 circuit image
Table.4 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 1000pF
2 C2 1000pF
3 C3 0.1µF
4 C4 0.1µF
5 C5 0.1µF
6 C6 0.1µF
7 C7 1000pF
OSCin
OSCout
fin1
Vcc1
fr
LD1
(BSC1 or Vp1)
Do1
Data
LE
fin2
Vcc2
fp
LD2
(BSC2 or Vp2)
Do2
1
2
4
5
6
7
8
3
16
15
13
12
11
20
9
14VCO
VVCO
Vcc
C1from a
connector
From an
oscillator
C3
C4
10
19
18
17
GND
BS1 BS2
Clock
C6Vcc
LPF
VCO output
VCO
VVCO
C5
LPF
VCO output
C2 C7
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PLL Evaluation tool (ver5.0)
Fig.3.8 MB1500EB11 board layout
(Top view)
(Bottom view)
Vcc1
Vvco
LD Do fr LD Do fr1 2
Vcc2
Vvco
VCO
LPF LPF
fr Do LD fr LDDo
LE Clk
Connectordirection
Three pins
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PLL Evaluation tool (ver5.0)
3.2.5 MB1500EB12
Fig.3.9 circuit image
Table.5 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 0.1µF 11 R2 2.2kΩ
2 C2 0.1µF 12 R3 51Ω
3 C3 0.1µF 13 R4 51Ω
4 C4 1000pF 14 R5 51Ω
5 C5 1000pF 15 R6 2.2kΩ
6 C6 0.1µF 16 R7 62kΩ
7 C7 1000pF 17 R8 15kΩ
8 C8 0.1µF 18 R9 12kΩ
9 C9 0.1µF 19 R10 5.1kΩ
10 R1 2.2kΩ
P2/fp2
Do1
VDD1
PS
fin1
DGND
OSCin
P3/fr2
P0/LD
Vp
Do2
AGND
fin2
VDD2
LE
Data
1
2
4
5
6
7
8
3
16
15
13
12
11
20
9
14
VDD
from a
connector
From an
oscillator
C3
10
19
18
17
P1/fp1
OSCout Clock
ISET
C6VDD
VCO
VVCO
C8
VCO output
VCO
VVCOC2
LPF
VDD
VDD
VDD
SW1
VDD
Vp
C9 SW5
LPF
R1
R2
R3
R4
R10
R6
R5
C4
C5
C7
SW4 SW2
SW3
R9R8R7
C1
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PLL Evaluation tool (ver5.0)
Fig.3.10 MB1500EB12 board layout
(Top view)
(Bottom view)
SW4 SW5
SW2 SW3
SW(PS)
VDD
VDD
Vvco
Vvco
Vp
VCO
LPF
Do2
LPF
Do1
LEClk
LD
VCO
SW(PS)
LEClk
Three pins
Connectordirection
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PLL Evaluation tool (ver5.0)
3.2.6 MB1500EB13
Fig.3.11 MB1500EB13 circuit image
Table.6 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 0.1µF 15 R3 18Ω
4 C4 0.1µF 16 R4 18Ω
5 C5 1000pF 17 R5 18Ω
6 C6 0.1µF 18 R6 51Ω
7 C7 0.1µF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C’1 10µF 21 R9 18Ω
10 C’2 10µF
11 C’3 10µF
12 C’4 10µF
OSCin
GNDIF
fin1
VccIF
LD/fout
PSIF
DoIF
Data
LE
finRF
VccRF
XfinRF
PSRF
DORF
1
2
4
5
6
7
8
3
12
11
9
16
10
VCO
VVCO
Vcc
C1from a
connector
From an
oscillator
C3
C4
15
14
13
GNDRF Clock
C6
Vcc
LPF
VCO output
VCO
VVCO
C7
VCO output
R2 C8
SW
LPF
C5
R1
C2
R6
SWC’2-
+
-
+C’1 -
+C’4
-
+
C’3
R3
R5
R4 R8 R9
R7
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PLL Evaluation tool (ver5.0)
Fig.3.12 MB1500EB13 board layout
(Top view)
(Bottom view)
Vvco
VCC
SW(PS)
SW(PS)
Do DoVCC
VCO VCO
Vvco
CKLE
IF RF
LE Clk
SW(PS)
LPF LPF
Connectordirection
Three pins
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PLL Evaluation tool (ver5.0)
3.2.7 MB1500EB13B
Fig.3.13 MB1500EB13B circuit image
Table.7Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 0.1µF 15 R3 18Ω
4 C4 0.1µF 16 R4 18Ω
5 C5 1000pF 17 R5 18Ω
6 C6 0.1µF 18 R6 51Ω
7 C7 0.1µF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C’1 10µF 21 R9 18Ω
10 C’2 10µF
11 C’3 10µF
12 C’4 10µF
OSCin
GNDIF
fin1
VccIF
LD/fout
PSIF
DoIF
Data
LE
finRF
VccRF
XfinRF
PSRF
DORF
1
2
4
5
6
7
8
3
12
11
9
16
10
VCO
VVCO
Vcc
C1from a
connector
From an
oscillator
C3
C4
15
14
13
GNDRF Clock
C6
Vcc
LPF
VCO output
VCO
VVCO
C7
R2 C8
SW
LPF
C5
R1
C2
R6
SWC’2-
+
-
+C’1 -
+C’4
-
+
C’3
R3
R5
R4 R8 R9
VCO
R7
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PLL Evaluation tool (ver5.0)
Fig.3.14 MB1500EB13B board layout
(Top view)
(Bottom view)
Vvco
VccDo Do
VCOVCO
ClkLE
Vvco
Vcc
LEClk
LPF LPF
SW(PS) SW(PS)
Connectordirection
Three pins
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PLL Evaluation tool (ver5.0)
3.2.8 MB1500EB14
Fig.3.15 MB1500EB14 circuit image
Table.8 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 0.1µF 13 R1 51Ω
2 C2 0.1µF 14 R2 18Ω
3 C3 0.1µF 15 R3 18Ω
4 C4 1.0nF 16 R4 18Ω
5 C5 1000pF 17 R5 51Ω
6 C6 1.0nF 18 R6 2KΩ
7 C7 0.1µF 19 R7 51Ω
8 C8 0.1µF 20 R8 18Ω
9 C9 0.1µF 21 R9 18Ω
10 C10 0.1µF 22 R10 18Ω
11 C11 1.0nF
12 C12 1000pF
OSCin
GNDIF
VccIF
LD/fout
Data
LE
finRF
VccRF
XfinRF
DORF
1
2
4
5
6
7
8
3
16
15
13
20
14
VCO
VVCO
C1
from a
connector
From an
oscillator
C3C4
19
18
17GNDRF
Clock
C6
Vcc
LPF
VCO output
VVCO
C7
R2
C8
LPF
C12
R1
C2
R6
R5
R4
R8
R9 R10
VCOR7
9 12
10 11
VpRF
GNDRF
GNDRF
GNDRF
XfinIF
finIF
DOIF
VpIF
C5R3
C11
C9
VCO output
C10
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PLL Evaluation tool (ver5.0)
Fig.3.16 MB1500EB14 board layout
(Top view)
(Bottom view)
LEClk
VccVp Vcc Vp
VCO VCO
Vvco
Vvco
LPF LPF
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PLL Evaluation tool (ver5.0)
3.2.9 MB1500EB16
Fig.3.17 MB1500EB16 circuit image
Table.9 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 10µF 15 R3 18Ω
4 C4 10µF 16 R4 18Ω
5 C5 10µF 17 R5 18Ω
6 C6 10µF 18 R6 51Ω
7 C7 1000pF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C9 1000pF 21 R9 18Ω
10 C10 10µF 22 R10 18Ω
11 C11 10µF 23 R11 18Ω
24 R12 18Ω
VpIF
finRF
Clock
LD/fout
VpRF
PSRF
GNDIF
OSCIN
VccIF
finIF
1
2
4
5
6
7
8
3
16
15
13
20
14VCO
VVCOC3
from a
connector
From an oscillator
C10
C1
19
18
17XfinIF
C9
LPF
output
VVCO
R9
LPF
R1
R6
R7
R12 R10
R11
VCO
R2
9 12
10 11
GND
PSIF
DoIF
VccRF
GNDRF
XfinRF
LE
Data
C2R8
C8 output
C11
C4
DoRF
C5
C7
SW
SW C6
29
PLL Evaluation tool (ver5.0)
Fig.3.18 MB1500EB16board layout
(Top view)
(Bottom view)
OSCin
VCO
LED
ataC
LK
LED
ataC
LK
VccIF VpIF LD/fout VpRF VccRF
RF Block
VCO
LPF
IF Block
LPF
30
PLL Evaluation tool (ver5.0)
3.2.10 MB1500EB16B
Fig.3.19 MB1500EB16B circuit image
Table.10 Components list on the evaluation boardNo. Symbol Value No. Symbol Value
1 C1 1000pF 13 R1 51Ω
2 C2 1000pF 14 R2 51Ω
3 C3 10µF 15 R3 18Ω
4 C4 10µF 16 R4 18Ω
5 C5 10µF 17 R5 18Ω
6 C6 10µF 18 R6 51Ω
7 C7 1000pF 19 R7 18Ω
8 C8 1000pF 20 R8 18Ω
9 C9 1000pF 21 R9 18Ω
10 C10 10µF 22 R10 18Ω
11 C11 10µF 23 R11 18Ω
24 R12 18Ω
VpIF
finRF
Clock
LD/fout VpRF
PSRF
GNDIF
OSCIN
VccIF
finIF
1
2
4
5
6 7 8
3
16
15
13
20
14VCO
VVCO
C3
from aconnector
From an oscillator
C10
C9
19 18 17
XfinIF
C1
LPF
output
VVCO
R9
LPF
R6
R1
R7
R12 R10
R11
VCO
R2
9
12
10 11
GND
PSIF
DoIF
VccRF
GNDRF
XfinRF
LE
Data
C2
R8C8 output
C11
C4DoRF
C7
SW
SWC6
C5
31
PLL Evaluation tool (ver5.0)
Fig.3.20 MB1500EB16board layout
(Top view)
(Bottom view)
VCO
OSCin
VCO
LED
ataC
LK
RF Block
LPF
VccIF VpIF LD/fout VpRF VccRF
IF Block
LPF