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Full Chip Analysis Chung-Kuan Cheng Computer Science and Engineering Department University of California, San Diego La Jolla, CA 92093-0114 [email protected]

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Page 1: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

Full Chip Analysis

Chung-Kuan ChengComputer Science and Engineering Department

University of California, San DiegoLa Jolla, CA 92093-0114

[email protected]

Page 2: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

2

Outlines

I. IntroductionII. Circuit Level AnalysisIII. Logic Level Analysis

I. Timing AnalysisII. Functional Analysis

IV. Mixed Signal AnalysisV. Research DirectionsVI. Conclusion

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3

I. Introduction

1. Trends of On-Chip Technologies2. Statistics About Design Flaws3. Spectrum of Analysis

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I.1 Trends of On-Chip Technologies

System:Huge Numbers of Devices and Wires

Power/Ground Distribution:Low Voltage, High Current

Wires: Lateral Coupling, Fragmented ParasiticsDevices: Modeling, NoiseMixed Signal Design: RF+Analog+Digital

Page 5: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

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Page 6: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

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Page 7: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

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Power/Ground Distribution (ITRS)

1,035982932885Off-ChipFreq(MHz)

2,0001,8571,7241,600On-ChipFreq(MHz)

160150140130MaxPower

1.21.21.51.5SupplyVoltage(V)

2005200420032002

Lower V margin: Higher I & Inductance x Freq.

Page 8: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

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Page 9: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

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Flip Chip Dynamic Effects

F:MHz IRStatic vs.DynamicRi(t) Ldi/dt

9.9 mV

17.3 mV

1.2 mV

16.2 mV

29.3 mV

12.3 mV

19.3 mV

36 mV

28.5 mV

22 mV

38.8 mV

41.6 mV

0.5%1.02%

1.08%2.77%

1.6%5.37%

2.2%8.0%

DynamicTotal

18.5 mV

1.8

1.5

1.2

1.0

41.6 mV

64.5 mV

80.4 mV

250

500

750

1,000

Static DynamicVdd

Courtesy of Apache

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Wire-bond Dynamic Effects

IR R i(t) Ldi/dt

103 mV

147 mV

3 mV

181 mV

275 mV

13 mV

200 mV

276 mV

75 mV

5.7%8.3%

12% 19.2%

16.6%29.2%

DynamicTotal

150 mV

1.8

1.5

1.2

288 mV

351 mV

133

250

400

Static Dynamic Static vs.Dynamic

F:MHz Volt

Courtesy of Apache

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Page 12: Full Chip Analysis41.6 mV 64.5 mV 80.4 mV 250 500 750 1,000 Static Dynamic Vdd Courtesy of Apache 10 Wire-bond Dynamic Effects IR R i(t) Ldi/dt 103 mV 147 mV 3 mV 181 mV 275 mV 13

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Increasing System Complexity

Courtesy of Mentor

RF front end

DSP

Memory

Complexconverters

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I.2 Statistics about Design FlawsPercent of Total Flaws Fixed in IC/ASIC Designs Having Two or More Silicon Spins

2%

3%

4%

4%

5%

5%

7%

12%

13%

47%

0% 10% 20% 30% 40% 50%

Other flaws

IR Drops

Mixed-Signal Interface

Power

Race Condition

Clocking

Yield

Noise

Slow Path

Logical or Functional

Collett Intl. 2000 Survey

4%13%

17%17%

20%21%

23%25%

28%29%

35%67%

0% 10% 20% 30% 40% 50% 60% 70% 80%

Other flawsFirmware

PowerRace Condition

IR DropsMixed-Signal Interface

YieldClocking

Slow PathNoise

Analog CircuitLogical or Functional

Collett Intl. 2001 Survey

Logical or FunctionalAnalog NoiseSlow PathMixed-signal interfaceClock, Power/GroundFirmware

Logical or FunctionalSlow PathNoise

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I.3 Spectrum of Analysis

RTLGateSwitchesTimingBehaviorElectrical

System

LogicCircuitDevice

Physics EngineeringEE CS

Circuit theoryAlgorithmsDatabaseProgramming

Extraction

PrecisionMath DiscreteComplex, Real

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I.3 Spectrum of Analysis(flow)

System

Software Hardware

Floorplan

Logic

Layout

Library

IP blocks

Analog

Architect

Chip

FunctionTimingCircuit Anal.

emulationpowerclock

critical paths

function

characterization

freq

power noise

global wirescross talk

mixed signal

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I.3 Spectrum of Analysis(coverage)

Circuit Size

Coverage

Circuit Analysis

Logic: Static Timing (sign off)

Logic: FunctionalMixed Signal

Spice Hspice

ASX EldoApache

NassdaIota

CadenceSynopsysMentor

Celestry

CadenceSynopsysMentor

Axis

IBMAptix

CadenceSynopsys Mentor

MentorCadenceSynopsys

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I.3 Spectrum of Analysis(trend)

Layout Dominated AnalysisPower/Ground, ClockWiresPre-layout, Post-layout

Layout Oriented AnalysisEE + CS

EE=> CS High ComplexityCS=>EE Deep Submicron EffectAccuracy and Efficiency

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II. Circuit Level Analysis

1. Circuit Analysis Advancement2. Circuit Analysis Techniques3. Examples4. Tasks

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1st Generation (SPICE) 2nd Generation (Fast SPICE) Next Generation (HSIM)

Circuit Size

Memory Usage

CPU Time

512M Bytes

Circuit Size

2 hrs300M elements

Circuit Size

Memory Usage

CPU Time

512M Bytes

Circuit Size

2 hrs

300M elements

Circuit Size

Circuit Size

Memory Usage

CPU Time

1G Bytes

2M elements20 hrs

Circuit Size

Circuit Size

Memory Usage

CPU Time

Bytes

20 hrs

2M elements

Circuit Size

Memory Usage

CPU Time

100MBytes

100K elements

100 hrs

Circuit Size

Circuit Size

Memory Usage

CPU Time

100 hrs

Circuit Size

100K elements

II.1 Circuit Analysis Advancement

Courtesy of Nassda

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II.2 Circuit Analysis Techniques

Memory: Hierarchical DatabaseCircuit Size: Parasitic ReductionDevice Complexity: Table ModelSimulation:

Backward Euler, Trapezoidal IntegrationHierarchical FlowEvent Driven (ignoring miller effect)Mixed Rate, Multiple step sizes (partition)

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525K

51K

121K

13M

473M

Total Elements

0.37111MBAnalog(119K, 175K, 232K,0)

0.2115MBPLL(2K, 8K, 23K, 0)

1.1142MBD/A(9K,65K,47K,0)

0.69195MBMemory B(3.1M, 5.4M, 4.5M, 88)

1.65775MBMemory A(159M, 159M, 155M,0)

CPU Time (hrs)

MemoryUsage

Circuit Type(#MOS, #R,#C,#L)

II.3 Examples (HSIM)

Courtesy of Nassda

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II.4. Tasks

Convergence

Matrix SolverIntegration Partition

Hierarchy DatabaseInput Patterns

EE CSSpeed

Accuracy

Circuit Red.Device Mod.

Event DrivenHierarchical Flow

Math

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III. Logic Level Analysis

1.Separation of Timing and Function2.Static Timing Analysis

Algorithms, Gate Models, Path, Cross Talks

3.Functional AnalysisEvent Driven, Cycle Based

4.Tasks

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III.1 Separation of Timing and Function

FunctionalAnalysisSimple timing

model

Timing Analysis

Input vectordriven

Inputindependent

Slew, RC treecross talk

Function +Timing

High Complexity!

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III.2 Static Timing Analysis

i. Algor.: Shortest and Longest Paths Searchii. Gate Model:

• Logic: Unate, Binate Signal Propagations• Timing: functions of Input Slope and Output Load

iii. Path Model:• Logic: False Path, Multiple Cycle Path, Cycles of

Combinational Logic, Multiple Clock Frequencies• Timing: RC Tree

iv. Cross Talks: Timing Window, ATPGv. Tasks

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III.2.i Algor.: Path Search

ArrivalTime,Slew Rate

Required Arrival Time

Static Timing Analysis: Worst Case Analysis, Independent of Input Patterns

0->1 slew rate window1->0 slew rate window

0->1 arrival time window1->0 arrival time window

PI1

PI2

PI3

A

G

F

B

H

E

C

D

J PO

Longest &Shortest Paths

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III.2.I Algor: Path Search(cont)

0/0

0/0

0/0

1/2PI1

PI2

PI3

A

G

F

B

H

E

C

D

J PO3

21

2 2

1

1

2

3 21

23

2

23/3

2/4min/max

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III.2.I Algor: Path Search(cont)

aminj, amaxj

amini,amaxidji

amini=minj aminj+dji

amaxi=maxj amaxj+dji

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III.2i Algor.: Path Search

PI1

PI2

PI3

A

G

F

B

H

E

C

D

J PO3

21

2 2

1

1

2

3 21

23

2

2

0/0

0/0

0/0

1/2

3/3

2/4

4/5 6/7

4/4

4/6 6/8

6/10 8/12

min/max Longest: PI2,G,F,E,D,J,POShortest: PI2,G,H,J,PO

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III.2.ii Gate Logic Model: Unate & Binate Signals

a y

a y

a yNAND

Unateness: a 0->1 => y 1->0

XNOR

Binateness: a 0->1 => y 0->1 & 1->0

BDD

Check unateness based on BDD

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III.2.ii Gate Timing Model

Slew rate of y Delay of y

Slew rate of a Slew rate of a

CeffCeff

a y

Ceff

Interconnect

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III.2.iii Path Logic Model: False Path

4 bit adder 4 bit adder c0c4c8

p[0,3]

y

Carry skip adderz

101101001111

C0=11

P[0:3]=110000 Z=1

+

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III.2.iii Path Logic Model: False Path

False path: c0->y->c4 ->c8Assumption: z->c4 ->c8 derives results faster

If we erase all false paths, we can identify the true critical paths and the corresponding input patterns

4 bit adder 4 bit adder c0c4c8

p[0,3]

y

Carry skip adderz

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III.2.iii Path Logic Model: False Path

False path b->c->d->e

3

10

410

2

a

b

c d

e

f

3,10 7,14

17,24

16

red+red=>redred+blue=>blueblue +blue=>blue

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III.2.iv Cross Talk

WCN: worst-case noise: Delay & GlitchNoise with maximum

pulse heightFixed circuit structure and parametersFixed transition time of input signalsVariable arrival time of input signals

WCN

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Aggressor / Victim Input Victim Output

III.2.iv Cross Talk: Timing Window

P1

P2

P3

P4

P5

Aligned arrival time Skewed peak noise

A1

A2

A3

A4

V0

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37Aggressor Alignment WITHOUT Timing Constraints

III.2.iv Cross Talk: Timing Window

Skewed arrival time Aligned peak noise

Victim Output

P1

P2

P3

P4

P5

A1

A2

A3

A4

V0Sweep line

Aggressor / Victim Input

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38Aggressor Alignment WITH Timing Constraints

III.2.iv Cross Talk: Timing Window

Victim Output

A1

A2

A3

A4

V0

P1

P2

P5

Sweep Line

Aggressor / Victim Input

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III.2.iv Cross Talk: Effective Timing Window

Timing window for aggressor input

Earliest arrivaltime

Timing window for victim output

Latest peak noiseoccurring time

aT bTLaT R

bT at btLat

Rbt

maxV

iP

aT bTiA

Latest arrival time

at btiP

Earliest peak noise occurring time

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Aggressor Alignment with Timing Constraints -- Reformulation

A1

A2

A3

A4

V0

(a) Original timing window (b) Shifted timing window

Old Sweep Line New Sweep Line

(c) Expanded timing window

New Sweep Line

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III.2.v Tasks

Path model: special cases

ATPG

Path search in hierarchy

Gate model: power, noise

Path model: RCLK reduction

Cross talk

Timing window+pattern

EE CSSpeed

Accuracy

Math

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III.3 Logic Level: Functional Analysis

i. Functional Analysis Techniquesii. Event Driven Analysisiii. Cycle Based Analysisiv. Tasks

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III.3.i Functional Analysis Techniques

Event Driven SimulationVCS, Verilog-XL, VSS, ModelSim

Cycle Based SimulationFrontline, Speedsim, Cyclone

Domain Specific SimulationSPW, COSSAP

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III.3.ii Event Driven Analysis

Event WheelMaintains schedules of eventsEnables sub-cycle timing

AdvantagesTiming accuracyGood Debug CapabilityHandles asynchronous

DisadvantagesPerformance

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III.3.iii Cycle Based Analysis

RTL DescriptionAll gates evaluated every cycleSchedule is determined at compile timeNo timingNo asynchronous feedback, latchesRegression PhaseHigh PerformanceHigh Capacity

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III.3.iv Tasks

Pattern generationDynamic timing model

coverage

Hardware acceleration

EE CSSpeed

Accuracy

Math

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IV. Mixed Signal Analysis

RF front-endRF Simulator

Analog IPVHDL-AMS

Verilog-AMS

DSPHDL

VHDL/Verilog

EmbeddedMemoriesHierarchical Fast SPICE

Complex AnalogTraditional

SPICE

Custom Logic & Mixed-SignalFast SPICE

Single-Kernel simulator for full-chip SoC Verification

Courtesy of Mentor

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IV. Mixed Signal Analysis: Interface

Digital AnalogD/A

A/D

D/A A/D

Analog Signal 0, 1, X

Threshold Detector

Rise, Fall TimeRise, Fall Resistance

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Spice VHDL-AMS VHDL Verilog Verilog-AMS

VerilogSpice VHDLVHDL-AMS

VHDL-AMS Verilog-ASpice Spice Verilog-A

CVerilog VHDL

VHDL-AMS SpiceC Verilog-A

Mixed Signal: Mixed Languages

•Single Kernel Architecture•Single Netlist Hierarchy•Automatic D/A and A/D converter insertion

Courtesy of Mentor

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IV. Tasks

EE CSSpeed

Accuracy

LanguageRF, Analog,

Power, Noise,

Convergence Partition

Interface Compiler

Math

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IV. Research Directions

Hierarchy ManagementAnalysis + OptimizationLayout Oriented AnalysisCircuit ReductionSpice

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Physical objAlgor

Floorplan

Partition,Bus

LogicRep, buffer

PlaceWire-length,Congestion,

Block,alignment,match,size

RoutePattern,vias

AnalysisSignal integrity

Ir drop, didtmanufacturability

verification

CircuitComp,dynamic,

passPower, clockpackaging

View, hierarchy

Hierarchy Management

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Hierarchy management

logic layoutDesign process

algor

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Hierarchy Management (cont.)

•Hierarchy Tree Construction•Hierarchy Tree Transformation•Incremental Changes•Graph Process on Tree Structure

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Analysis and Optimization

i. Circuit Reductionii. Transient Analysisiii. Optimization of

• power/ground: pads, decoup caps, network

• clock networks: topology, shield, decoup caps

• Buses: shield, topology

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•Huge Circuitry•Millions of nodes

•Whole Chip Analysis•Power/Ground, Substrate, Analog

•Guaranteed Accuracy •Accuracy vs Execution Time

•Construction or Incremental Changes

Layout Oriented Analysis

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Layout Based Signal Analysis

•Generalized Y-Delta Transformation•R,C,L,Coupling, Sources

•Natural Frequency•Realizability•Hierarchical Circuit Analysis

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2112 ggy +=

1 21g

2g

1 212y

Conductance in parallel

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21

2112 gg

ggy+⋅

=

1 212y1 21g 2g

0

Conductance in series

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1

2 3

12y 13y

23y

321 ggggg

y jiij ++

⋅=

1g

2g 3g

1

2 3

0

Conductance in Y-structure

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212 11

1

clsglsg

csls

gls

gy

++=

++

⋅=

1

2 3

12y 13y

23y

e.g.

g

ls1

cs

1

2 3

0

Admittance in Y-structure

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1

2 3

12y 13y

23y

22 11

1

clsglsI

csls

g

IlsI

++=

++

⋅=is the same , and

g

ls1

cs

1

2 3

I

0

44

2I

12y

Admittance in Y-structure, with current source

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skm

1−

sk11

1

4

31

2

skm

1skm

1sk22

1

skm

1−

⎪⎩

⎪⎨⎧

=+

=+

221

11

121

11

22

11

IVV

IVV

sksk

sksk

m

m

4

31

2

sk11

1

skm

1

sk22

11V

+

2V

+

1I 2I

K-element

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Reduction example

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Waveform Estimation

Transient response evaluated using Y-∆transformation with Hurwitz polynomial approximation.

8th order stabilized Y-∆ models are used for near-end and far-end node waveform evaluation.

Only a 3rd order AWE model is obtained.

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Pole Analysis

Both AWE and Y-∆transformation have artificial positive poles;

High order AWE tends to collapse approximate poles, hiding other less dominant ones.

Y-∆ transformation with model stabilization yields no positive poles, and has broader band in pole estimation.

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V. Conclusion

Layout Oriented AnalysisUnified tools combining EE and CS with Math as foundationNew Methodologies

Larger Circuits, Shorter Product Turnaround

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References

M. Marek-Sadowska, UCSBL.T. Pileggi, CMUCK Cheng, et al, Interconnect Analysis and Synthesis, John WileyACM/IEEE Design Automation Conf.IEEE/ACM Int. Conf. On CADApache, Nassda, Mentor, Synopsys, Cadence, Celestry, IBM, and etc.