Interface Between Process EquipmentAnd Process Bus for Light WeightTesting Of Protection Functions

KHURRAM, ZEESHAN ALI

Master’s Degree ProjectStockholm, Sweden August 2012

XR-EE-ICS 2012:015

Abstract

The technological advancements in the substation automation give rise to many newchallenges for the engineers. The IEC 61850 standard defines the most advanced tech-niques towards the digital substation development. It describes the communicationmappings for the substation automation of both conventional and digital substations.The most important challenge is to replace old successful and reliable protection relayswith the newly born microprocessor based relays called intelligent electronic devices(IEDs). The IEC 61850 standard gives the novel ideas in its sub-clauses IEC 60044-8 and IEC 61850-9-2 about digital communication and sampled values transmissionover an Ethernet link called process bus. As this thesis is the Part-A and it is mainlybased on the development of the conventional instrument transformers, analog to digi-tal data converter and a multi-bus power system. The scope of this study contains thedevelopment of current and voltage transformer models in SIMULINK which gives theideal behaviour of the conventional instrument transformers for voltage and currentmeasurements.The methodology of this study is to model the Sigma-Delta analog todigital converter in the SIMULINK and then simulated results are verified accordingto the standard. The 4KHz output (Voltage/Current) signal is obtained in the digitalform with 16-bit resolution. The SNR (Signal to Noise Ratio) and ENOB (EffectiveNumber of Bits) of the data converter is verified both theoretically and practically.In the next phase the multi-bus power system is modelled in the SIMULINK usingSimPowerSystems Library to make the final tests on the developed product. Finallythe developed models of Project Part-A have been integrated with the transmissionmodel developed in the Project Part-B, collectively known as Merging Unit. Thefunctionality of this complete developed product is to get 3-phase analog signals ofcurrents and voltages from the instrument transformers, perform signal processingon these signals and then transmit them on the Ethernet port in the form of SV(Sampled Value) stream according to the IEC 61850-9-2 standard. The developedMerging Unit is then connected to the different nodes of the power system to testthe performance and reliability of the Merging Unit. The over current and differen-tial protection functions are tested on the ABB’s RET 670 IED (Protection Relayfor Transformer). In both test cases three phase short circuit fault is applied to thepower system to check the behaviour of the Merging Unit during normal and abnor-mal conditions. It detects all the values correctly during pre-fault condition, faultcondition and post-fault condition.

I want to dedicate this degree project to my teachers,family and friends.

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Acknowledgments

First of all I would like to thank Allah Almighty for the completion of my thesis.

It is pleasure to thank the many people who made this thesis possible.

I would like to express my deep and sincere gratitude to my Supervisor, Mr.NicholasHoneth, Ph.D student at the Department of Industrial Information and Communica-tion Systems, The Royal Institute of Technology (KTH). His wide knowledge and hislogical way of thinking have been of great value for me. His encouragement, inspi-ration and personal advice ensure the progress and quality of this research work. Iwould also like to pay my regards to Professor Lars Nordstrom for his kind behaviourand positive feedback during the substation automation courses and this thesis work.Ican not help mentioning Mr.Mustafa Chenine Ph.D student at Industrial Informationand Control Systems for his fruitful advices during my stay at ICS. I would also liketo mention Dr.Arshad Saleem for his help during the thesis.

At ABB, I would like to express my gratitude to my supervisors Mr.Johan Salj andMr.Klas Koppari for their encouragement, guidance and patience towards me duringthe whole master thesis. I would also like to thank Dr.Murari Saha for his adminis-trative assistance throughout this project.

I want to thank my seniors and friends in KTH ; Zeeshan Ahmed,Umer Zeeshan,Shoaib Almas, Zeeshan Talib, Amir Sultan, Naveed Khan,Muhammad Salman, fortheir support, kindness and useful advices all the time.

I would like to mention my class fellows; Farhan, Malik Usman, Usman Shaukat, AmitKumar, Siaful with whom I spent a wonderful time during entire Master Degree inElectrical Engineering. I will always miss the movements spent with Farhan whilegoing back to home after university. I would like to thank Amit Kumar Jha for hissupport during entire Master Degree.

Last but not the least,I would like to thank Pencheng Zhao, my fellow thesis workerand close friend. Without his co-operation, company and invaluable assistance thework would not have been as enjoyable and successful.

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I wish to thank my Peer-o-Murshad Baba Majeed (Babajee) and my best friendsRana Matloob, Aurangzeb Poomi, Rana Poond, Asad Malhi and Faisal Dev for help-ing me get through the difficult times, and for all the emotional support, comraderie,entertainment, and caring they provided.

Furthermore I am thankful to everyone that has participated in any way in my thesisproject.

”Believers pray to God for the protection of faith, But few pray for the gift of hislove. I am ashamed at what they ask for, Even more at what they are willing to yield.Religion is quite unaware of the spiritual plane, To which love can raise us. O Lord,

keep my love for you ever fresh, Says Bahu: I shall mortgage my religion for it”.

Zeeshan Ali KhurramStockholm, 2012

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Table of Contents

Abstract i

Dedication ii

Acknowledgements iii

List of Acronyms ix

List of Tables xi

List of Figures xii

1 Introduction 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Project Goals and Objectives . . . . . . . . . . . . . . . . . . . . . . 21.3 Scope of the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5 General Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6 Outline of Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Methodology 52.1 Research Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 IEC 61850 Standard for Substation Protection and Automation . . . 62.3 Conventional Substation Architecture . . . . . . . . . . . . . . . . . . 62.4 Digital Substation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.5 Merging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.6 Merging Unit Related Work . . . . . . . . . . . . . . . . . . . . . . . 92.7 Design of Merging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7.1 Data Acquisition and Processing Function . . . . . . . . . . . 102.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Models of CT/PT 123.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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3.2 Instrument Transformers . . . . . . . . . . . . . . . . . . . . . . . . 123.3 Conventional Instrument Transformers VS NCIT . . . . . . . . . . . 123.4 Conventional Instrument Transformers . . . . . . . . . . . . . . . . . 133.5 Non-Conventional Instrument Transformers . . . . . . . . . . . . . . 14

3.5.1 General Configuration of ECTs and EVTs . . . . . . . . . . . 143.6 Simulink Model of CT/VT . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Modelling Of Analog To Digital Converter In SIMULINK 174.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.1 Analog To Digital Conversion . . . . . . . . . . . . . . . . . . 174.1.2 Steps From Analog To Digital Conversion . . . . . . . . . . . 184.1.3 Analog Input Signals . . . . . . . . . . . . . . . . . . . . . . . 184.1.4 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1.5 Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Types Of Analog to Digital Conversions . . . . . . . . . . . . . . . . 204.2.1 Selection Of ADC Type . . . . . . . . . . . . . . . . . . . . . 20

4.3 Principle Of Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . 214.3.1 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . 214.3.2 Flash ADC Modelling . . . . . . . . . . . . . . . . . . . . . . 214.3.3 Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Sigma-Delta Analog To Digital Converter . . . . . . . . . . . . . . . . 254.4.1 Why Sigma-Delta ADC? . . . . . . . . . . . . . . . . . . . . . 254.4.2 Sigma-Delta Modulator Working . . . . . . . . . . . . . . . . 254.4.3 Signal Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . 264.4.4 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . 274.4.5 Sigma-Delta Modulator Quantization Noise . . . . . . . . . . 284.4.6 Order Of Modulator And Quantization Noise . . . . . . . . . 294.4.7 SNR Of Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . 30

4.5 Complete SIMULINK Model Of Sigma-Delta ADC . . . . . . . . . . 314.5.1 Analog Filter Design Block . . . . . . . . . . . . . . . . . . . . 324.5.2 Integrator Block . . . . . . . . . . . . . . . . . . . . . . . . . . 334.5.3 Signum Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.5.4 Zero Order Hold Block . . . . . . . . . . . . . . . . . . . . . . 344.5.5 FIR Decimation Block . . . . . . . . . . . . . . . . . . . . . . 354.5.6 Transport Delay Block . . . . . . . . . . . . . . . . . . . . . . 36

4.6 Comprehensive Sigma-Delta Design Explanation . . . . . . . . . . . . 374.7 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5 Modelling Of Power System In SIMULINK 405.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1.1 Power System Modelling . . . . . . . . . . . . . . . . . . . . . 405.1.2 Power System Modelling In SimPowerSystems . . . . . . . . . 41

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5.2 List Of SimPowerSystems Blocks Used . . . . . . . . . . . . . . . . . 415.2.1 Three phase Programmable Voltage Source . . . . . . . . . . . 415.2.2 Three Phase Transformer . . . . . . . . . . . . . . . . . . . . 435.2.3 Three Phase PI Section Line . . . . . . . . . . . . . . . . . . . 465.2.4 Three Phase OLTC . . . . . . . . . . . . . . . . . . . . . . . . 475.2.5 Three Phase Series RLC Load . . . . . . . . . . . . . . . . . . 495.2.6 Three Phase Fault . . . . . . . . . . . . . . . . . . . . . . . . 505.2.7 Metering Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 515.2.8 Discrete Three Phase Sequence Analyser . . . . . . . . . . . . 535.2.9 Power GUI Block . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3 Full Modelled Power System . . . . . . . . . . . . . . . . . . . . . . . 575.3.1 Purpose of Power System . . . . . . . . . . . . . . . . . . . . 58

6 Complete Test Platform 596.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.2 Physical Test Platform . . . . . . . . . . . . . . . . . . . . . . . . . . 596.3 Protection Function Testing Tools . . . . . . . . . . . . . . . . . . . . 60

6.3.1 Hardware Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 606.3.2 Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.4 Lab Setup for the Soft Merging Unit Testing . . . . . . . . . . . . . . 616.5 Complete System Integration . . . . . . . . . . . . . . . . . . . . . . 62

6.5.1 Protection Function Testing Scheme . . . . . . . . . . . . . . 636.5.2 Description of Hardware and Software . . . . . . . . . . . . . 64

6.6 Over-current Protection Scenario . . . . . . . . . . . . . . . . . . . . 646.6.1 Configuring IED RET 670 . . . . . . . . . . . . . . . . . . . . 646.6.2 Power System for Steady State Measurements . . . . . . . . . 656.6.3 Application Configuration in PCM 600 . . . . . . . . . . . . . 666.6.4 Simulation Values at Node 2 . . . . . . . . . . . . . . . . . . . 666.6.5 Screenshot of IED RET 670 HMI . . . . . . . . . . . . . . . . 676.6.6 Transient State Test and Over-Current Protection . . . . . . . 686.6.7 Configuration of Over-Current Protection in PCM 600 . . . . 696.6.8 Parameter Settings for Over current Protection . . . . . . . . 706.6.9 Simulation Values at Node 2 During Fault . . . . . . . . . . . 716.6.10 Screenshot of Local HMI of IED RET670 . . . . . . . . . . . 72

6.7 Additional Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736.7.1 Response of MU Under Unsymmetrical Fault . . . . . . . . . . 736.7.2 Response of MU Under Harmonic Injection by Source . . . . . 736.7.3 Response of MU Under OLTC Operation . . . . . . . . . . . . 756.7.4 Simulation Results on Bus 3 and 4 . . . . . . . . . . . . . . . 76

6.8 Transformer Differential Protection Test . . . . . . . . . . . . . . . . 77

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7 Results 787.1 ADC output for Over current Protection . . . . . . . . . . . . . . . . 787.2 ADC Output During Harmonic Injection . . . . . . . . . . . . . . . . 80

8 Discussion 82

9 Future Recommendations 849.1 Future work for this thesis . . . . . . . . . . . . . . . . . . . . . . . . 849.2 Future work for the whole project . . . . . . . . . . . . . . . . . . . . 85

Bibliography 86

A Evaluation Report 1A.1 Four Steps Phase Overcurrent Protection OC4PTOC with 2nd Harmonics 1A.2 Two Windings Transformer Differential Protection (T2WPDIF) . . . 7

ix

List of Acronyms

IEC International Electrotechnical Commission

IEEE Institute of Electrical and Electronics Engineers

ABB Asea Brown Boveri

CT Current Transformer

PT Potential Transformer

VT Voltage Transformer

ECT Electronic Current Transformer

EVT Electronic Voltage Transformer

NCIT Non Conventional Instrument Transformer

MU Merging Unit

ADC Analog to Digital Conversion

SAS Substation Automation Systems

HMI Human Machine Interface

IED Intelligent Electronic Device

SNR Signal to Noise Ratio

ENOB Effective Number of Bits

FIR Finite Impulse Response

OSR Oversampling Ratio

SV Sampled Value

GOOSE General Object Oriented Substation Event

OLTC On Load Tap Changer

RAM Random Access Memory

RMS Root Mean Square

BI Binary Input

x

BO Binary Output

BER Bit Error Rate

UDP User Datagram Protocol

FPGA Field Programmable Gate Array

PPS Pulse Per Second

LED Light Emitting Diode

MMS Manufacturing Message Specification

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List of Tables

6.1 OC4PTOC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 71

A.1 The map of LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A.2 OC4PTOC settings for 2nd harmonic restrain . . . . . . . . . . . . . 5A.3 Parameter setting for MU . . . . . . . . . . . . . . . . . . . . . . . . 12A.4 The LED map for T2WPDIF . . . . . . . . . . . . . . . . . . . . . . 13A.5 T2WPDIF settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13A.6 The changed parameters for T2WPDIF . . . . . . . . . . . . . . . . . 16

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List of Figures

1.1 Substation Automation With Station and Process Bus . . . . . . . . 3

2.1 Method Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Station Bus and Conventional Wiring to the Process . . . . . . . . . 62.3 Station Bus with Ethernet connection to the Process level . . . . . . 72.4 Hierarchical Communication Network with Station and Process Bus[1] 82.5 Merging Unit defined in IEC 60044-8 . . . . . . . . . . . . . . . . . . 82.6 Merging Unit Architecture . . . . . . . . . . . . . . . . . . . . . . . . 92.7 Phase Delay in the Signal[2] . . . . . . . . . . . . . . . . . . . . . . . 92.8 Design of Merging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Equivalent Circuit for CT . . . . . . . . . . . . . . . . . . . . . . . . 133.2 Equivalent Circuit for VT . . . . . . . . . . . . . . . . . . . . . . . . 143.3 Digital Substation Configuration of a Bay . . . . . . . . . . . . . . . 153.4 CT/PT Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 ADC flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2 Sampling an analog signal . . . . . . . . . . . . . . . . . . . . . . . . 194.3 (a)Spectrum of unsampled waveform (b)Spectrum of sampling function

(c)Spectrum of sampled waveform . . . . . . . . . . . . . . . . . . . . 194.4 Aliasing phenomena . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.5 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.6 Flash ADC schematic [3] . . . . . . . . . . . . . . . . . . . . . . . . 224.7 Priority Encoder SIMULINK model 8-3 bit . . . . . . . . . . . . . . . 234.8 Detailed Flash ADC model in SIMULINK . . . . . . . . . . . . . . . 234.9 MATLAB/SIMULINK Simscape Toolbox . . . . . . . . . . . . . . . 244.10 First order sigma-delta ADC block diagram . . . . . . . . . . . . . . 264.11 Under-sampled signal spectrum . . . . . . . . . . . . . . . . . . . . . 264.12 Over-sampled signal spectrum . . . . . . . . . . . . . . . . . . . . . . 274.13 Code example of a 2-bit A/D converter . . . . . . . . . . . . . . . . . 274.14 First order sigma-delta modulator sampled data equivalent block diagram 284.15 SNR VS Oversampling ratio for sigma-delta modulators[4] . . . . . . 294.16 Frequency Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

xiii

4.17 Sigma-Delta ADC model in SIMULINK . . . . . . . . . . . . . . . . 314.18 MATLAB/SIMULINK DSP Toolbox . . . . . . . . . . . . . . . . . . 324.19 Analog Filter Block Parameter Details . . . . . . . . . . . . . . . . . 334.20 Integrator Block Parameter Details . . . . . . . . . . . . . . . . . . . 334.21 Signum Block Parameter Details . . . . . . . . . . . . . . . . . . . . 344.22 Zero order hold Block Parameter Details . . . . . . . . . . . . . . . . 354.23 FIR Decimation Block Parameter Details . . . . . . . . . . . . . . . 354.24 FIR Decimation Block Parameter Details . . . . . . . . . . . . . . . 364.25 Transport Delay Block Parameter Details . . . . . . . . . . . . . . . 364.26 Detailed model with explanation . . . . . . . . . . . . . . . . . . . . 374.27 Simulated Sampled Signal Output . . . . . . . . . . . . . . . . . . . 384.28 Analog Signal and Simulated Quantized Signal with error . . . . . . . 384.29 Final Digital Signal Output . . . . . . . . . . . . . . . . . . . . . . . 39

5.1 Single line diagram of Test System . . . . . . . . . . . . . . . . . . . 415.2 Three phase Programmable Voltage Source Block . . . . . . . . . . . 425.3 Three phase Programmable Voltage Source Block Parameter Details . 435.4 Three phase Two Winding Transformer Block . . . . . . . . . . . . . 445.5 Three phase Two Winding Advance Parameter Details . . . . . . . . 445.6 Three phase Two Winding Transformer Parameter Details . . . . . . 455.7 Three phase Two Winding Transformer Parameter Details . . . . . . 455.8 Three Phase PI Section Line Block . . . . . . . . . . . . . . . . . . . 465.9 Three Phase PI Section Line parameter details . . . . . . . . . . . . . 465.10 Three Phase OLTC Block . . . . . . . . . . . . . . . . . . . . . . . . 475.11 Three Phase OLTC transformer parameter details . . . . . . . . . . . 485.12 Three Phase OLTC voltage regulator parameter details . . . . . . . . 495.13 Three Phase Series RLC Load Block . . . . . . . . . . . . . . . . . . 495.14 Three Phase Series RLC Load Parameter details . . . . . . . . . . . . 505.15 Three Phase Fault Block . . . . . . . . . . . . . . . . . . . . . . . . . 505.16 Three Phase Fault Parameter Details . . . . . . . . . . . . . . . . . . 515.17 Three Phase VI Measurement Block . . . . . . . . . . . . . . . . . . . 525.18 Three Phase VI Measurement Parameter Details . . . . . . . . . . . . 535.19 Discrete Three Phase Sequence Analyser Block . . . . . . . . . . . . . 545.20 Discrete Three Phase Sequence Analyser Parameter Details . . . . . . 545.21 Power GUI Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.22 Power GUI Configuration Settings . . . . . . . . . . . . . . . . . . . . 555.23 Power GUI Configuration Settings . . . . . . . . . . . . . . . . . . . . 565.24 Power GUI Analysis Tools . . . . . . . . . . . . . . . . . . . . . . . . 575.25 Three Phase Power System Modelled in Simulink . . . . . . . . . . . 57

6.1 Picture of the test setup for the all-digital over-current protection[5] . 606.2 Lab Setup for Soft Merging Unit for Protection Function Testing . . 616.3 Lab Setup for Soft Merging Unit for Protection Function Testing . . . 62

xiv

6.4 Protection Function Testing Scheme . . . . . . . . . . . . . . . . . . . 636.5 Protection Function Testing Scheme . . . . . . . . . . . . . . . . . . . 636.6 Power System with MUs attached to the Nodes . . . . . . . . . . . . 656.7 Application Configuration for Monitoring Function In PCM600 . . . . 666.8 Three phase Voltages and Currents at BUS 2 . . . . . . . . . . . . . 676.9 Steady State Values . . . . . . . . . . . . . . . . . . . . . . . . . . . 686.10 Power System with Three Phase Short Circuit Fault . . . . . . . . . 696.11 Four Step Over-current Protection Block OC4PTOC . . . . . . . . . 706.12 Three Phase Voltages and Currents at BUS 2 . . . . . . . . . . . . . 726.13 Transient State During Three Phase Short Circuit . . . . . . . . . . . 726.14 Three Phase Voltages and Currents at BUS 2 During Unsymmetrical

Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736.15 Test System for Harmonic Injection . . . . . . . . . . . . . . . . . . . 746.16 Three Phase Voltages and Currents at BUS 2 With Harmonic Injection 756.17 Voltage Regulation Monitoring Test System . . . . . . . . . . . . . . 766.18 Voltage Regulation on Bus 3 and 4 . . . . . . . . . . . . . . . . . . . 776.19 Tap Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.1 ADC Output of Voltage During Steady State . . . . . . . . . . . . . . 787.2 ADC Output of Current During Steady State . . . . . . . . . . . . . 797.3 ADC Output of Voltage During Transient State . . . . . . . . . . . . 797.4 ADC Output of Current During Transient State . . . . . . . . . . . . 807.5 ADC Output of Voltage During Harmonic Injection . . . . . . . . . . 817.6 ADC Output of Current During Harmonic Injection . . . . . . . . . . 81

9.1 Interoperability Representation at Process Level . . . . . . . . . . . . 85

A.1 The Simulink model of the testing . . . . . . . . . . . . . . . . . . . . 2A.2 The scheme of the testing . . . . . . . . . . . . . . . . . . . . . . . . 3A.3 The application configuration in PCM 600 . . . . . . . . . . . . . . . 4A.4 The results of OC4PTOC with 2nd harmonic . . . . . . . . . . . . . . 6A.5 Schematic of two windings transformer differential protection . . . . . 7A.6 The transformer differential protection provided in RET 670 . . . . . 8A.7 The Simulink model for differential protection . . . . . . . . . . . . . 9A.8 The waveforms of primary and secondary sides . . . . . . . . . . . . . 10A.9 The Wireshark capture of sending SVs for two MUs . . . . . . . . . . 11A.10 Application configuration for T2WPDIF . . . . . . . . . . . . . . . . 12A.11 The trips of T2WPDIF . . . . . . . . . . . . . . . . . . . . . . . . . . 15A.12 The trips of T2WPDIF . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1

Chapter 1

Introduction

1.1 Introduction

Generation, transmission, distribution are the main parts of a power system. Thesafe operation of power system is vital for the clients satisfaction. For this satisfac-tion power system protection is an indispensable event for the safety. In the historydifferent eras have different kind of protection equipment deployed for the protection.If we talk about the substation automation electromechanical relays were the first tostart with in protection field. As time goes on development had been made towardsthe more reliable protection devices. Then the solid state relays came into the appli-cation of protection and they were much better than the electromechanical relays inthe sense of their operation functionalities. Furthermore, there came a revolution inthe field of electronics and microprocessor based relays came into being as the stateof art. These microprocessor based relays have lots of advance operating principlesby use of which the highest level of substation automation can be achieved for themore reliable energy transfer to the customers. The continuous advancements andreduced costs have made the microprocessor relays the solution of choice. Since theinformation processed digitally, a large number of protection functions can be builton one device [6]. International Electrotechnical Commission (IEC) standard 61850suggests the Ethernet based communication in the substation automation field. Thesuccessful deployment of this standard in the substation automation will provide bothreliability and efficient cost reduction. In order to the successful deployment of theprocess bus and IEC 61850-9-2 sampled measured values lots of time critical testshave to be made. This report addresses different aspects of the Merging Unit andthe standard IEC 61850-9-2 [7]. As the IEC 61850 communication standard has beenwidely accepted and applied in the substation automation it is important that thetesting tools keep up with these developments [8]. Besides all these the Merging Unitwill also be discussed in detail in the report as it is the important part of interfacingbetween the high voltages of transmission and the secondary protective devices.

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1.2 Project Goals and Objectives

The main goal is to develop a light weight Merging Unit in MATLAB/SIMULINKenvironment. The objective is to have a soft MU which gives us the opportunityto make test and run simulations on an ordinary lab computer as compared to anyvendor product which demands a lot of security parameters and license agreementswith a high cost.The final goal of this project is the product development of MUaccording to the IEC 61850 standard. Another objective of this project is to developa test bed for the testing of different protection functions under different constraints.

1.3 Scope of the Project

The scope of the this Part-A of the project is to parametrize the current and voltagetransformer models developed in the Simulink. The scope also covers the modellingof ADC’s and multi-bus power system in Simulink. Therefore the Part-A and Part-B[9]are integrated and the final developed product is achieved. The scope of thisproject is also to provide a test bed for the testing of different protection functionslike over current and differential protections.

1.4 Motivation

• Light Weight 9-2 testing environment

• Quick Configuration

• Demonstration for customers

• Testing of different types of protection Functions

• Interoperability tests for MU and IEDs

The figure 1.1 is the illustration of the whole Project. The red encircled portion ofthe figure 1.1 is the main task of research work where MU is an interface betweenInstrument transformers and the process bus, and process bus is the interface betweenMU and IED.

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Figure 1.1: Substation Automation With Station and Process Bus

1.5 General Limitations

As a general rule,the time factor, cost, availability of technical apparatus bring con-straints to each project which somehow affects the quality of research work. Thereforethe constraints make the expectations of the work more reasonable and close to finalresults and findings.

Technical Limitations

This constraint includes the unavailability of real time simulator which restrict thiswork to off-line simulations. The unavailability of IEC 61850-9-2 process bus on theAREVA and SIEMENS could not allow us to perform interoperability tests.

Time Constraint

The time factor plays an important role in any project. Due to this constraint wecould not able to develop the synchronization function. Even though it was not inthe tasks to compete in priority list but it could be the interesting work to add up tothe research work.

1.6 Outline of Report

Chapter 1 summarizes with the introduction and motivation behind this study work.Chapter 2 provides the purpose of research, literature review and the selected research

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methodology. Chapter 3 covers the basic theory and modelling of the CT/PT. Chap-ter 4 covers the theoretical background of signal processing and explains the selectionand modelling of the analog to digital conversion. Chapter 5 presents the modellingof a power system required for the analysis. Chapter 6 gives the complete test systemevaluation based on different protection functions. Chapter 7 presents the results ofthe designed ADC.Chapter 8 is included to present discussion about whole projectand chapter 9 gives future recommendations about this thesis work.

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Chapter 2

Methodology

This chapter comprises the research methodology for this thesis work. Firstly, anunderstanding of the substation automation according to the IEC 61850 is done.Then the understanding of the latest research going on is also needs to be taken intoaccount. This was done by reading related literature, reports and previous work.When a certain level of understanding and knowledge had been achieved then itstime to start working on this research problem.

2.1 Research Method

The following figure 2.1 explains the method used for the research in this study work.

Figure 2.1: Method Steps

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2.2 IEC 61850 Standard for Substation Protection and Au-tomation

The success of a substation protection and automation system depends on the effec-tiveness of the communication link to the different devices within an electric powersubstation. The important challenge for the substation automation design engineersis to provide interoperability among devices from different vendors. A large amountof investment is required to develop costly and complicated protocols and interfacesfor the communication among all the devices in the substation. In order to addressthis matter the International Electro technical Commission (IEC) Technical Com-mittee (TC-57) has published IEC 61850 standard titled ”Communication Networksand Systems in Substation” in 2003[10]. IEC 61850 is the new standard for commu-nication networks and systems in the substations.The transmission and distributionsubstation of the future is currently influenced by the future standard IEC 61850.The standard gives the communication mappings for all the primary and secondaryequipment in the substation automation. This standard will help in eliminating themost of copper wiring in the substation. These copper wires are used to connect theprocess equipment to the bay level. These wires contain analog signals from switch-yard, binary status and command signals. This will be the basis for new applicationssupporting not only the operation but also the maintenance of the substation [11].

2.3 Conventional Substation Architecture

The conventional substation architecture is shown in the figure below[11].

Figure 2.2: Station Bus and Conventional Wiring to the Process

Figure 2.2 is self explanatory about the architecture of a conventional substa-tion. The conventional transformers are connected through a lot of copper wires tomake connections to the protection system. This is just for the case of one bay. One

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can imagine easily the complexity level of connections when there are hundreds ofbays to protect. The same architecture is good enough for the IEC 61850 to imple-ment its standards. The first step is to remove the conventional transformers and usenon-conventional transformers and conventional switchgear which will be connectedthrough serial point-to-point connections according to the standard. In this thesisthe non-conventional transformers are modelled and then IEC 61850-9-2 interface isimplemented. The architecture for IEC 61850 is also given in the figure 2.3 below.

Figure 2.3: Station Bus with Ethernet connection to the Process level

2.4 Digital Substation

The future substations are the digital substations with IEC 61850 implementation.Digital substations comprise of intelligent primary devices and networking IEDs toachieve information sharing and inter-operability between different vendor productsbased on IEC 61850 protocols e.g MMS, GOOSE and SV. As compared with theconventional substations, communication interfaces and protocols are different at thebay level and the station level. However the major difference between the two is theprocess bus implemented in the digital substation. The digital substation includesintelligent primary devices,merging units and optic fiber connections. The fiber con-nections replace conventional CT/VT, primary devices and conventional cable wiring.Digital substations has introduced GOOSE scheme which is the replacement of tradi-tional binary inputs and binary outputs. The digital BI and BO are configurable andcan be delivered to Ethernet switch. This helps in reducing the wiring in the substa-tion. The use of the sampled value makes the current/voltage sampling at primaryside easier and more reliable. The voltage and current signals are captured at theprimary side, converted to the optic signals and then transferred to the protection andcontrol devices via optical fiber [1]. The pictorial comparison between conventionaland digital substation is given in the figure 2.4.

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Figure 2.4: Hierarchical Communication Network with Station and Process Bus[1]

2.5 Merging Unit

It is an important intelligent electronic device in digital substation. It is the importantpart to exchange the messages between ECT/EVT (electronic current and electronicvoltage transformers) process level and the secondary equipment (bay level) of thesubstation automation. The function of merging unit is to collect multichannel digitalsignals output by electronic current and electronic voltage transformers synchronouslyand transmit these signals with the protocol of IEC 61850 to protective devices andmeasure control devices [12].

A lot of research is going on by different vendors and researchers on this in-telligent device which is the interface between the conventional and non conventionalvoltage and current transformers and the process bus. The overall interface is repre-sented in the figure 2.5 which is defined in the IEC 60044-8.

Figure 2.5: Merging Unit defined in IEC 60044-8

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2.6 Merging Unit Related Work

The suggested design of the Merging Unit is described to have an insight of thecomponents needed to design a merging unit. The incoming signals are from theinstrument transformers which are fed into the MU. The MU architecture containsfirst block with the analog filtering circuits first to process on analog signals to decidethe cut off frequencies for the incoming signals. The second block contains the ADCto convert analog to digital converter for analog signals conversion to digital form.The third block contains the digital signal processing block which is used to removethe noise and to perform digital filtering on the signals. The signal after passingthrough all these processing blocks experienced a delay in its phase. This delay canbe compensated by using the synchronization pulse. If the synchronization pulse isnot used then there will always be a delay in the phase of the incoming signal. Thisis the one of the related work which gives much clearer insight into the design of themerging unit. This idea will also be utilized in the design of soft merging unit at ICS[13] [2]. The figure2.6 explains the idea of merging unit internal components.

Figure 2.6: Merging Unit Architecture

The delay in the phase can be realized in the figure2.7.

Figure 2.7: Phase Delay in the Signal[2]

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2.7 Design of Merging Unit

According to the recent research works different researchers suggest different designsfor the Merging Unit. The research work in [12] is taken as reference for this thesiswork. The design of MU is comprises of three major parts.

1. Data Acquisition and Processing

2. Packet Transmission

3. Synchronizing Function

The part of Data Acquisition and Processing is done in this Part-A of the Project.The Part-B [9] of the Project is responsible for the Packet Transmission part. Thethird part is Synchronization function and it is not completed for now due to timeconstraint.

Figure 2.8: Design of Merging Unit

2.7.1 Data Acquisition and Processing Function

The function of this module is to connect the CT/VT to the secondary equipment.The merging unit must have the ability to acquire and merge the sampled valuesfrom multichannel electronic transducers and the analog values from the conventionalinstrument transformers synchronously . Then the ADC’s convert the incoming 4Vand 4I into the digitized form with a output rate of 4 KHz according to the standardIEC 61850. Afterwards the packet transmission part does the rest and put this datato the Ethernet port by making the packets of the digitized data according to theIEC 61850-9-2 standard.

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2.8 Summary

These above reference points which are explained thoroughly would be the basic build-ing blocks for the development of merging unit. The merging unit which is developedin the reference [12] provided above is in the FPGA but the merging unit for thisresearch work would be developed in the MATLAB/SIMULINK.The models of merg-ing unit and the process bus development will be connected as an interface betweenthe instrument transformers and the intelligent electronic devices and different kindsof tests like accuracy of merging unit, correctness, speed and the limitations will bediscussed and a useful finding out of this project will be presented.

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Chapter 3

Models of CT/PT

3.1 Introduction

This chapter starts with theoretical background about conventional instrument trans-formers and non-conventional instrument transformers. After the theoretical back-ground the developed models are presented which are continuously providing thescaled down measured value for currents and voltages. These models are not the realmodels for CT/PT but give the ideal realization of CT/PT.

3.2 Instrument Transformers

In order to develop an interface between secondary equipment and process bus an-other interface between high tension side and merging unit is required. This interfacewill transform high voltages and currents to low value voltages and currents. Instru-ment transformers consists of current transformers and voltage transformers. Thepurpose of instrument transformers is to convert the high voltages and currents tothe low values of currents and voltages in a power system. The rapid and reliableoperation of the power system protection and control is dependent on reasonably ac-curate measurements of electrical signals associated with controlled elements of thepower system. The values of currents and voltages from instrument transformersduring large and small disturbances in the power system are of great importancewith respect to their accuracy of measurement [14]. The protection systems are to-tally dependent on the measurements from the instrument transformers, so accuratemodelling of CT/PT is of great importance.

3.3 Conventional Instrument Transformers VS NCIT

The current transformers are the key components as they produce the access to thehigh currents in a power system through reduced replica on the secondary side. Itenables the protection function to detect the faults within time limits and isolate

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them. Therefore the protection devices are totally dependent on the measurementvalues coming from the instrument transformers. Unfortunately there is a problem ofsaturation in the CT core. The CT cores have the problem of non linear excitationwhen exposed to high fault currents. Therefore the non linear excitation forces the nonlinear saturation in the core material of the current transformer. When the non linearsaturation phenomena occurs the measured value of current on the secondary side isno more according to the turns ratio which leads to the triggering of wrong event [15].On the other hand the new replacements for the conventional instrument transformersis the non conventional instrument transformers also known as electronic current andvoltage transformers.The ECT plays an important part in the smart substation,it usesthe electronic technology to measure the voltage and current of power system andsupplies these data to relay protection and control system. Compared with traditionalelectromagnetic current transformer, the ECT has many advantages, such as simpleinsulation structure, immunity to electromagnetic interference, no saturation effect,no flammable materials such as oil [16].

3.4 Conventional Instrument Transformers

Conventional instrument transformers are also known as the electromagnetic trans-formers. The main purpose of the instrument current transformer is to produce a pro-portional secondary current from the incoming primary current.Current transformersare commonly used in metering and protective relaying in the electrical power indus-try. They facilitate the safe measurement of large current from high tension lines.Theprimary winding is connected in series with the source current to be measured. Thesecondary winding is normally connected to a meter, relay, or a burden resistor todevelop a low level voltage that is amplified for control purpose. The basic theoryof a current transformer is the same as for any other iron-core type. The primaryis normally a single turn while the secondary has a large number of turns, normallya turn ratio of 100 or more is common. A high turns ratio generally causes a highleakage inductances. This causes the secondary output to be less than the predictedfrom the primary voltage times the turns ratio. Due to these leakages phenomena thedesign of CT is need to be considered very carefully [17]. The circuit diagram of CTis shown in the figure3.1.

Figure 3.1: Equivalent Circuit for CT

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The inductive voltage transformers are the dominant sources of the voltageoutput signals for measurement and protective devices and relays in medium and highvoltage networks due to their simple construction and low costs.The main purposeof the instrument voltage transformer is to produce a proportional secondary voltagefrom the incoming primary voltage. The secondary winding consists from one to threewindings that are used for measuring, protection purposes or earth fault indication.Primary winding consists of copper wire usually the conductor of high voltage comingfrom transmission line [18]. The equivalent circuit for the voltage transformer is shownin the figure 3.2.

Figure 3.2: Equivalent Circuit for VT

3.5 Non-Conventional Instrument Transformers

Nowadays NCIT have achieved high performance regarding substation automation.Due to latest developments in the field of electronics and information technologysubstations are becoming more and more compact. The data transmission is becom-ing digital upto process level. NCIT with compact dimensions and digital outputshave found a suitable place in the modern digital substation. The performance ofNCIT satisfies the protection and metering requirements under most worst condi-tions of temperature, mechanical vibrations and electromagnetic compatibility [19].Non-conventional instrument transformers are also known as electronic current andvoltage transformers. The ECTs and EVTs play a sensing and digitizing role forcurrent and voltage information with the processing capabilities of digital electronics.The designs of ECTs and EVTs are based on IEC 60044-8 and IEC 60044-7 respec-tively. The digital output interface of NCIT is based on IEC 61850-9. The sensedcurrent and voltage measurements are transmitted to them as optical digital signals.Therefore the primary equipment and substation system wiring can be simplified dueto extensive use of optical fiber for communication of current and voltage informationand operating commands[20].

3.5.1 General Configuration of ECTs and EVTs

The ECT is based on the principle of a Rogowski coil by taking into account ofsaturation free characteristics and economical efficiency. As for the voltage detection

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sensor of EVT, a capacitive voltage divider of high reliability and simple insulatedconstruction was applied. The sensing units are arranged near the rogowski coiland the capacitive voltage divider to each bay and one MU is provided to get thesecondary information. The interface between sensing unit and MU is provided bythe optical fiber connection. The MU is also connected to the process bus via opticalfiber. Redundancy is provided for the sake of reliability of the system. The figure 3.3gives the clearer idea about it [20].

Figure 3.3: Digital Substation Configuration of a Bay

3.6 Simulink Model of CT/VT

The voltages and currents on the transmission level are very high. These voltages arestepped down by the instrument transformers for monitoring and protection purposes.The current and voltage transformers usually transform the high tension side to (0-1A)or(0-5 A) and (0-110 V) depending on the measuring systems configuration. Inthis study work the voltages and currents are stepped down to (0-110 V) and (0-1 A).After stepping down the voltages and currents the measurements are further scaleddown for the ADC’s to work properly on these measurements. The Simulink modelused for both CT/PT are given in the figure 3.4.

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Figure 3.4: CT/PT Model

In the figure3.4 there are two gain blocks with one saturation block.

The first gain block is to provide step down ratio to the incoming voltages andcurrents from the main transmission line. After the step down block the saturationblock is connected to provide an upper and lower limit to the measured values. Thepurpose of putting saturation limits is to block the extra high voltages and currentsduring any abnormal or fault condition. At the end the second gain block is connectedwhich is mainly used for the further scaling down of the input voltages and currentsif required. The model is flexible for any value of the input measurements and canbe parametrize according to the given or required conditions. This final scaled downoutput is ready for the ADC as an AC input signal to convert it to digital signal.

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Chapter 4

Modelling Of Analog To DigitalConverter In SIMULINK

4.1 Background

The modeling of MU (merging unit) requires an important component to model is theanalog to digital converter. The functionality of this converter is to take in the analogvalues from the conventional instrument transformers CT/PT and convert them tothe high resolution digital values. According to the IEC 61850 standard the mergingunit will take three phases and neutral current and three phases and neutral voltagefrom the conventional instrument transformers. These current and voltage signalsare converted to digital form and after some signal processing are then transferredto the Ethernet port to the process bus. The two kinds of output resolutions arerequired at the process bus for the IEDs. The 16-bit resolution digital signals arerequired for the protection functions to work properly and 14-bit resolution signalsare required for the monitoring purposes. The achievements of these two kinds ofsignals are explained in the following section.

4.1.1 Analog To Digital Conversion

Analog-to-digital and digital-to-analog converters provide the interface between theanalog signal domain and the binary digital computational domain. The analog sig-nals which are converted to the digital can originate from many types of transducersthat convert physical phenomenon, temperature, pressure, position, motion, sound,images to electrical signals. The electrical signals from an energized transducer areeither an analog current or voltage whose value is proportional to the physical phe-nomena being measured [21].In the development of our application the three phase currents and three phase volt-ages are taken as the inputs for the analog to digital conversions from the instrumenttransformers.

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4.1.2 Steps From Analog To Digital Conversion

Achieving digital signals from analog signals include the following main steps as shownin the figure 4.1.

1. Input signal conditioning

2. Sampling

3. Quantization

4. Decimation

Figure 4.1: ADC flow diagram

4.1.3 Analog Input Signals

Analog refers to the physical quantities that vary continuously instead of discretely.Physical phenomena usually involve analog signals e.g. temperature, pressure, speed,position, altitude, voltage, current, etc. Microprocessors work with digital quantities.Therefore for a digital system to interact with an analog system, conversion betweenanalog and digital values is desired [22].The signals used for the application will be the current and voltage signals of (0-1Amp) and (0-110Volts) from the instrument transformers with 50Hz frequency.

4.1.4 Sampling

This is the important step in ADC in order to digitize the signal to be able to convertit into digital form. The signals we use in the real world, such as our voices, arecalled ”analog” signals. To process these signals in computers, we need to convertthe signals to ”digital” form. While an analog signal is continuous in both time andamplitude, a digital signal is discrete in both time and amplitude. To convert a signalfrom continuous time to discrete time, a process called sampling is used [23]. Thefigure4.2 is representing the sampling process.

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Figure 4.2: Sampling an analog signal

The value of the signal is measured at certain intervals in time. Each measure-ment is referred to as a sample. When the continuous analog signal is sampled at afrequency F, the resulting discrete signal has more frequency components than didthe analog signal. To be precise, the frequency components of the analog signal arerepeated at the sample rate. That is, in the discrete frequency response they are seenat their original position, and are also seen centered around +/- F, and around +/-2F, etc. If the signal contains high frequency components, we will need to sample ata higher rate to avoid losing information that is in the signal. In general, to preservethe full information in the signal, it is necessary to sample at twice the maximumfrequency of the signal. This is known as the Nyquist rate. The frequency spectrumof a signal sampled at greater than Nyquist rate is shown in the figure 4.3 [23].

Figure 4.3: (a)Spectrum of unsampled waveform (b)Spectrum of sampling function(c)Spectrum of sampled waveform

The Sampling Theorem states that a signal can be exactly reproduced if it issampled at a frequency where F is greater than twice the maximum frequency in thesignal. If the sampling law theorem is not obeyed then if the signal is converted backinto a continuous time signal, it will exhibit a phenomenon called aliasing.

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4.1.5 Aliasing

Aliasing is the presence of unwanted components in the reconstructed signal. Thesecomponents were not present when the original signal was sampled. In addition,some of the frequencies in the original signal may be lost in the reconstructed signal.Aliasing occurs because signal frequencies can overlap if the sampling frequency is toolow. Sometimes the maximum frequencies components of a signal are simply noise,or do not contain useful information. To prevent aliasing of these frequencies, we canfilter out these components before sampling the signal. Because we are filtering outhigh frequency components and letting lower frequency components through, this isknown as low-pass filtering [23]. The figure 4.4 shows aliasing phenomena.

Figure 4.4: Aliasing phenomena

4.2 Types Of Analog to Digital Conversions

There are different methods for analog to digital conversion. The choice of methodis fairly dependent on the type of application one needs. Following are some types ofanalog to digital converters [22].

1. Flash ADC

2. Dual Slope

3. Successive approximation

4. Sigma delta ADC

The above are the different techniques to get the digitized form of the respectiveanalog signal. Every technique has different advantages and disadvantages in theprocedure of their selection criteria for a specific application.

4.2.1 Selection Of ADC Type

While selecting a technique for the analog to digital conversion there are differentparameters which are necessary to look at before making the final selection of the

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converter type for the specific application. According to the specifications of myapplication I need to convert an analog signal of 0-1(ampere) and 0-110(volts) signalwith input frequency of 50 Hz to digital form with a high resolution of 14-bit to 16-bit.

4.3 Principle Of Flash ADC

The basic principle of Flash ADC is illustrated for the sake of understanding, thathow it converts an incoming analog signal to the digital form.

4.3.1 Voltage Comparator

In electronics, a comparator is a device which compares two voltages or currents andswitches its output to indicate which is larger. More generally, the term is also usedto refer to a device that compares two items of data. Output voltage will switchwhenever the input voltage (at the inverting input) reaches the reference voltage Vref(at the non-inverting input). The figure 4.5 shows the schematic for the comparator.When a comparator performs the function of telling if an input voltage is aboveor below a given threshold, it is essentially performing a 1-bit quantization. Thisfunction is used in nearly all analog to digital converters (such as flash, pipeline,successive approximation, delta-sigma modulation, folding, interpolating, dual-slopeand others) in combination with other devices to achieve a multi-bit quantization[24].

Figure 4.5: Voltage Comparator

First of all the basic 3-bit resolution is achieved by using the spontaneousmethod of analog to digital conversion. The Flash ADC is modeled in the SIMULINK.

4.3.2 Flash ADC Modelling

This is the fastest and spontaneous way of converting the analog signals to digitalsignals. It uses the comparator and a bunch of resistors in a characterized way toperform the desired operation. The Flash ADC is modeled in the SIMULINK usingSimScape and SimPowerSystems libraries. The analog signals from the instrumenttransformers are fed to the Flash ADC which are converted to the digital form. After

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conversion to digital form they are converted to the binary form by applying digitalsignals to the priority encoder which actually gives the output into 3-bit stream formaccording to the respective active input at that instant of time.

Advantages

1. Flash ADC is very fast and spontaneous.

2. It is simple in order to understand.

Disadvantages

1. It requires a large number of comparators compared to other ADCs, as theprecision increases.

2. Due to the increase in the circuitry components more power is dissipated.

The schematic of Flash ADC is given in the figure 4.6.

Figure 4.6: Flash ADC schematic [3]

4.3.3 Priority Encoder

A priority encoder is a circuit or algorithm that compresses multiple binary inputsinto a smaller number of outputs. The output of a priority encoder is the binaryrepresentation of the ordinal number starting from zero of the most significant inputbit. If two or more inputs are given at the same time, the input having the highestpriority will take precedence [22]. In this case the 3-bit binary stream is the outputfrom the priority encoder representing the decimal number from 0 to 7. The logicalcircuit for the 8-bit to 3-bit encoder is given in figure 4.7.

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Figure 4.7: Priority Encoder SIMULINK model 8-3 bit

The detailed SIMULINK design model for Flash ADC is given in figure 4.8.

Figure 4.8: Detailed Flash ADC model in SIMULINK

The different blocks and the internal settings for them are described below.

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MATLAB/SIMULINK Simscape1 toolbox is mainly used to implement this 3-bitFlash ADC. The main block comprises of Voltage Comparators, Resistors, Physicalsignal to Simulink, Logical gates and Voltage sensor.

Figure 4.9: MATLAB/SIMULINK Simscape Toolbox

Description Of SIMULINK Blocks Implemented

1. The PS-Simulink converter block converts a physical signal to a simulink outputsignal. This block is used to connect the outputs of a physical network diagramto Simulink scopes or other Simulink blocks.

2. Each topologically distinct Simscape block diagram requires exactly one SolverConfiguration block to be connected to it. Each physical network representedby a connected Simscape block diagram requires solver settings information forsimulation. The Solver Configuration block specifies the solver parameters thatthe model needs before the simulation is begin.

3. Comparator block is from the integrated circuit library of Simscape toolbox.This block models the gate output as a voltage source driving a series resistorand a capacitor that connects to ground. The block models differential inputselectrically as having infinite resistance and a finite or zero capacitance. If thedifference in the inputs is greater than the input threshold voltage, then theoutput is equal to the High level output voltage. Otherwise, the output is equalto the Low level output voltage.

4. The Voltage Sensor block represents an ideal voltage sensor, that is, a devicethat converts voltage measured between two points of an electrical circuit intoa physical signal proportional to the voltage.

1MATLAB SIMULINK Library

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5. The last three blocks are logical AND, OR, and NOT gates which behave ac-cording to their logical operation defined [25].

4.4 Sigma-Delta Analog To Digital Converter

Sigma-Delta ADCs have been receiving increased attention as an alternative to theconventional ADCs. The conventional ADCs use precision elements to maintain res-olution and accuracy. Whereas Sigma-Delta ADC produces conversions with just1-bit of resolution at very high sampling rate. Also, Delta-Sigma converters maybe superior for data acquisition because of good overall noise performance[26]. TheDelta-Sigma converter consists of two main components, a Delta-Sigma modulatorand a digital filter. The modulator part consists of an analog filter and a coarsequantizer enclosed in a feedback loop[27]. The feedback loop and the filter attenuatethe quantization noise at low frequencies while emphasizing the high-frequency noise(noise shaping). With noise shaping, the quantization noise effects in the band ofinterest can be dramatically reduced. The very high sampling rate and noise shap-ing allow the 1-bit Delta-Sigma to have the same performance as 16-bits or higherof quantization[28]. The literature study and the requirement of the MU productdevelopment lead to this type of ADC which is quite famous for the high resolutionand as noise shaping modulator.

4.4.1 Why Sigma-Delta ADC?

The sigma-delta ADC is the converter of choice for modern voice band, audio, andhigh resolution precision in industrial measurement applications. The digital architec-ture of sigma-delta is suited for modern fine-line CMOS processes, thereby allowingeasy addition of digital functionality without significantly increasing the cost. Thefundamental concepts of oversampling, quantization noise, digital filtering, and deci-mation will be discussed later in the chapter [29].In the application development forthis thesis work first order sigma-delta modulator is used. The input signal frequencyof 50 Hz is oversampled to a rate of much larger than the Nyquist rate to achieve thedesired resolution. Oversampling is not the only way to get higher resolution; insteadthe decimation is also performed on the digital signal to get the desired resolution of16-bit and output of 4 kHz data rate.

4.4.2 Sigma-Delta Modulator Working

Figure 4.10 shows the first order sigma delta modulator which is used in this applica-tion development of MU. The input signal X comes into the modulator via summingjunction. It then passes through the integrator which feeds a comparator that actsas a 1-bit quantizer. The comparator output is fed back to the summing junction via

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1-bit digital to analog converter. It also passes through the digital filter and emergesat the output of the digital filter [4].

Figure 4.10: First order sigma-delta ADC block diagram

The signal theory concepts will be described below before going deep into thesigma-delta ADC.

4.4.3 Signal Sampling

The sampling theorem states that the sampling frequency of a signal must be at leasttwice the signal frequency in order to recover the sampled signal without distortion.When a signal is sampled its input spectrum is copied and mirrored at multiples ofthe sampling frequency fs. The figure 4.11 depicts the spectrum of a signal when thesampling theorem is violated [29].

Figure 4.11: Under-sampled signal spectrum

In the figure 4.11 the sampling frequency is less than the twice of input fre-quency. The shaded area on the plot shows what is commonly referred to as aliasing.In figure 4.12 shows the spectrum of an oversampled signal. The oversampling processputs the entire input bandwidth at less than fs/2 and avoids the aliasing trap [4].

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Figure 4.12: Over-sampled signal spectrum

The one reason of using this technique in our product development is its over-sampling techniques which helps in avoiding the aliasing effect and also gives morerelaxation in the selection of analog and digital anti-aliasing filters.

4.4.4 Quantization Noise

Quantization noise (or quantization error) is one limiting factor for the dynamic rangeof an ADC. This error is actually the round-off error that occurs when an analog signalis quantized. For example, Figure 13 shows the output codes and corresponding inputvoltages for a 2-bit A/D converter with a 3V full scale value. The figure shows thatinput values of 0V, 1V, 2V, and 3V correspond to digital output codes of 00, 01, 10,and 11 respectively. If an input of 1.75V is applied to this converter, the resultingoutput code would be 10 which correspond to a 2V input. The 0.25V error (2V -1.75V) that occurs during the quantization process is called the quantization error.Assuming the quantization error is random, which is normally true, the quantizationerror can be treated as random or white noise. Therefore, the quantization noisepower and RMS quantization voltage for an A/D converter are given by the followingequations [4].

e2RMS =1

q

∫ q2

−q2

e2de =q2

12V 2 (4.1)

eRMS =q√12

(4.2)

A quantized signal sampled at frequency fs has all of its noise power folded into the

Figure 4.13: Code example of a 2-bit A/D converter

28

frequency band of 0 ≤ f ≤ fs/2. Assuming the noise is random, the spectral densityof the noise is given by:

E(f) = eRMS

(2

fs

) 12 V√

Hz(4.3)

By squaring above equation and integrating it the noise power over the band ofinterest is given by:

n2o = e2RMS

(2fofs

)V 2 (4.4)

no = eRMS

(2fofs

) 12

V (4.5)

Where no is the in-band quantization noise, fo is the input signal bandwidth, andfs is the sampling frequency. The quantity fs/2fo is generally referred to as theoversampling ratio or OSR. It is important to note that the oversampling reduces thein-band quantization noise by the square root of the OSR [4].

4.4.5 Sigma-Delta Modulator Quantization Noise

The results of the above sampling and noise theory can now be used to show howa sigma-delta modulator shapes quantization noise. The sampled data equivalentblock diagram of the first order sigma delta modulator is shown in the figure 4.14.The difference equation for the output of the modulator is given below and e is thequantization noise.

Yi = Xi−1 + (ei − ei−1) (4.6)

Figure 4.14: First order sigma-delta modulator sampled data equivalent block dia-gram

Assuming the input signal is active enough to consider the error as white noise,the spectral density of the noise can be expressed as given below in mathematical form

29

[4].

N(f) = E(f)|1− e−jωfs | = 2eRMS

(2

fs

) 12

sin

(ω

2fs

)(V√Hz

)(4.7)

The noise power in the bandwidth of interest is given by

n2o = e2RMS

π2

3

(2fofs

)V 2 (4.8)

Therefore the generalized formula for the Mth order modulator is provided below.

no = eRMS

(πM

√2M + 1

)(2fofs

)M+ 12

V (4.9)

If the sampling frequency is doubled the in-band quantization noise will be decreasedby 3(2M+1) dB.

4.4.6 Order Of Modulator And Quantization Noise

As the modulator order is increased from first order to second order the quantizationnoise is reduced. Therefore by increasing the order of the sigma delta modulator thenoise can be reduced but at the same time the greater the order of modulator moreunstable the modulator will be. There will be a tradeoff on the order of the modulatorto work it in the stable region. The figure 4.15 showS the relationship between sigmadelta modulator order and quantization noise [4].

Figure 4.15: SNR VS Oversampling ratio for sigma-delta modulators[4]

The first order sigma-delta ADC modulator model is developed and used inthe development of merging unit for this thesis work.

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4.4.7 SNR Of Sigma-Delta ADC

Signal to noise ratio plays an important role in the strength of the signal to bemeasured. The resolution for the protection signal according to standard is 16-bit.Inorder to get the 16-bit resolution the SNR of the signal must be greater than 90 dB.The SNR of the sigma-delta ADC is calculated by using the following equation[30].

SNR = 6.02N + 1.76 + 10log10

(fs2fo

)(4.10)

Where N is the number of bits, fs is the sampling frequency and fo is the frequencyof the input signal either current or voltage. According to our requirements thevalue of N=16, fs=64 KHz and fo=50 Hz.By putting the values of known variablesin equation (10) the SNR theoretically calculated value is 126.142 dB. Thereforetheoretical value is clearly greater than 90 dB which gives us the output bit resolutionconfirmation of 16-bits. The simulated value is calculated in MATLAB and thegraphical representation of SNR and frequency is given in the figure below.

Figure 4.16: Frequency Spectrum

From the figure 4.16 it is clear that the simulated SNR value is a little smallerthan the theoretical value. Even then simulated value is much greater than 90 dB,which is still approving the requirements needed in the signal strength. When we havethe SNR the term known as effective number of bits (ENOB) can also be calculatedwith the following equation.

ENOB =

(SNR− 1.76

6.02

)(4.11)

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4.5 Complete SIMULINK Model Of Sigma-Delta ADC

The detailed sigma delta model of ADC developed in SIMULINK is given in figure4.17 and explained under.

Figure 4.17: Sigma-Delta ADC model in SIMULINK

In SIMULINK the DSP2 System Toolbox is used in the modelling of sigma-delta ADC. The overall blocks which are used are given in the figure 4.18. The mainsignal processing blocks are from the DSP Toolbox which is related to the analogsignal processing, sampling, digital signal processing and digital filtering along withdown sampling.

2MATLAB/SIMULINK Library

32

Figure 4.18: MATLAB/SIMULINK DSP Toolbox

4.5.1 Analog Filter Design Block

The block for analog filter design is given above in the figure16. In this design theanalog filter which is designed is the Butterworth filter used for the analog signalprocessing on the incoming current or voltage signal. This filter is used to protectaliasing in the frequency band of signals.

Details Of Parameters

The details of the analog filter design demands the following values from the user.

33

Figure 4.19: Analog Filter Block Parameter Details

4.5.2 Integrator Block

The block of integrator is shown above in the figure16. The function of this block isto take the integral of the incoming input.

Details Of Parameters

The detail settings of this block are given below.

Figure 4.20: Integrator Block Parameter Details

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4.5.3 Signum Block

This block is in the Math Operations library of SIMULINK. It indicates the sign ofthe input signal. Here it is used as a1-bit quantizer for the quantization process inthe analog to digital conversion.

Details Of Parameters

The detail settings of this block are given below.

Figure 4.21: Signum Block Parameter Details

This block function is to give a positive 1 if the input is positive and a negative1 if input is negative and zero if the input is zero.

4.5.4 Zero Order Hold Block

This function block is in the SIMULINK/DISCRETE Library and is shown in thefigure16. It implements a zero order hold of one sample period. In simple words itconverts the continuous time signal to discrete time signal.

Details Of Parameters

Parameter details are given in detail as under.

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Figure 4.22: Zero order hold Block Parameter Details

4.5.5 FIR Decimation Block

This block is in the DSP Systems Toolbox in Filtering/Multi-rate Filters Library.The function of this block is to apply digital filtering and down sample the inputdigital signal to the desired rate.

Details Of Parameters

Figure 4.23: FIR Decimation Block Parameter Details

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Figure 4.24: FIR Decimation Block Parameter Details

4.5.6 Transport Delay Block

This block is used to delay the input signal to a certain value. The Transport Delayblock delays the input by a specified amount of time. You can use this block tosimulate a time delay. The input to this block should be a continuous signal.

Details Of Parameters

Figure 4.25: Transport Delay Block Parameter Details

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4.6 Comprehensive Sigma-Delta Design Explanation

The complete sequence of operations for AD conversion from analog input signal tothe digitized output signal is given in the detailed figure 4.26. For the sake of betterunderstanding only one phase is considered either it is current or voltage with 50 Hzfrequency normally. Analog signal processing is done first on the input signal thenthe ADC modulator converts the processed analog signal to the digital signal whichalso contains noise in it. In order to remove the noise and to get back the equivalentdigitized signal at the output digital filtering and down sampling is done in the lastsection of the sigma-delta AD converter. According to the standard the 4 KHz datarate is required at the output with a 16-bit of resolution.

Figure 4.26: Detailed model with explanation

After explaining above all the details of the Simulink modeling and the func-tionalities of the ADC model it is worth mentioning that the flexibility in this specificADC design is of quite big range. Any input analog signal having defined specifica-tions can be converted to the digital form by tuning the input output filters and byputting the required sampling rate and output data rate.

38

4.7 Simulation Results

The ADC model is simulated and the final step by step results are collected in theform of Simulink graphs. These results are presented in the sequence as the ADCmodel performs the processing on the input signal in the different sections of the ADCmodel.

Result Before Modulator Action

Figure 4.27 shows the input signal waveform in the upper part of the graph andthe lower part shows the sampled signal for the equivalent input analog signal. Forall the figures below, the x-axis is the time axis and the y-axis is for the amplituderepresentation.

Figure 4.27: Simulated Sampled Signal Output

Result After Modulator Action

In the modulator section of ADC model the sampled signal is 1-bit quantized. Infigure 4.28 upper part of the graph shows the analog input signal and the lower partof the graph shows the quantized signal with some noise.

Figure 4.28: Analog Signal and Simulated Quantized Signal with error

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Final Digital Output

The final figure gives the digitized form of the analog input signal. There are threeparts in the figure 4.29, the upper part of the graph shows the analog input signal,the middle part shows the final digital form of the analog input signal and the lowestpart of the figure gives the total error between the input analog signal and the outputdigital signal. The error is approximately ± 5 %.

Figure 4.29: Final Digital Signal Output

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Chapter 5

Modelling Of Power System InSIMULINK

5.1 Introduction

This chapter comprises of the modelling of a multi-bus power system in SimPower-Systems for different scenario simulations.The chapter starts with the introduction to the overall power system with differentcomponents in it. After the power system has been developed the MUs are placed atthe different nodes in the power system to get the three phase voltage and currentmeasurements. After the measurements have been collected then these measurementsare sent on to the Ethernet port in the form of SV (Sampled Value) stream. Thecreation of SV (sampled value) stream of the digitized voltage and current signals isthe part of Project Part-B.

5.1.1 Power System Modelling

In order to test the developed product of MU the next task was to model a power sys-tem which can give the simulated values during normal and fault conditions to checkthe flexibility and dynamics of the MU. In this task towards the accomplishment of thethesis was to model a power system with multiple nodes in the MATLAB/SIMULINKSimPowerSystems Toolbox.The reason for choosing SimPowerSystems Toolbox is be-cause it operates in the Simulink environment and is dedicated tool for modellingand simulating the generation, transmission, distribution, and utilization of electricalpower. It includes models of three phase electric voltage source, transmission line,load, transformers. The motivation in using SimPowerSystems is because SimPower-Systems is compatible with the OPAL-RT Real Time Simulator and can be used totest the overall system in the real time environment.

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5.1.2 Power System Modelling In SimPowerSystems

The single line diagram of the power system which was modelled in the SimPower-Systems is shown in the figure 5.1.

Figure 5.1: Single line diagram of Test System

The figure shows various power system components connected together to forma power system model. The details of these components and their respective param-eter settings are discussed below.

5.2 List Of SimPowerSystems Blocks Used

The used components are presented in the following list and are explained one byone.

1. Three phase Programmable Voltage Source

2. Three phase Two Winding Transformer

3. Three phase Pi Model For Transmission Line

4. Three phase OLTC Regulating Transformer

5. Three phase Series RLC Load

6. Three phase Fault

7. Three phase Discrete Sequence Analyser

8. Power GUI Block

5.2.1 Three phase Programmable Voltage Source

In SimPowerSystems library , the electrical sources category contains various voltagesources which are based on the requirement of the modelling a certain power system.In this thesis the three phase programmable voltage source is used. The figure 5.2shows the block used in the model.

42

Figure 5.2: Three phase Programmable Voltage Source Block

Inputs And Outputs Of Block

The left side terminal denoted by ”n” is to connect the source to the ground terminalexternally. The A B and C terminals represents the three phases of voltages withprogrammable time variation of amplitude, frequency, phase and harmonics.

Details of Parameters

43

Figure 5.3: Three phase Programmable Voltage Source Block Parameter Details

In this thesis work the programmable source is used to inject 2nd harmonic contentalong with fundamental to check the data acquisition property of the MU. Also tosee how the MU behave when sudden changes happen in voltage, frequency duringcertain time intervals.

5.2.2 Three Phase Transformer

The power system model shown in the figure 5.1 consists of a three phase transformer.This transformer is modelled by using three phase transformer block in the elementscategory of SimPowerSystems library as shown in the figure 5.4.

44

Figure 5.4: Three phase Two Winding Transformer Block

The block models three phase transformers using three single phase transform-ers. The model takes into account the winding resistances and inductances alongwith the magnetizing characteristics of the core. The transformer between bus 1 andbus 2 is a step down transformer with primary connected to 100 KV secondary isconnected to 33 KV.

Inputs and Outputs of Block

The terminals A B C represents the primary side of the transformer and the terminalsa b c represents the secondary side of the transformer. Transformer can be used as stepup and step down by using the appropriate voltage levels at primary and secondarywindings of the transformer.

Details of Parameters

Figure 5.5: Three phase Two Winding Advance Parameter Details

45

Figure 5.6: Three phase Two Winding Transformer Parameter Details

Figure 5.7: Three phase Two Winding Transformer Parameter Details

46

5.2.3 Three Phase PI Section Line

The transmission line between bus 2 to bus 3 is modelled by using three phase PIsection linie block available in the elements category of the SimPowerSystems libraryas shown in the figure 5.8.

Figure 5.8: Three Phase PI Section Line Block

This blocks implements a balanced three phase transmission line with param-eters lumped in a PI section line.

Inputs and Outputs of Block

The terminals on both sides of the block represent the two ends of a transmissionline. The parameters provided for the transmission line will implement a Pi sectionline within these two terminals of a block.

Figure 5.9: Three Phase PI Section Line parameter details

47

5.2.4 Three Phase OLTC

The three phase OLTC transformer block available in the transformer category of theapplication library of SimPowerSystems is phasor type. However the aim is to modelthis system in discrete mode. This phasor block can not be used in discrete mode.The OLTC block thus used for this purpose is available in the demo OLTC RegulatingTransformer(Phasor Model). This demo contains simple three phase OLTC regulatingtransformer and it is used here in our power system model for voltage regulation onbus 4.

Figure 5.10: Three Phase OLTC Block

This block models a three phase two winding transformer with on load tapchanger to regulate the voltage on the transmission or distribution network. Thismodel basically provides 17 taps i.e. +8 to -8 and tap position 0 represents nominalvoltage ratio.

Inputs and Outputs of Block

The terminals A B C represents three input terminals connected to winding 1.Termi-nals a b c represents the three terminals connected to winding 2. Vm is the voltagewhich is to be controlled. In this system model the 10 MW load is attached to theBus no 4 whose voltage is to be regulated. So we are feeding this Vm input with avoltage magnitude at Bus 4, ”m” ia an output which provides the metering facili-ties for various signals which can be chosen with the help of ”bus selector” block ofSimulink.

Parameter Details

48

Figure 5.11: Three Phase OLTC transformer parameter details

49

Figure 5.12: Three Phase OLTC voltage regulator parameter details

5.2.5 Three Phase Series RLC Load

This block implements three phase balanced load as a series combination of resistance,inductance and capacitance. The load provides a constant impedance. The blockdiagram is shown in the figure 5.13.

Figure 5.13: Three Phase Series RLC Load Block

Parameter Details

50

Figure 5.14: Three Phase Series RLC Load Parameter details

5.2.6 Three Phase Fault

As this model is also designed to study dynamics of power system i.e transient sta-bility, voltage stability in a sense to observe the behaviour of ADC and the packettransmission during different system conditions or to see the performance of the MU.Inthat sense a provision is given to the user to apply a three phase fault at the trans-mission line between the nodes 2 and 3 to check the system behaviour and at thesame time to check whether the developed product MU work with required accuracyor not. The three phase fault is applied by using the three phase fault block availablein the elements category of SimPowerSystems library.

Figure 5.15: Three Phase Fault Block

51

Inputs and Outputs of Block

The terminals A B C represents the three breakers inside the block which are con-nected to the ground through an internal ground resistance.

Parameter Details

Figure 5.16: Three Phase Fault Parameter Details

5.2.7 Metering Blocks

In order to monitor the voltages and currents in the system the three phase VImeasurement block is available in the measurement category of SimPowerSystemslibrary.

52

Figure 5.17: Three Phase VI Measurement Block

This block measures the three phase instantaneous currents and voltages in acircuit.Either phase to phase or phase to ground can be measured with the help ofthree phase VI measurement block.

Inputs and Outputs of Block

Vabc and Iabc are the outputs containing three phase currents and voltages measure-ments. Terminals A B C are the input terminals and a b c are the output terminals.This block is often used as a bus in the model and gives output same as the input tothe bus.

Parameter Details

53

Figure 5.18: Three Phase VI Measurement Parameter Details

5.2.8 Discrete Three Phase Sequence Analyser

Another metering block used is discrete three phase sequence analyser.As the signalsfrom the three phase measurement blocks are the three phase voltages and currents inper unit, so these signals are fed to the sequence analyser to get the positive sequencevoltages and currents in per unit which are then monitored with the help of scope.It is available in discrete measurement subcategory of the measurements category inSimPowerSystems libraary.

54

Figure 5.19: Discrete Three Phase Sequence Analyser Block

Inputs and Outputs of Block

The input abc can be either Voltage Vabc OR Iabc generated by the three phase VImeasurement block. The output magnitude and phase is the value of the positivesequence voltage or current.

Parameter Details

Figure 5.20: Discrete Three Phase Sequence Analyser Parameter Details

However all the signal monitoring is done through the scope block present inthe commonly used blocks category of Simulink.

5.2.9 Power GUI Block

It is the environment block for the SimPowerSystems models and provides multiplefunctions. This block is present in the main library of SimPowerSystems. The detailsof this block are explained below.

55

Figure 5.21: Power GUI Block

Details of Power GUI Block

Figure 5.22: Power GUI Configuration Settings

56

Figure 5.23: Power GUI Configuration Settings

57

Figure 5.24: Power GUI Analysis Tools

5.3 Full Modelled Power System

Power system model comprises of 100 KV programmable voltage source, 1-100/33KV step down transformer, 4-buses, 10 Km transmission line, 10 MW load attachedto the bus 4. A OLTC voltage regulator 33/33 KV is placed between bus 3 and bus4 to stabilise the voltage on the bus 4 and keep it to the nominal value.

Figure 5.25: Three Phase Power System Modelled in Simulink

58

5.3.1 Purpose of Power System

The main reasons behind the modelling of power system in this study work is to testthe developed MU for different scenarios. The scenarios which will be produced bysimulating the above power system under different parameter settings. Once thesescenarios have been developed then the performance of the modelled MU can betested. These scenarios are listed below, but the details of these scenarios will beexplained in the next chapter.

1. Executing Three Phase Symmetrical Fault near Bus2 for Over current Protec-tion Function Testing of RET 670 IED

2. Executing Single Phase to Ground Fault For Unsymmetrical Faults of RET 670IED

3. Injection of 2nd Harmonic Content to Test Harmonic Restrain Function of RET670 IED

4. Voltage Stability Test

5. Testing of Transformer Differential Protection Function

The MU can be connected to any of the bus or at all buses to get valuesand transmit them to the IED. However the power system will be simulated underdifferent parameter conditions to test the MU performance.

59

Chapter 6

Complete Test Platform

6.1 Background

This chapter comprises of scenarios listed in the previous chapter for the testing ofthe developed models. First of all the full testing scheme will be presented. Theintroduction of the hardware and the software used to accomplish the testing ofMerging Unit will be given before the testing function details.

6.2 Physical Test Platform

There are quite a few test schemes already existed and used for the testing of MergingUnit. One of these test platform is presented here in order to support the test setupdesigned for the testing of soft Merging Unit in this thesis work. This test comprisesof all the physical models of all the participating devices but the test setup used in thisthesis work is comprises of all the components modelled in Simulink. In order to testthe digital protection system using optical instrument transformers interconnectedby an IEC 61850-9-2 process bus, Arizona State University (ASU) has developed adedicated test facility. The major components in the system are, the current generatorof the test set up, NxtPhase optical current transformer (OCT), with Merging Unit(MU), AREVA digital relay and a computer. The over current protection function istested in this setup. The SV traffic stream is sent to the digital relay and the relaysends the trip message after detecting the over current fault [5]. The test facility ispresented in the figure 6.1.

60

Figure 6.1: Picture of the test setup for the all-digital over-current protection[5]

6.3 Protection Function Testing Tools

The testing of different protection functions is done through the following testingscheme. Testing scheme consists of the following hardware and software tools.

6.3.1 Hardware Tools

As the motivation behind this thesis work is to develop a soft Merging Unit whichcan be used and simulate on a student MATLAB/SIMULINK environment whereyou can have the opportunity to work on such an advance device without any accessissues which surely lies with the vendor manufactured Merging Units.

1. Ordinary Lab Computer

2. RuggedSwitch RS900

3. IED RET 670

61

6.3.2 Software Tools

As we have developed the soft Merging Unit consists of the parts which are modelledin a working environment which is easily accessible by activating student licenserequirements.

1. MATLAB/SIMULINK

2. C language

3. PCM 600

4. Wireshark

6.4 Lab Setup for the Soft Merging Unit Testing

The figures 6.2 and 6.3 show the setup in the lab for the testing of protection functionsby soft Merging Unit.

Figure 6.2: Lab Setup for Soft Merging Unit for Protection Function Testing

62

Figure 6.3: Lab Setup for Soft Merging Unit for Protection Function Testing

6.5 Complete System Integration

The procedure for the testing of different protection functions includes the integrationof all the developed models. In first step the CT/PT models are connected to thedifferent nodes of developed power system in order to convert the higher voltages andcurrents to the level of low voltages and currents. In the second step the ADC modelsare connected to the outputs of the CT/PT to convert analog signals to the digitalform.In the third step the transmission part is attached to transmit the digitized datato the Ethernet port according to the IEC 61850-9-2 Sampled Value protocol. In thefourth step the SV stream is fed to the ABB IED RET 670 through a RuggedcomSwitch to operate the IED for the desired protection.

63

Figure 6.4: Protection Function Testing Scheme

6.5.1 Protection Function Testing Scheme

The pictorial representation of the test scheme is given in figure6.5.

Figure 6.5: Protection Function Testing Scheme

64

All kinds of scenario testing will be done with this basic testing scheme. Theonly constraint which will be changing for each scenario is the parametrization of thepower system components to check the performance of developed components.

6.5.2 Description of Hardware and Software

A personal computer with MATLAB/SIMULINK software tool installed on it pro-vides the dynamic and flexible environment to model any type of system. In ourproject the specifications of the computer are 2.00 GB of memory (RAM) and IntelCore 2 DUO CPU of 2.53 GHz. An Ethernet switch is required to send the data fromthe sending end to the destination address. In our case the RuggedSwitch RS900 isused for the sending of SV stream to the IED RET 670. The RuggedSwitch RS900 isa 9 port industrially hardened, fully managed , Ethernet switch specifically designedto operate reliably in electrically harsh and climatically demanding environments. Itprovides a high level of immunity to electromagnetic interference and heavy electricalsurges[31]. As this research study is collaborated with ABB so we are provided withRET 670 IED which is a differential protection relay for transformers. The softwaretool PCM 600 is used to configure the RET 670 for over current and differentialprotection of transformer.

6.6 Over-current Protection Scenario

The purpose of this scenario is to test the working of the Merging Unit during normaland fault condition measurements received from the power system.

Power transformers can have large inrush currents in the energizing process.This is due to the saturation of the transformer core.The inrush current has a largecontent of 2nd harmonic. Due to these inrush currents there is a risk that thesecurrents will reach the level above the pick up current of the phase over currentprotection. This gives the risk of an unwanted trip. In order to get rid of thisunwanted trip there is a 2nd harmonic restrain blocking function. This componentcan be used to create a restrain signal to prevent this unwanted trip[32].

It would be interesting here to first analyse whether the RET 670 recognisesthe transmission of data by the Merging Unit or not and then to test the over currentprotection function for the 2 winding transformer.

6.6.1 Configuring IED RET 670

In order to make any kind of test on the MU it is necessary to configure the IED forthe MU. The software which is used to configure RET 670 is the PCM 600. The IEDcan be configured according to the functionalities already defined in the package ofthat IED. The model which is used in the study is basically a differential protection

65

relay for the transformer. It has main protection blocks for the configuration of 2-winding transformer protection, 3-winding transformer protection. There are lots ofother protection function blocks related to the internal protection of the transformer.There is also an over current protection block which will be used to configure the IEDRET 670 for the protection of 2-winding transformer from the over-currents due tothe large faults on the system.

6.6.2 Power System for Steady State Measurements

The complete system used for the measurements during the steady state is a 3-buspower system which is comprises of a three phase source, a 2-winding step downtransformer, 10 Km long transmission line and a 10MW load. The values from anynode of the power system can be taken and send to the IED. As the values from thesending end are known and can be verified by reading on the HMI screen of the RET670 IED. System for steady state test is shown in the figure 6.6.

Figure 6.6: Power System with MUs attached to the Nodes

It is very important to brief about the .mat files which are saving data fromthe power system during off-line simulations. These files are then directly read bythe Part-B of the Project and the SV stream is sent to the IED, which explains thewhole purpose of this project.

66

6.6.3 Application Configuration in PCM 600

Before going to check complex functions on the Merging Unit the first test is toapprove that the MU is working properly and sending the data according to theIEC 61850-9-2 standard. However to check and confirm the steady state process thesending end values from the power system developed in the Simulink can be checkedon the local HMI of the IED after configuring it for the MU and SV stream.Theblocks which are configured in the PCM 600 for steady state measurement of the SVstream are shown in the figure6.7.

Figure 6.7: Application Configuration for Monitoring Function In PCM600

The block named ”VMMXU” and ”CMMXU” are used to configure the mon-itoring functions for the measured values of voltages and currents. Now the valueswhich are sent by the MU can be seen on the IED HMI. When these values werechecked, the sending end values and the values which appeared on the HMI of IEDwere same. These values are the RMS 3-phase voltages and currents.

6.6.4 Simulation Values at Node 2

The steady state values of 3-phase voltages and currents on the secondary side ofthe transformer is shown in the scope. The figure 6.8 shows the steady state valuescaptured in off-line simulations.

67

Figure 6.8: Three phase Voltages and Currents at BUS 2

6.6.5 Screenshot of IED RET 670 HMI

The SV stream read by the IED is shown on the HMI. The 4I and 4V are beingmonitored by the IED. All these values are RMS values of currents and voltages.Screen shot of IED HMI is shown in the figure 6.9.

68

Figure 6.9: Steady State Values

6.6.6 Transient State Test and Over-Current Protection

In order to analyse the behaviour of the MU during the transient state the powersystem is subjected to the sever short circuit fault. A three phase to ground symmet-rical fault is applied on the secondary side of the 2-winding transformer to create thetransient scenario. The transient case scenario also gives the opportunity to test theover current protection function. The system used for this test is shown in the figure6.10.

69

Figure 6.10: Power System with Three Phase Short Circuit Fault

The interesting point about the testing of MU involves how it responds to thetransient values produced by the three phase to ground short circuit fault. It will beanalysed that whether the correct values are shown on the IED HMI or not. In orderto test the over current protection function the instant the fault current crosses theset threshold value of the current the IED must give a trip signal to confirm that theeverything responded to the abnormal condition.

6.6.7 Configuration of Over-Current Protection in PCM 600

The application configuration includes the configuration of Four step phase over-current protection block named ”OC4PTOC”. The four step over-current protectionfunction has an inverse or definite time delay independent for each step separately.The protection design can be divided in four steps[32].

• The direction element

• The harmonic restraint blocking function

• The four step over current function

• The mode selection

70

From the above four parts the simple four step over current and harmonic restraintblocking function are configured in application and parameter settings. The moredetails about the parameter settings are attached in the appendix for the betterunderstanding of reader. The block used for configuring the over-current protectionis shown in the figure6.11.

Figure 6.11: Four Step Over-current Protection Block OC4PTOC

The different trip signals are assigned to different LED’s on the local HMIof the IED RET 670 to visualise the protection function working properly. For thecase of over-current protection each phase current values area compared with the setoperation current values in a comparator block. If the values of phase currents forsome reason exceeds the set operation values the trip will be activated.

6.6.8 Parameter Settings for Over current Protection

The Table 6.1 shows the Parameter settings of 4 step over current protection function.In the following table the four step over current protection function parameters areset to test the over current protection. There are four steps each step can be set withdifferent threshold values of current and the time to activate the trip. Similarly thereare four pickup currents for each step. In the following parameter settings the firststep will be activated when the pick up current will rise up to 175% of the base valueof the current which is set to 170 amperes. This trip will be activated after waitingfor 5 seconds. The second step will be activated when the pick up current will riseup to 250% of the base value of the current which is set to 170 amperes. This tripwill be activated after waiting for 2.5 seconds seconds.The third step will be activatedwhen the pick up current will rise up to 500% of the base value of the current which

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is set to 170 amperes. This trip will be activated after waiting for 1 second. Thefourth step will be activated when the pick up current will rise up to 1000% of thebase value of the current which is set to 170 amperes. This trip will be activatedsimultaneously due to too high short circuit currents which probably gives the deadshort circuit condition. For more details on the overcurrent test which includes theparameter and application configurations of the digital relay (ABB RET 670 IED)are presented in the appendix A.

GeneralParameters Values

Ibase 170AStartPhSel 3 out of 3

Step 1 Step 2Parameters Values Parameters Values

I1> 175% I2> 250%t1> 5s t2> 2.5s

Step 3 Step 4I3> 500% I4> 1000%t3> 1s t4> 0s

Table 6.1: OC4PTOC parameters

6.6.9 Simulation Values at Node 2 During Fault

Three phase voltages and currents values for off line simulations when a three phaseto ground short circuit fault is applied on the secondary side of the 2 winding trans-former. The simulated values on the BUS 2 are shown in the figure 6.12.

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Figure 6.12: Three Phase Voltages and Currents at BUS 2

6.6.10 Screenshot of Local HMI of IED RET670

The figure 6.13 shows the transient state values of 4I and 4V during the three phaseshort circuit state. The trip command is activated by the IED RET 670 in order toprotect the transformer from over current fault.

Figure 6.13: Transient State During Three Phase Short Circuit

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6.7 Additional Tests

The test platform is available along with complete test setup. The developed productis available to test for different functionalities. The additional tests like injection ofadditional harmonics along with fundamental frequency, putting an unsymmetricalfault would be quite interesting to see the response of MU.

6.7.1 Response of MU Under Unsymmetrical Fault

This test is performed to check if the MU work properly during unsymmetrical faultsor breaks down. For this test one phase to ground fault was applied to the secondaryside of the power system. The measurements are collected by the MU attached atbus 2. This measurement of three phase currents and voltages due to unsymmetricalfault is transferred to IED RET670 according to the IEC 61850-9-2 SV stream. Thelocal HMI of IED can be visualised to verify the values from both ends, values atsimulation and the values picked up by the IED from the MU. The same system as inthe figure 6.10 is used with different set of parameters to apply unsymmetrical fault.The simulation results obtained from the power system are in figure6.14 and the IEDRET 670 local HMI Snapshot is also shown.

Figure 6.14: Three Phase Voltages and Currents at BUS 2 During UnsymmetricalFault

6.7.2 Response of MU Under Harmonic Injection by Source

This test is simulate to expose the MU under another different condition to analysethe behaviour of the MU. In this test besides fundamental harmonic two additionalharmonics are injected and in the similar way the measurement are taken at the bus

74

2 and then checked at the local HMI of the IED for verification. The test system usedis shown in the figure6.15.

Figure 6.15: Test System for Harmonic Injection

The power system simulation results at bus 2 with the injection of 3rd and 5thharmonic is shown in the figure6.16.

75

Figure 6.16: Three Phase Voltages and Currents at BUS 2 With Harmonic Injection

6.7.3 Response of MU Under OLTC Operation

In this test the OLTC voltage regulator is used as to regulate the voltage on the bus4. The voltage magnitude is fed as input to the OLTC to keep the continuous trackof the voltage on the bus 4. If for some reason the voltage on the bus 4 drops downit will operate and keep the voltage to the nominal 1 p.u. according to the controlsettings in the OLTC. While voltage regulation process is working continuously it isquite interesting to see how the MU give response and transmit the value to the IED.In order to monitor the measurements at the buses 3 and 4 each bus is connectedwith the MU. Also these measured values are verified on the local HMI of IED.Thesystem used for this test is shown in the figure 6.17.

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Figure 6.17: Voltage Regulation Monitoring Test System

For this test two MUs are subscribed and configured in the IED by PCM600.First the offline simulations are run and the data is stored in the .mat files. Thesestored data files are then read by the transmitting part of MU and SV stream is trans-ferred to the IED via Ethernet port according to IEC 61850-9-2 protocol. As boththe MUs are sending data from the same Computer they are not exact synchronised.The synchronization part is left to the future work.

6.7.4 Simulation Results on Bus 3 and 4

The voltage regulation on the bus 3 and bus 4 are shown in the scope in the figure6.18.The voltage value is shown in the p.u. value.

77

Figure 6.18: Voltage Regulation on Bus 3 and 4

The voltage is at its nominal 1.0 on both the buses. The tap changing is alsoshown in the figure 6.19.

Figure 6.19: Tap Position

The tap position changes according to the feedback given to the OLTC controlas Vm from the Bus 4. When the voltage magnitude at Bus 4 decreases or increasesthe tap adjusts its position by increasing or decreasing the number of windings.

6.8 Transformer Differential Protection Test

This test is explained in detail and is appended in the appendix A.

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Chapter 7

Results

This chapter presents the results of all the test cases. This section mainly shows theresults of all the cases after passing through the developed ADC model. Once theanalog waveforms are produced by the power system then these waveforms are fed toADC to convert them to digital form.

7.1 ADC output for Over current Protection

The ADC converts the analog input to digital form at 4KHz. The figures7.1,7.2 givesthe simulation results for over current protection case to show the ADC behaviourduring the steady state and the figures 7.3 7.4 shows transient state when three phaseto ground short circuit fault occurs.

Figure 7.1: ADC Output of Voltage During Steady State

79

Figure 7.2: ADC Output of Current During Steady State

Figure 7.3: ADC Output of Voltage During Transient State

80

Figure 7.4: ADC Output of Current During Transient State

The simulation results and the IED local HMI results during the off line testingverify the measured values by the power system and the visual result on the IED lacalHMI, as both have the same values.During fault the voltage goes to zero that is whatthe ADC is showing in the voltage output scope. when three phase short circuit faultoccurred the value of current goes 10-12 times to the nominal and the saturationoccurred in the CT which leads to the ADC, that is what ADC showing the transientin the current scope.

7.2 ADC Output During Harmonic Injection

Thus result presents the simulated output of ADC when the additional harmonicsare also added to the fundamental signal. The figures7.5,7.6 shows both three phasevoltages and currents in the scope.

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Figure 7.5: ADC Output of Voltage During Harmonic Injection

Figure 7.6: ADC Output of Current During Harmonic Injection

The output digitized signal is of 16-bit resolution and 4KHz of data rate whichis the requirement of this study work. The values shown in the scopes are scaleddown for signal processing. The ADC is flexible in converting the analog signals todigital signals in its range. There is not any exact upper and lower limit of scaleddown data that can be converted to the digital form by the modelled ADC. Basicallythe tuning of filters define the limit of a scaled down signal that can be converted todigital form with minimum error between the original and digitized signal.

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Chapter 8

Discussion

This thesis is the Part-A of the Project named development of a soft Merging Unit. InPart-A the instrumentation and signal processing modules are modelled in Simulink.The transmitter module in Part-B of the Project [9] is programmed in C language.Combining all the three modules gives us the developed model of a soft MergingUnit. The discussion includes the reliability, validity and evaluation of the whole softMerging Unit.

The idea behind the development of the soft merging unit is to have such a testscheme setup where you could easily attach your device to perform different kinds offunctionalities in order to test the reliability, validity and evaluation of that device.There are two interfaces between the 3 phase high voltage incoming conductors andthe protection relay (IED) in a substation.

The most important thing which is needed to mention here is the synchroniza-tion module of the MU. The SV messages are the time critical messages. The timestamp is needed when you have more than one MU in your test system. The syn-chronization part of this Project is in the pipeline and is recommended as the futurework due to the time constraint.

The first interface is to step down the high voltages and currents to the levelof monitoring and control. The second interface is the conversion of this step downmeasurement to the standardised form. The scaled down measurements are convertedto digital form upto 16-bit of resolution. The first interface is modelled in Simulinkwhich gives the realization of a conventional CT/PT. The CT/PT is used to stepdown the high voltages and currents to the 120V and 1A respectively. These stepdown analog values are further scaled down for the second interface to work properly.The second interface is modelled as an analog to digital converter with a workingrange of values from -1 to 1. Now the Part-B of the Project is used to transmitthese measured values from the power system to the ethernet cable connecting to the

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protection relay (IED) according to the IEC 61850-9-2 standard.

The idea was to integrate both the interfaces with the transmission part devel-oped in Part-B of the Project [9] by creating a S-function and connecting it directlyto the Part-A of the Project. We tried to run the whole simulation online but due tothe large number of computations in the ADCs and also due to the slow processing byS-function it was not appropriate to wait for a simulation which is actually run for 30seconds but in real time it was taking almost 1 hour so we leave this idea for furtherresearch due to the time constraint. We are aiming to try this out by using the UDPsend and UDP receive techniques to get the online realization of this simulation ofsoft MU.

In order to evaluate the soft MU the off-line testing is performed and theprotection relay successfully recognised the MU according to the IEC 61850-9-2 stan-dard.Then the on-line simulation is performed to check the response off IED to theSV stream send by the computer. The Part-B of the Project [9] use the reading of.mat files and replaying that data to the IED. Over current protection and differentialprotection for transformer is also configured and successfully implemented by usingthe soft MU. During off-line testing the digitized data is stored into the .mat files.

The advantage of this soft MU is that the utility persons and the academicresearchers can easily connect this MU to any of the modelled system without anyhesitation to test different scenarios according to the customer requirements. In con-trast if you need to connect a 1000 real MUs it could be extremely hard and costlyto set such a setup which could be of a huge price. Also the danger of loosing costlyequipment if any kind of disturbance occurs. Whereas with the facility of soft MUwe can test any kind of scenario depending on the demand from the utility.

Finally the soft MU is available to make a lot of tests on it. In order to inves-tigate soft MU more accurately we need to have more advanced networking tools. Byusing those software tools we can check the data rate, bit error rate (BER), packetloss, delay between two consecutive samples and total network traffic. The reliabil-ity of the MU can be checked by loading the network heavily and lightly to analysethe background traffic impact on the soft MU. These tests and analysis will be morehelpful in the validation and reliability of soft MU.

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Chapter 9

Future Recommendations

This chapter gives future recommendations about this thesis and also about the de-veloped soft Merging Unit.

9.1 Future work for this thesis

This thesis work comprises of models of CT/PT, ADCs and power system modelling.The recommended future work about all of theses individual components is listedbelow.

1. CT/PT models developed here are the ideal models which are giving the exacttransformation of currents and voltages at any condition. In the future workit is recommended that the CT/PT models should be of real kind which couldgive the realization of saturation effects due to core saturation during transients.This will help in more detailed analysis of the ADCs. It is recommended thatfor the modelling of CT the right choice of CT type must be considered becauseit affects the performance of relay with respect to time. The accuracy classand burden load should also be taken care of in the future design of the CTmodel[33].

2. In this thesis work one kind of ADC model is developed called Sigma-Deltawhich is considered for its cheapness and oversampling ration advantages. Butit would be quite interesting if we develop the ADC models with successive ap-proximation or dual slope types to also have a nice comparison among differentADC types. In this thesis work the first order sigma delta model is used. Theanalysis can be done by developing a second order Sigma-Delta ADC model.

3. In this study the simple power system is used to have a set of nice data ofvoltages and currents to feed MU under different scenarios. In future the morecomplexed power system can be developed with large number of buses havingMU attached to more than three buses. This will increase the analysis range

85

of the developed project. This power system is only used to test the ProcessBus. If the loop of the setup is completed by giving GOOSE trip message backto the breaker in the modelled power system then both the process and stationbuses can be seen working together.

9.2 Future work for the whole project

As the output of the Project is the soft Merging Unit. Some recommendations aboutthe future work On this developed product is listed.

1. The application of MU is to fulfil the IEC 61850-9-2 standard in the moderndigital substation. The sampled value messages are time critical and also needsto be synchronised. So the synchronization part of this MU is missing due totime constraint. It is recommended that the synchronization part should alsobe developed according to the IEEE 1588, a precision clock synchronizationprotocol.

2. The third application is to test the interoperability between the developed MUand different kind of IEDs manufactured by different vendors. The setup willhave all the three IEDs from ABB, AREVA and SIEMENS connected all to-gether and the MUs through a switch. The SV stream send to the ABB IEDand the trip command send by ABB IED to other IEDs will be interesting toanalyse. The figure 9.1 explains the idea of interoperability.

Figure 9.1: Interoperability Representation at Process Level

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[2] A. Apostolov, “Impact of iec 61850 on power quality monitoring and record-ing,” in Electricity Distribution-Part 1, 2009. CIRED 2009. 20th InternationalConference and Exhibition on, pp. 1–4, IET, 2009.

[3] T. R. Kuphaldt, Lessons In Electric Circuits, Volume IV Digital. Design ScienceLicense, fourth edition ed., November 01, 2007.

[4] D. Jarman, “A brief introduction to sigma delta conversion,” Application NoteAN9504, Intersil Corporation, pp. 1–7, 1995.

[5] S. Kucuksari and G. Karady, “Development of test facility for compatibility andperformance testing of all-digital protection systems connected to iec 61850-9-2standard,” in Power & Energy Society General Meeting, 2009. PES’09. IEEE,pp. 1–8, IEEE, 2009.

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[9] P. Zhao, “Iec61850-9-2 process bus communication interface for lighht weightmerging unit testing,” Master’s thesis, KTH, 2012.

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[13] D. Tholomier and D. Chatrefou, Protection IEC 61850 Process Bus - It is Real!AREVA, Winter 2008.

[14] M. Saha, J. Izykowski, M. Lukowicz, and E. Rosolowskiz, “Application of annmethods for instrument transformer correction in transmission line protection,”in Developments in Power System Protection, 2001, Seventh International Con-ference on (IEE), pp. 303–306, IET, 2001.

[15] C. Luiz Magalhaes and S. Paulo Marcio, “Ct saturation effects on performanceof digital overcurrent relays,” in Advanced Power System Automation and Pro-tection (APAP), 2011 International Conference on, vol. 1, pp. 637 –642, oct.2011.

[16] P. WuLue, Z. BingQuan, Q. YuTao, C. ShuiYao, and C. XiaoGang, “The researchand application on interfacing technology between electronic current transformerand relay protection,” in Advanced Power System Automation and Protection(APAP), 2011 International Conference on, vol. 1, pp. 422 –426, oct. 2011.

[17] A. Makky, H. Abo-Zied, F. Abdelbar, and P. Mutschler, “Design of the in-strument current transformer for high frequency high power applications,” inPower System Conference, 2008. MEPCON 2008. 12th International Middle-East, pp. 230–233, IEEE, 2008.

[18] P. Rafajdus, P. Bracinik, and J. Altus, “Transient analysis of voltage transformerin order to fault location in medium voltage network,” in Electrical and Elec-tronics Engineers in Israel (IEEEI), 2010 IEEE 26th Convention of, pp. 000741–000745, IEEE, 2010.

[19] P. Kirchesch, “Non-conventional instrument transformers in high voltage substa-tions,” e & i Elektrotechnik und Informationstechnik, vol. 119, no. 1, pp. 10–14,2002.

[20] M. Saitoh, T. Kimura, Y. Minami, N. Yamanaka, S. Maruyama, T. Nakajima,and M. Kosakada, “Electronic instrument transformers for integrated substationsystems,” in Transmission and Distribution Conference and Exhibition 2002:Asia Pacific. IEEE/PES, vol. 1, pp. 459–464, IEEE, 2002.

[21] D. F. Hoeschele, Analog to digital and digital to analog conversion techniques.Wiley, 1994.

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edu/~glover/applets/Sampling/Sampling.html.

[24] P. Allen and D. Holberg, “Cmos analog circuit design,” 2002.

[25] MathWorks, “Matlab/simulink simscape toolbox library,” 2012a.

[26] A. El-Koubysi, Y. Guo, and M. Lucas, “Testing the performance of delta-sigmaadcs,” in Instrumentation and Measurement Technology Conference, 1992. IMTC’92., 9th IEEE, pp. 514 –517, may 1992.

[27] I. Taha, M. Ahmadi, and W. Miller, “A sigma-delta modulator for digital hearinginstruments using 0.18µm cmos technology,” in System-on-Chip for Real-TimeApplications, 2004. Proceedings. 4th IEEE International Workshop on, pp. 233–236, IEEE, 2004.

[28] A. El-Koubysi, Y. Guo, and M. Lucas, “Testing the performance of delta-sigma adcs,” in Instrumentation and Measurement Technology Conference, 1992.IMTC’92., 9th IEEE, pp. 514–517, IEEE, 1992.

[29] W. Kester, “Mt-022: Adc architectures iii: Sigma-delta adc basics,” AnalogDevices, Rev. 0, pp. 02–06.

[30] N. Afzal and J. Wikner, “Study of modified noise-shaper architectures for over-sampled sigma-delta dacs,” in NORCHIP, 2010, pp. 1 –4, nov. 2010.

[31] “Ruggedswitch rs900 9-port, product description.” http://www.ruggedcom.

com/products/ruggedswitch/rs900/.

[32] Transformer Protection RET670, 1mrk504086-uen ed., June 2010.

[33] A. Nawikavatan, C. Thammart, T. Niyomsat, and M. Leelajindakrairerk, “Thecurrent transformer model with atp-emtp for transient response characteristicand its effect on differential relays performnce,” in Advances in Power SystemControl, Operation and Management (APSCOM 2009), 8th International Con-ference on, pp. 1–6, IET, 2009.

[34] F. Rekina and D. Ouahdi, “Analysis of the effects of magnetizing inrush currenton power transformer differential protection,” in Proceedings of the 6th confer-ence on Applications of electrical engineering, pp. 65–70, World Scientific andEngineering Academy and Society (WSEAS), 2007.

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1

Appendix A

Evaluation Report

A.1 Four Steps Phase Overcurrent Protection OC4PTOCwith 2nd Harmonics

The OC4PTOC without 2nd Harmonics is already discussed in Chapter ?? so onlythe principle of harmonic restrain blocking function is introduced in next section.

Principle of the harmonic restrain blocking function

Over excitations of a transformer can cause unnecessary operation of transformer dif-ferential relays. These over excitations can also be caused by the inrush currents orby sudden voltage rise. One condition might be the loss of a big load connected tothe secondary of transformer and the primary is still energized. When the primarywinding of a transformer is overexcited and driven into saturation as a result morepower appears to be flowing in than flowing out of the secondary winding. As over ex-citation phenomena is developed due to some internal dynamics caused in the powersystem it also generates some of the other harmonics with the fundamental [34]. Thissituation causes the relay towards wrong trip condition which is not acceptable atany cost. Now it is necessary to have a algorithm in the relay to clearly discriminatebetween the over excitation and the faulty states. Therefore the relay we are using inour testing facility is RET 670 which is equipped with second harmonic restrain func-tion. This function will not allow the trip due to inrush currents in the transformer.Power transformers can have a large inrush current, when being energized. This phe-nomenon is due to saturation of the transformer magnetic core during parts of theperiod. There is a risk that inrush current will reach levels above the pick-up currentof the phase over current protection. The inrush current has a large 2nd harmoniccontent. This can be used to avoid unwanted operation of the protection. Therefore,OC4PTOC have a possibility of 2nd harmonic restrain if the level of this harmoniccurrent reaches a value above a set percentage of the fundamental current.[35]

If a power transformer is energized there is a risk that the transformer core will

2

saturate during part of the period, resulting in an inrush transformer current. Thiswill give a declining residual current in the network, as the inrush current is deviatingbetween the phases. There is a risk that the phase over current function will givean unwanted trip. The inrush current has a relatively large ratio of 2nd harmoniccomponent. This component can be used to create a restrain signal to prevent thisunwanted function.[35]

To avoid unwanted trip due to inrush current in the transformer, 2nd harmoniccurrent is monitored. The 2nd harmonic current is compared to a pre-set restraincurrent level. If 2nd harmonic current exceeds the set level, the over current trip fromall steps will be blocked.

Testing setup

1. Simulink power system model which is used to generate testing data.

Figure A.1: The Simulink model of the testing

As shown in Figure A.1, the red rectangle marks the block which can inject 2nd

harmonic into the system. The fault is still the three-phase to ground fault.The time line of the simulation is shown in Figure A.2 below.

3

Figure A.2: The scheme of the testing

To test the 2nd harmonic restrain in OC4PTOC function, the 2nd harmonic isintroduced with fault during 20-25s. The OC4PTOC function should not tripduring that period. The OC4PTOC function will trip after 25s when the 2nd

harmonic is removed.

2. The application configuration is shown in Figure A.3 below.

4

Figure A.3: The application configuration in PCM 600

The mapping of the LED is listed in Table A.1.

Signals LEDs Signals LEDsGeneral Trip RED1 General Start YELLOW7

Trip for Step 1 RED2 Start signal from step1 phase L2 YELLOW8Trip for Step 2 RED3 Start signal from step2 phase L2 YELLOW9Trip for Step 3 RED4 Start signal from step3 phase L2 YELLOW10Trip for Step 4 RED5 Start signal from step4 phase L2 YELLOW11

Trip signalRED6

Block fromYELLOW12

from phase L3 2nd harmonic detection

Table A.1: The map of LED

3. Parameter configuration of OC4PTOC is listed in Table A.2.

5

GeneralParameters Values

Ibase 170A(RMS)StartPhSel 3 out of 3

2ndHarmStab 50%IB

Step 1 Step 2Parameters Values Parameters Values

I1> 150%IB I2> 250%IBt1> 5s t2> 2.5s

HarmRestrain1 On HarmRestrain2 OnStep 3 Step 4

I3> 500%IB I4> 1000%IBt3> 1s t4> 0s

HarmRestrain3 On HarmRestrain4 On

Table A.2: OC4PTOC settings for 2nd harmonic restrain

6

Results

(a) Normal condition during 0-15s (b) The 2nd harmonic is introduced at 15s

(c) The fault is injected after 20s but no trip(d) The 2nd harmonic is removed and Step 3is trip

Figure A.4: The results of OC4PTOC with 2nd harmonic

7

A.2 Two Windings Transformer Differential Protection (T2WPDIF)

Principle of Transformer Differential Protection

Differential relays are often used as main protection for all important elements of thepower system such as generators, transformers, buses, cables and overhead lines. Theprotected zone is clearly defined by the positioning of the main current transformersto which the differential relay is connected [36].

The principle of transformer differential operation is the comparison of valueof current on both primary and secondary sides of the transformer. Under normalconditions I1 and I2 are equal and opposite such that the resultant current throughthe relay is zero. If the difference between the two currents is greater than the setthreshold value the relay will detect the fault [36].

Figure A.5: Schematic of two windings transformer differential protection

Principle of T2WPDIF

As we are using ABB RET 670 differential protection relay for the transformer. RET670 has both two winding and three winding differential protection functions whichis shown in Figure A.6. In this evaluation work we used the two winding transformerprotection block. The brief introduction about T2WPDIF is provided here for betterunderstanding of the differential protection function of RET 670.

8

Figure A.6: The transformer differential protection provided in RET 670

A transformer differential protection compares the current flowing into thetransformer with the current leaving the transformer. A correct analysis of faultconditions by the differential protection must take into consideration changes due tovoltages, currents and phase angle changes caused by protected transformer. Tra-ditional transformer differential protection functions required auxiliary transformersfor correction of the phase shift and ratio. The numerical microprocessor based dif-ferential algorithm as implemented in the IED compensate for both the turns-ratioand the phase shift internally in the software. No auxiliary current transformers arenecessary. [35]

Testing Setup

1. Set up the offline testing model for differential protection

9

Figure A.7: The Simulink model for differential protection

As shown in Figure A.7 above, the power system comprises of a voltage source,two winding power transformer, a transmission line and a load. The transformerwinding ratio is 1:1. The model is simulated in offline mode for 30 seconds tocollect the measurements. The three phase short circuit fault is applied on theprimary side of the transformer from 16 to 25 seconds. The Merging Unit 1and Merging Unit 2 named ”KTH ICS SV1” and ”KTH ICS SV2” respectivelyare connected to the CT1 and CT2. After the simulation, the waveforms of theprimary and secondary sides are shown in Figure A.8 below.

10

Figure A.8: The waveforms of primary and secondary sides

Druing the normal operation, the current on both sides is around 500A atpeak. During the fault, the primary side current increases to approximately700A at peak and the secondary side current goes to almost zero. As shownin Figure A.7, the three-phase to ground fault happens in the primary side of

11

the transformer, all the current comes into the primary side will go to groundduring the fault. There will be no current on the secondary side during the fault.During the fault, the current difference between primary side and secondary sideis about 500A.

2. Set up the process bus communication interface. In this test, the process businterface should read measurement from both primary and secondary sides oftransformer and send both of them out.

Figure A.9: The Wireshark capture of sending SVs for two MUs

3. To subscribe two measurement data sets, set up the ”svID” for RET 670 to”KTH ICS SV1” and ”KTH ICS SV2”.

12

Parameter ValueMU1 4I 4U 921

SVId KTH ICS SV1MU2 4I 4U 921

SVId KTH ICS SV2

Table A.3: Parameter setting for MU

4. Connect the T2WPDIF function block in application configuration

Figure A.10: Application configuration for T2WPDIF

The LED mapping for T2WPDIF is listed below in Table A.4.

13

Signals LEDs Signals LEDsGeneral Trip RED1 2nd harmonic block RED5

Trip from restrained function RED2 5th harmonic block RED6Trip from

RED3Alarm from

YELLOW7unrestrained function sustained diff current

Common start RED4

Table A.4: The LED map for T2WPDIF

5. Parameter setting of the T2WPDIF

Parameters Values Parameters ValuesT2WPDIF:1

RatedVoltageW1 100kV ClockNumberW2 6[180deg]RatedVoltageW2 100kV ZSCurrSubtrW1 onRatedCurrentW1 350A(RMS) ZSCurrSubtrW2 onRatedCurrentW2 350A(RMS) TconfigForW1 no

ConnectionTypeW1 WYE(Y) TconfigForW2 noConnectionTypeW2 WYE(Y) LocationOLTC1 Not UsedSetting Group1

Operation On tAlarmDelay 10sSOFTMode Off IdMin 0.3 IBIDiffAlarm 0.1 IB IdUnre 10 IB

Table A.5: T2WPDIF settings

As shown in Table A.5, the rated current of winding 1 (W1) and winding 2 (W2)are set to the same value which indicates the ratio of the primary and secondaryside is 1. The ”IdMin” is the threshold current. When the current differencebetween primary and secondary sides exceeds ”IdMin”, the restrained protectionwill trip. In this case, the ”IdMin” is 0.3*IB=0.3*350=105A(RMS). When thecurrent difference exceeds ”IdUnre” which is set to 10*IB, the unrestrainedprotection will trip.

Results

Normal Setting

Firstly, the setting as listed in Table A.5 is written to RET 670. Since the three-phaseto ground fault happens in the primary side of the transformer, all the current comesinto the primary side will go to ground during the fault. There will be no currenton the secondary side during the fault. The current difference between primary and

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secondary sides is around 500A which already exceeds the threshold 105A. The RET670 trips normally and the results are shown in Figure A.11 below.

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(a) The normal readings from MU1 (b) Readings from MU1 during trip

(c) Readings from MU2 during trip (d) After fault readings from MU2

Figure A.11: The trips of T2WPDIF

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High Threshold Setting

In this setting, most of the parameter settings are the same as that in Table A.5. Theparameter changed are listed in Table A.6 below.

Parameters ValuesT2WPDIF:1RatedCurrentW1 1000A(RMS)RatedCurrentW2 1000A(RMS)Setting Group1

IdMin 0.6 IB

Table A.6: The changed parameters for T2WPDIF

It can be calculated, the threshold ”IdMin” is 0.6*1000=600A in this case.Since the current difference during the fault is around 500A in the simulation, theT2WPDIF will not trip. The results are shown in Figure A.12.

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(a) The normal readings from MU1(b) Readings from MU1 during fault but notrip

(c) Readings from MU2 during fault but notrip

(d) After fault readings from MU2

Figure A.12: The trips of T2WPDIF