Fully-Integrated Low Phase Noise BipolarDifferential VCOs at 2.9 and 4.4 GHz

Ali M. Niknejad Robert G. Meyer

Electronics Research LaboratoryUniversity of California at Berkeley

Joo Leong Tham1

Conexant Systems2

Newport Beach, CA

1 The author is now with Maxim Integrated Products2 Formerly known as Rockwell Semiconductor Systems

Outline of Presentation

• Project motivation

• Modeling on-chip inductors above 3 GHz

• Center-tapped inductors / differential Q

• Varactors above 3 GHz / MIM caps

• Circuit topology for low phase noise design

• Overall chip design & layout

• Summary of measured performance

3-10 GHz VCOs

• Realize high Q small footprint inductors > 3 GHz• fT ~ 25 GHz• Scaling area curtails substrate losses• MIM caps smaller > 3 GHz• Design low phase noise VCO w/high Q tank• Divide down to convenient frequency range

• VCO key building block in RF transceivers• Specs: Tuning Range, Power, and Phase Noise• Power and Phase Noise directly impacted by inductor Q• Fully integrated VCOs very difficult to implement• Main constraint: Lack of high Q inductor

Solution

Project Motivation

High-Frequency Effects Over Si Substratesegments couple magnetically

and electrically through oxide/airproximity effectsdue to presence of

nearby segment current crowding at edgedue to skin effect

radiation

substrate tap nearby causes lateral currents

substrate injection

substrate currents: ohmic, eddy, anddisplacement current

Summary of Loss Mechanisms

• Series ohmic loss due to conductor resistivity• Eddy current losses: Skin and proximity effects

• Electrically induced substrate currents• Magnetically induced substrate currents (bulk eddy currents)• Dielectric losses

• Radiation into air• Surface waves and radiation into the substrate

Conductor losses:

Substrate losses:

Radiation losses:

Bulk Eddy Current Losses• Are bulk eddy current losses significant?• Negligible if ρ > 1 Ω-cm (quasi-TEM) • Dominant if ρ < .01 Ω-cm (skin-effect mode)• Mechanism: Magnetic field penetrates bulk substrate and generates electric fields which produce currents• Eddy current mechanism different from electrical substrate losses• At h.f. the inductance drops significantly due to “image currents”

S piral Q uality F ac to r

4

5

6

7

8

9

10

1 4 7 10 (G Hz)

S p iral S e ries R e s is tance

0

3

6

1 4 7 10 (GHz)

.01 ohm-cm

.001 ohm-cm

.0001 ohm-cm

.00001 ohm-cm

ASITIC Software

• Analysis and Simulation of Inductors and Transformers for ICs

• A software tool for design and analysis of passive devices on Si

• ASITIC checked against meas. up to 14 GHz (conductive substrate)

http://www.eecs.berkeley.edu/~niknejad

-8

-4

0

4

8

12

0 2 4 6 8 10 12 14GHz

Lmeas

Lsim

Qmeas

Qsim

• Qmax > 5 in absence of eddy currents!

inductance

Q factor

• 1 nH: R= 75µ W= 5.2µ S=2.1µ N=2

• 10 nH: R=150µ W=12.3µ S=2.1µ N=7.5

• 1 nH at 10 GHz: L=1.0n R=1.6 Cs=28 Rs=500 Q = 11.4, 14.9, 20.3

• 10 nH at 2 GHz:L=8.7n R=5.3 Cs=258 Rs=350 Q = 4.4, 5.1, 10.2

Inductors at 2 GHz versus 10 GHz

0

5

10

15

20

25

0 2 4 6 8 10

Freq (GHz)

Inductor/Transformer Layout Geometry

circular spiral inductor symmetric center-tapped

transformer

balun

Center-Tapped Inductors

• Benefits:– Windings share area so better self-resonance– Don’t need to worry about parasitic coupling btwn two ind– Differential Q at h.f. depends heavily on substrate!

• Problems:– Each turn accumulates additional resistance due to vias– Forced to keep N < 4

center

Sin g le -E n ded & D iffe ren tia l Q -F ac to r

0

3

6

9

12

15

18

0 2 4 6 8 10G Hz

circular

square

single-ended

differentialR=100µw =12µs = 3µ

L=2nHC=200fFR=2Ω

Compact Circuit Model• Model includes two coupled windings

L L

rx

Rs Rs

Cs Cs

Cb Cb

k

rx

Rs2

Cs2

• 2.9 GHz circular design: Radius = 125µ, W=14.5µ, S=3µ, N=3, L2=23µ

L=.9nH, rx=1.2Ω, k=.5, Cb=70fFCx=28fF, Rx=380 Ω, Cx2=235fF, Rx2=310 Ω

• Peak Differential Q = 22 at 5 GHz, 14 at 3 GHz

Varactor Q Above 3 GHz

• Peak Q about 18 at 5.7 GHz (CMIM=0)

• This is comparable to inductor Q

0.5n

CMIM

0.5n

Q1 Q2

2V

1V

Lch

oke

Differential Circuit Topology

• Differential operation provides better immunity frompackage and substrate

• Differential Q higher (if substrate losses dominate)

• Differential dividers easier to build above 3 GHz

• Doubles area of actives but substantially reduces area ofpassives (due to mutual coupling & higher Q)

• De-couples circuit blocks on same substrate

Oscillator Design Equations

ωφ

d

d

• Steady-state conditions:

• RF large signal transconductance

• Phase delay of transconductor, transformer, and tankmust add to zero

• Phase delay in transconductor and transformer causesoscillator frequency to differ from peak

01)(

3210 =+−= φφφω

n

jZG TmL

)( 03

2

1

ωφ

φ

φ

jZ

en

vv

veGi

T

jox

xj

mLx

∠=

=

=

−

−

)( ωjZ T

1:n

xi

xv ov

Oscillator Design Procedure

• Find highest Q inductor (optimize )

• Split cap between transformer, load, and varactor to providesufficient tuning range

• Find smallest Ibias so that circuit oscillates with reasonableamplitude over process variation

• Optimize device size for phase noise

• Optimize n for best phase noise (noise match)

• Minimize noise from bias circuit

• Degen. bias current mirrors; degen. of osc. core does not help

• Minimize flicker noise up-conversion from bias

ωφ

d

d

VCO Layout: fT=25 GHz Bipolar Process

MIM caps

3 GHz Buffer

VCO Core

Inductor

Passive Coupler

1.5 GHz Buffer

Divide by 2

Feedback

Bypass Caps

VCO Core Circuit

current bias

Vbias

Q10

Q12

Q1-Q4

C1

Lt

Ct

D2D1

C4 C3

RB1

RB2

Q5

Q6

Q7

Q8

Q9

Q11

RE5 RE7RB3

RB4

RE10

RE11 RE12

Vcc

Vtune

C2

variable LC tank

negative R ckt

constantbase bias

VCO Core Layout

• 0.4µ×7µ×4 BJT• 3.5 - 4 mA bias current• 5 mA with bias current

pnp mirrors

varactors

differential quad

Capacitor Loads and Feedback

rsubRx

C

Cx1

Cx2

port1

port2

Bottom plate(shield)

Vo−

shield

Vo+

Vi+

Vi −

shield

top plate

bottom plate

Differential Load:Capacitive Feedback Network:

Down-Conversion, Mode Locking and Division

VCO

LO

Filter

])cos[( 11 nVCO tAv φωω +∆+=

)cos( 2nLOLO tBv φω +=

])cos[( 2121 nnVCO tCv φφωωω ++∆+±=

VCO LO

Injection locked LO or PLL

)cos( 1nVCO

LO tn

Bv φω +=

VCO FF divider

)cos( 1

n

tBv nVCO

LO

φω +=

Note: VCO inject more power than intrinsic noise of LO

Divider FF CircuitVcc

D

Clk ClkBar

DBar

QQbar

400Ω

200Ω

1kΩ

Bias

• Resistor CM improves headroom• 260µA total current (works up to 8 GHz with 200Ω load)

• 2.9 GHz Tank: 3nH, 500fF (varac), 450fF (MIM)

• 4.4 GHz Tank: 2nH, 500fF (varac), 130fF (MIM)

• Best predicted phase noise: -110 dBc/Hz at 100 kHzoffset (based on 6 GHz design!)

• Power dissipation: 10mW (Vcc=2.4, I~4mA)

• Tuning Range: 7%

• Core swing: ~1.7V differential

• Base swing: ~400mV

Design Summary and PredictedPerformance

VCO Measurement Setup

• Phase Noise Analyzer RDL model NTS-1000B• 4.4 GHz: Measured phase noise at ÷ 4 (internal FF divider)• 2.9 GHz: Down-convert to 1 GHz, assume phase noise of LO is

negligible

÷4VCO Buff Phase Noise Analyzer

4.4 GHz

π-matchnetwork

VCO Buff Phase Noise Analyzer

LO

2.9 GHz

π-matchnetwork

Phase Noise Measurement Results

-120

-110

-100

-90

-80

-70

-60

-50

-40

1 10 100 1000offset (kHz)

dBc/Hz

• 2.9 GHz: Measured phase noise of -95.2 dBc/Hz at 2.9 GHz Effective: -104 dBc/Hz @ 100 kHz offset (1 GHz carrier)• 4.4 GHz: Measured phase noise of -100.2 dBc/Hz at ÷ 4 Effective: -101 dBc/Hz @ 100 kHz offset (1 GHz carrier)

Summary and Conclusion

• Inductors above 3 GHz feasible and desirable

• Accurate and efficient analysis of inductors possible

• Differential operation beneficial over single-ended

• SpectreRF phase noise simulation used for optimization

• Measurement results close to expectations

Center Freq. 2.9 GHz VCO 4.4 GHzTechnology 25 GHz bipolar 25 GHz bipolarSubstrate 10 :-cm 10 :-cmCore current 3.5 mA 4 mATuning Range 250 MHz (10%) 260 MHz (6%)SSB Phase Noise@100 kHz offset

-95.2 dBc/Hz@ 2.9 GHz

-100.2 dBc/Hz@ 1.1 GHz

Acknowledgements

• Conexant Systems, Newport Beach, CA

• Frank Intveld (layout)

• Ron Hlavac (test board)

• U.S. Army Research Office

(Grant DAAG55-97-1-0340)