fully integrated switched-capacitor dc-dc … enables single, low-impedance global input ... Ł sc...
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Fully Integrated Switched-Capacitor DC-DC Conversion
Elad Alon
Berkeley Wireless Research Center
University of California, Berkeley
In collaboration with Hanh-Phuc Le, Seth Sanders
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Multi-Core Chips Are Here
IBM POWER7 Sun Rainbow Falls
Intel Westmere AMD Phenom
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Multi-Supply Chips?
Separate supply voltages
clearly desirable
Power management, compensate
variability, etc.
But, true multi-supply adoption
slow
Except for power gating
Why not use multiple external converters?
Shin, ISSCC 2010
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Supply Impedance and Split Planes
Supply impedance requirement extremely low 1V, 100A part 1mΩ
Split power planes bad for impedance Load and decap isolation
Reason I/O’s often placed on edges even with flip-chip4
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On-Die Voltage Conversion
Enables single, low-impedance global input
voltage
Key challenge: fully integrated DC-DC
Energy storage must be integrated on-die too5
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Switching Converter Options
Conversion ratio set by
duty cycle
Very popular for off-
chip converters
Inductor: Capacitor:
Conversion ratio set
by topology
Many perceived
disadvantages
Vx
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So Why Switched-Capacitor (SC)?
7
Key motivation:
integration with low cost
Dense, high-quality
capacitance widely available
(Development of on-die
magnetics can be leveraged
for SC converters too)
Integrated SC design can mitigate perceived
downsides
Component count no longer critical
What is achievable efficiency, power density?
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Previous Work
Work Breussegem, VLSI 09 Somasekhar, VLSI 09
Technology 130nm Bulk 32nm Bulk
Topology 2/1 step-up 2/1 step-up
Interleaved Phases 16 32
Converter Area (mm2) 2.25 6.678x10-3
Power density @ ηmax 0.002 W/mm2 1.123 W/mm2
Efficiency (ηmax) 82% 60%
Selected Previous Designs
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Vout
Vcap
Phase 1: Phase 2:
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Review: SC Basics
load
conv
I
C
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Phase 1: Phase 2:
Conversion ratio set by topology
Works in other direction too
Step-up: reverse Vi, Vo
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Switched Capacitor (SC) Basics
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SC Converter Loss Mechanisms
Intrinsic loss
Fundamental to converter
operation
Switch/parasitic loss
Non-idealities of the
capacitor(s) and switches
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SC Converter Loss with Digital Loads
Gate delay depends on Vdd:
Performance set by Vmin
SC converter effective output
resistance (for Vmin):
But, load also draws “extra” current when Vdd > Vmin
This power is wasted since it doesn’t improve performance
Ripple leads to extra loss:
2
,
loadReff
conv cap conv sw
IP
M C f=
2
,
,
1eff Csw
conv cap conv sw
RM C f
=
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Interleaving
2
int ,
11 load
Reff
conv cap conv sw
IP
N M C f
⎛ ⎞= +⎜ ⎟⎝ ⎠
Good news: interleaving
reduces ripple
But leaves Vmin unchanged
With Nint interleaved
converters:
Ripple minor for ~16+ way
interleaving
Vout
in
out
2
1
sw
1 1
1
2in
2 2
sw
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D. Ma, “Robust Multiple-Phase Switched-Capacitor DC-DC with Digital Interleaving Regulation
Scheme,” ISLPED 2006.
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Efficiency Optimization
Intrinsic loss
Reduced by ↑ C density
Reduced by ↑ fsw
Switch/parasitic loss
Reduced by ↑ switch fT
Increased by ↑ fsw
Efficiency optimization: choose fsw and Wsw to
balance loss terms
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Loss Terms Detail
2
loadReff
ccap conv sw
IP
M C f≈
Sw.-cap R:
2
Cbot bott bot out swP M C V f=
Bottom plate:
2
Csw sw sw sw swP W C V f=
Gate loss:
2
sw load onRsw
sw
M I RP
W=
Switch R:
15
0.1 1 100.3
0.5
0.7
0.9
Eff
icie
ncy
fsw
[GHz]
Optimal fsw
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Optimized Efficiency
Ignoring bottom-plate:2
3, , 2
3loss sw on swconv sw conv cap
load out L conv
P V R CM M
P V R C= ⋅
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Optimized Efficiency cont’d
Efficiency set by
conductance density
I.e., (Iload/Vout) / Conv. Area
(Equivalent to power
density for given Vout)
Typical numbers (1V)
Mobile device: ~0.1 S/mm2
Processor: ~1 S/mm2
Efficiency trades off with
converter area overhead…
17
2
32
3loss sw on swsw cap
load out L conv
P V R CM M
P V R C= ⋅
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Side Note
Explicit decoupling capacitance usually required
for supply integrity
Can largely replace decap with converter
In order to fit, converter needs to deliver ~10X higher
density than load18
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Impact of Bottom-Plate
With Cbot = kbotCconv:
19
2
22 2
caploss sw on swcap bott bot sw
load bott bot out L conv
MP V R CM M k M
P M k V R C
⎛ ⎞= + ⎜ ⎟
⎜ ⎟⎝ ⎠
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Impact of Bottom-Plate cont’d
Bottom plate sets min. loss:
E.g., 2:1 step-down,
1% bottom plate 10% loss
In the limit of low
power density:
Converter area does
not affect efficiency
Low parasitics more
important than cap.
density
2loss load cap bott botP P M M k≈
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Achievable Performance
45nm, 2:1 converter:
75% - 80% efficiency at
1W/mm2
Even in standard CMOS
Looks promising
Reminder: mobile device
~0.1W/mm2
But, only checked one
conversion ratio so far…
How to handle variable voltages?
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SC “Standard Cell” Converter
Integrated capacitors/switches
easily partitioned
“Standard cell” configuration
sets conversion ratio
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Efficiency vs. Conversion Ratio
Change topology,
Wsw, and fsw
Rout ~ 1/(Cfsw)
Just like linear
regulator
Probably need only
~4-5 topologies
Clustered around 2:1
Watch out for switch drivers
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0.4 0.6 0.8 1 1.20.5
0.55
0.6
0.65
0.7
0.75
0.8
Eff
icie
ncy
Vout [V]
n = 2/3n = 1/2n = 1/3
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Prototype
Implemented in 32nm SOI
test-chip (w/AMD)
MOS flying capacitors,
32-way interleaved
Supports 0.6V ~ 1.2V from
2V input
24
Die photo
H.-P. Le, S. Sanders, and E. Alon, “Design Techniques for Fully Integrated Switched-Capacitor
DC-DC Converters,” JSSC Sept 2011.
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Measured Efficiency vs. Power Density
Measured with n = 1/2 (Vi = 2V, Vo ≈ 0.88V)
Matches analysis: ~80% efficiency @ 0.86 W/mm225
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Measured Efficiency vs. Topologies
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All three topologies
functional (3:1 efficiency limited by
breakdown)
Efficiency still >70% for
0.75V – 1.15V Vo with
2V Vin
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Enables converter to use entire area over core
Mitigates efficiency vs. power density tradeoff
Converter die can use older, lower-cost
technology
While still meeting efficiency & density requirements
Core
Sw. Cap
Core
Sw. Cap
Core
Sw. Cap
Core
Sw. Cap
27
Looking Forward: Leveraging 2.5/3D Integration
Conv. SoC
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Dense capacitors already exist for DRAM/eDRAM
IBM eDRAM 2:1 converter*: 90% efficiency @ 2.3A/mm2
Opportunity to further leverage stacked DRAM
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Looking Forward: Dense Capacitors
Barth, ISSCC 2010
*L. Chang et al., “A Fully Integrated Switched-Capacitor 2:1 Voltage Converter with Regulation Capability and 90% Efficiency at 2.3A/mm2,” IEEE Symposium on VLSI Circuits, Jun. 2010
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Clear need for fully-integrated DC-DC converters
Multiple off-chip supplies costly, degrade impedance
Switched-capacitor converters in standard
CMOS can achieve:
In 2:1: ~80% efficiency @ 0.86 W/mm2
>70% efficiency for Vo from ~0.75V to 1.15V with
Vi = 2V
Low-cost technologies to enable even higher
densities, efficiencies already exist
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Summary
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BWRC students, faculty, and staff
Focus Center Research Program
IFC and C2S2
AMD
Sam Naffziger, Vishvesh Sathe, Rich DeSantis
IBM Faculty Award
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Acknowledgments