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IEEE JOURNAL OF PHOTOVOLTAICS 1

Fully Ion-Implanted and Screen-Printed 20.2%Efficient Front Junction Silicon Cells

on 239 cm2 n-Type CZ SubstrateYuguo Tao, Young-Woo Ok, Francesco Zimbardi, Ajay D. Upadhyaya, Member, IEEE, Jiun-Hong Lai,

Steven Ning, Vijaykumar D. Upadhyaya, and Ajeet Rohatgi, Fellow, IEEE

Abstract—In this study, we present fully ion-implanted screen-printed high-efficiency 239 cm2 n-type silicon solar cells thatare fabricated on pseudosquare Czochralski wafers. Implantedboron emitter and phosphorous back-surface field (BSF) were op-timized to produce n-type front junction cells with front and backSiO2 /SiNx surface passivation and rear point contacts. Averageefficiency of 19.8%, with the best efficiency of 20.2%, certified byFraunhofer ISE, Freiburg, Germany, was achieved. In addition,the planarized rear side gave better surface passivation, in combi-nation with optimized BSF profile, raised the average efficiency to∼20% for the fully implanted and screen-printed n-type passivatedemitter, rear totally diffused cells.

Index Terms—Back-surface field (BSF), ion implantation, n-typewafer, planarization, screen printed.

I. INTRODUCTION

ION implantation has become an active area of investigationin photovoltaics (PV) because it can produce advanced high-

efficiency cell structures with fewer processing steps [1]–[4].It is also well known that n-type silicon (Si) provides severaladvantages over p-type, including better tolerance to commonimpurities (e.g., Fe), high bulk lifetime, and no light-induceddegradation due to boron–oxygen complex [5], [6]. Benick et al.,demonstrated high quality of boron and phosphorus implanta-tion by fabricating 22.3% efficient small-area (4 cm2) n-typepassivated emitter, rear totally-diffused (PERT) cell with Vocof 684 mV. It is worth mentioning that this fully implantedhigh-efficiency cell on float zone wafer had Al2O3 /SiNx pas-sivated boron-doped emitter, thermally grown SiO2 passivatedphosphorous-doped back-surface field (BSF), and photolitho-graphically defined front contacts (evaporated Ti/Pd/Ag) [7].The Al2O3 films synthesized by plasma-assisted atomic layer

Manuscript received June 10, 2013; revised July 10, 2013 and August 13,2013; accepted September 3, 2013.

Y. Tao, Y.-W. Ok, F. Zimbardi, A. D. Upadhyaya, J.-H. Lai, S. Ning, andV. D. Upadhyaya are with the Georgia Institute of Technology, Atlanta,GA 30332 USA (e-mail: [email protected]; [email protected];[email protected]; [email protected]; [email protected]; [email protected]).

A. Rohatgi is with Suniva Inc., Norcross, GA 30092 USA and alsowith the Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JPHOTOV.2013.2281106

Fig. 1. Schematic of the front junction n-type Si solar cell structure.

deposition (ALD) have a high fixed negative charge density.Therefore, it provides excellent field-induced passivation onthe boron-doped p+ -emitter with doping concentrations around1019 cm−3 [8]–[11]. On the other hand, it has also been re-ported that the high quality oxide with low interface statesdensity can be formed during implantation anneal at no ad-ditional cost [12]. Furthermore, an emitter saturation currentdensity (Joe) of ∼80 fA/cm2 was reported on highly boron-doped emitter passivated with SiO2 /SiNx stack after firing ofscreen-printed contacts at high temperature [13]. Therefore, inthis study, ion implantation and low-cost screen-printing tech-nologies are combined with thermally grown SiO2 passivationon both emitter and BSF. In a previous work, we reported 19.6%efficient n-type bifacial cells on large area (239 cm2) Czochral-ski (Cz) substrate using ion implantation and screen printing,and pointed out that ∼8% metal coverage on the rear side wasin part responsible for lower efficiency [13]. In this study, wepresent the development of higher efficiency n-type cells on239 cm2 Cz Si with less metal coverage (point contacts) on theback and the two different rear surface morphologies: texturedand planar.

II. EXPERIMENTS

Fig. 1 shows the structure of our front junction n-type cell thatis fabricated on 1∼6 Ωcm 200-μm thick wafers. The fabrica-tion process involves saw damage removal in heated potassiumhydroxide (KOH) solution followed by alkaline texturing ofboth sides of the starting wafers. The boron and phosphorusimplantations were performed on a production-line implanterat Suniva Inc., Norcross, GA, USA. Hermle et al. [3] pointedout that the crystal defects created during implantation are dif-ferent for different implanted ions, for example, amorphized

2156-3381 © 2013 IEEE


2 IEEE JOURNAL OF PHOTOVOLTAICS

Fig. 2. Cell efficiency distribution of 75 cells (textured rear) in five differentexperiments with wafers supplied by three vendors.

surface is formed for heavy ion like phosphorus, and point de-fects (self-interstitials and vacancies) without amorphization arecreated for lighter element like boron. Therefore, two differentanneals were performed in this study—the first right after theboron implantation and the second after the phosphorous im-plantation. To reduce surface recombination on boron-dopedemitter and obtain low Joe , a chemical etching treatment wasperformed after the first anneal [13], [14], while the SiO2 pas-sivation layer on both sides was grown as a byproduct of thesecond anneal [12], [13]. The appropriate implantation, anneal-ing, and chemical etching treatment were applied to obtain sheetresistivity of ∼80 Ω/� for the boron emitter and ∼60 Ω/� forthe phosphorus BSF. The resulting thickness of thermally grownoxide was ∼10 nm on the front and ∼20 nm on the rear side.Then, the SiNx films with appropriate thickness were depositedby the plasma-enhanced chemical vapor deposition (PECVD)tool on the front and rear surfaces. Prior to metallization, theimplied open-circuited voltage (implied Voc) of 660∼665 mVwere achieved after a simulated cofiring cycle. Implied Voc wasmeasured at a light intensity of one sun using the quasisteady-state photoconductance (QSSPC) method that is developed bySinton Consulting [15].

In order to reduce the metal shading while maintaining goodseries resistance, the coverage of screen-printed front Ag/Al gridwas limited to ∼8%. Ag dots were screen printed on the rearwith diameter of 110∼150 μm and pitch of ∼500 μm, whichis equivalent to 4∼5% metal coverage. Next, the cofiring wasoptimized in an industrial-style belt furnace to get good frontand back ohmic contacts. Finally, a low temperature metal pastewas screen printed and dried on the entire rear side to connectthe Ag dots. Note that in term of the major material of this lowtemperature metal paste—Ag, it is more expensive than the Alpaste for the standard Al-BSF cell.

III. RESULTS

A. Cells With Textured Back Surface

The resulting efficiency distribution of double side textured75 cells is shown in Fig. 2. Note that these cells were fabricatedin five different experiments using wafers from three different

Fig. 3. Fraunhofer-certified full area (239.5 cm2 ) 20.2% efficient n-type cell(textured rear surface).

vendors. The average cell efficiency of 19.7% was obtainedwith a maximum of 20.0% (see Fig. 2). Reasonably narrowspread in the cell efficiency over a wide range of bulk resistivity(1∼6 Ωcm) from different wafer suppliers suggests excellentstability of the established process and its capability of fab-ricating high-efficiency solar cells. However, further processrefinement is necessary to achieve economic viability, such asreplacing the two separated annealing steps by a single coan-nealing, and exploring an Al paste instead of the expensive metalpaste for the entire rear side, etc.

Fig. 3 shows the I–V data of the best cell achieved on ∼3 Ωcmwafer, with Voc of 649 mV, Jsc of 39.3 mA/cm2 , FF of 79.1%,and cell efficiency of 20.2% (certified by Fraunhofer ISE CellCalibration Lab). These results demonstrate the high quality ofboron and phosphorus impantation and in situ oxide passivation.

B. Cells With Planar Rear Surface

To obtain planar rear surface, the double side textured waferswith bulk resistivity of ∼2 Ωcm (after annealing) were coatedwith SiNx as a barrier layer on the front side, and then, etched inheated KOH solution to planarize the back. After planarization,the wafer thickness was reached to about 175 μm. To extractthe saturation current density of phosphorus implanted BSF(Job ′) on planar surface, four groups of wafers (five samplesper group) with symmetric n+nn+ structure were implantedwith four different doses (“D,” “E,” “F,” and “G”) but annealedunder the same condition. Group “A” with textured rear surfacewas also included for comparison. Wafers for Job ′ study hadhigh base resistivity (5∼6 Ωcm) and high bulk lifetime (>1 ms)to attain high level injection. The measured Job ′ in Fig. 4 showsthat all planar back samples have lower Job ′ than the texturedback samples, with the lowest Job ′ value of 38 fA/cm2 for groupG. To account for the difference in surface morphology and areaof the textured and planar surfaces, the implanted phosphorusdose in group A was increased by a factor of 1.8 compared withthe counterpart group E.

Fig. 4 shows that group A has about 20 fA/cm2 higher Job ′ rel-ative to group E. This suggests that oxide passivation quality issuperior on a planar rear surface. In addition, model calculations


TAO et al.: FULLY ION-IMPLANTED AND SCREEN-PRINTED 20.2% EFFICIENT FRONT JUNCTION Si CELLS ON 239 cm2 n-TYPE CZ SUBSTRATE 3

Fig. 4. Average saturation current density from the BSF (Job ′ ) as a functionof implanted BSF profiles.

Fig. 5. Phosphorus concentration profiles obtained via Sentaurus simula-tion that is calibrated by the measurement results from the electrochemicalcapacitance–voltage (ECV) technique.

in Fig. 5 shows that lower dose on planar surface produces shal-lower BSF for the same annealing conditions.

Fig. 6 shows the cell data for groups A–G (6∼10 cellsper group). Consistent with the decreasing Job ′ trend shownin Fig. 4, open-circuit voltage (Voc) gradually increases fromgroup A to F . However, it drops for group G, in spite of lowerJob ′ prior to metallization. This is because group G has veryshallow or transparent BSF. Therefore, it is more adversely af-fected by metal recombination, which negates the positive effectof reduced heavy doping in the BSF.

The measured reflectance in Fig. 7 shows that all the planarback cells (groups D,E, F , and G) have higher escape or back-surface reflectance than the textured back cells (group A) in thelong wavelength range of 980∼1200 nm. However, the averageshort-circuit current density (Jsc) are similar for all the BSFconditions, about 38.6 mA/cm2 . Fig. 7 also indicates that theBSF with lower implanted phosphorus dose has slightly higherescape reflection possibly due to reduced free carrier absorptionin the back.

Fig. 6. Open-circuit voltage (Vo c ) and short-circuit current density (Jsc ) asa function of implanted BSF profiles.

Fig. 7. Reflectance of front junction Si cells as a function of implanted BSFprofiles.

Fig. 8. Cell efficiency (η) and fill factor (FF) as a function of different BSFprofiles.

Fig. 8 shows that the cells with lower phosphorus dose BSFgave lower fill factor (FF), which is attributed to higher se-ries resistance (Rs) as well as higher n-factor (see Fig. 9).The measured sheet resistivity gradually increased from ∼50 to∼90 Ω/� as the phosphorus-doped BSF profile on the planar



Fig. 9. Series resistance (Rs ) and n-factor the rear side of cells as a functionof different BSF profiles.

TABLE IAVERAGE LIGHT I–V PARAMETERS OF THE ∼5 Ωcm n-TYPE CELLS WITH

TEXTURED BACK (GROUP A) AND PLANAR BACK SURFACE (GROUP E)MEASURED AT AM1.5G, 100 mW/cm2 , 25 ◦C (MEASURED IN-HOUSE)

Fig. 10. Comparison of internal quantum efficiency (IQE) and reflectance ofthe cell with efficiency of 20.0% for planar rear surface from group E and19.8% for textured rear surface from group A.

surface was changed from D to G. This is the result of increas-ing Rs . High n-factor (>1.1) for the group G is most likely dueto shallow BSF and possibly metal spiking. Since the Jsc has asmall variation for all the dose conditions, Fig. 8 reveals that theoptimal phosphorus dose is mainly determined by the tradeoffbetween Job ′ (hence, Voc) and FF.

Table I and Fig. 10 summarize the cell parameters and internalquantum efficiency (IQE) of textured back group A and corre-spondent planar back group E cells. It is clear that planarizationincreases the long wavelength response and Voc due to improved

passivation and back-surface reflectance. This is supported byhigher long wavelength response (passivation) and higher es-cape reflectance (BSR) in Fig. 10. Consequently, enhancementof ∼4 mV in Voc and ∼0.1 mA/cm2 in Jsc was achieved, incombination with ∼0.3% increase in absolute FF due to betterohmic contacts. As a result, rear planarization resulted in∼0.2%increase in absolute average efficiency. Average efficiency forplanar devices increased from 19.8% to 20% with a maximumof ≥20.2% in this experiment. Nevertheless, to the authors’knowledge, it is still not clear whether the 0.2% increase in thecell efficiency from rear planarization overcomes the cost of theadditional processing required to obtain planar rear surface.

IV. SUMMARY

We have fabricated average 19.8% efficient fully ion-implanted and screen-printed front junction n-type cells on239 cm2 Cz substrate with textured surface and point contacts onthe rear side. By applying planar rear surface and an optimal im-planted phosphorus BSF profile, the average cell efficiency wasincreased to ∼20% with a maximum of ≥20.2% for the largearea fully implanted and screen-printed n-type PERT cells.

ACKNOWLEDGMENT

The authors would like to thank Dr. A. Gupta and Dr. A.Payne of Suniva Inc. for support in ion implantation and allother group members at UCEP/GIT for their invaluable supportand discussion.

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[11] P. Saint-Cast, A. Richter, E. Billot, M. Hofmann, J. Benick, J. Rentsch,R. Preu, and S. W. Glunz, “Very low surface recombination velocity ofboron doped emitter passivated with plasma-enhanced chemical-vapor-deposited AlOx layers,” Thin Solid Films, vol. 522, pp. 336–339, 2012.

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Yuguo Tao received both the B.S. degree in mechan-ical engineering and the M.S. degree in power ma-chinery engineering from Tianjin University, Tianjin,China, in 2002 and 2005, respectively, and the Ph.D.degree in photovoltaic engineering from the Univer-sity of New South Wales (UNSW), Sydney, Australia,in 2012.

He was a Research Assistant from 2003 to2005 with FAI Electronics Ltd., Hangzhou, China—founded by his supervisors. Upon graduating fromthe graduate school, he served as a Research Engi-

neer with Robert Bosch GmbH, Wuxi, China. He joined SIEMENS, Shanghai,China, in 2006. Having strong interest in the renewable energy world, in 2008,he started to pursue new study in solar energy. Since graduating from UNSW,he has been a Research Engineer with the University Center of Excellence forPhotovoltaics, Georgia Institute of Technology, Atlanta, GA, USA. His currentresearch interests include the design and development of ion-implanted andscreen-printed high-efficiency and cost-effective Si solar cells on commerciallyavailable large-area wafers.

Young-Woo Ok received the B.S. degree from theSchool of Materials Science and Engineering, KoreaUniversity, Seoul, Korea, in 1999 and the M.S. andPh.D. degrees from the Gwangju Institute of Scienceand Technology, Gwangju, Korea, in 2001 and 2005,respectively.

After receiving the Ph.D. degree, he workedwith Solar Cell Laboratory, Korea University, asa Postdoctoral Fellow for two years and thenwith the Semiconductors and Solar Cells Labo-ratory, Australian National University, Canberra,

Australia, as a Visiting Researcher for one year. He has been working withthe University Center of Excellence, Georgia Institute of Technology, Atlanta,GA, USA, as a Research Engineer since 2009. He has published more than50 papers in the research areas of semiconductor and photovoltaic Si devices.His research interests include the fabrication and characterization of Si-basedphotovoltaic devices. His current research interests include the development ofnew structure and passivation to realized low-cost and high-efficiency n-type Sisolar cells.

Francesco Zimbardi received the Bachelor of Sci-ence degree in electrical engineering from the Geor-gia Institute of Technology, (Georgia Tech) Atlanta,GA, USA, in 2009.

While in college, he worked for two years withthe National Electric Energy Testing Research andApplication Center, Forest Park, GA, USA, testingnew power transmission and distribution componentsqualifying them to industry standards. In 2008, he be-gan working with the University Center of Excellencefor Photovoltaics as a Student Researcher, becoming

a Research Engineer upon graduating from Georgia Tech. He is involved instudent projects and currently serves as a Faculty Advisor with the Solar JacketsRacing Team: a group which he helped found while in college.

Ajay D. Upadhyaya (M’06) was born on August10, 1974, in India. He received the B.Sc. degree inelectrical engineering from the Georgia Institute ofTechnology (Georgia Tech), Atlanta, GA, USA, in2001 and the M.B.A. degree in marketing from Mer-cer University, Macon, GA, USA, in 2006.

He has been with Georgia Tech since 2001 inmany capacities. He started as a Research Engineer Iand was promoted to Research Engineer II during hiscareer. He has been serving as the Operation Man-ager with research duties for the University Center of

Excellence for Photovoltaics with Georgia Tech. He is the author or co-authorof more than 40 publications in journals and conference proceedings. His cur-rent research interests include making monocrystalline silicon solar cells moreefficient and cost effective through technology innovation. His past researchinterests were the enhancement of lower quality silicon materials such as mul-ticrystalline, ribbon, and edge-defined film-fed growth silicon to improve thequality and performance of solar cells through existing processing steps.

Mr. Upadhyaya is on the Board of Directors of the Energy and EnvironmentExpo. He received the Best Researcher Award in 2004 from Georgia Tech.

Jiun-Hong Lai received the B.S. degree in electricalengineering from Chung-Hua University, Hsinchu,Taiwan, in 1996; the M.S. degree in electrical andcontrol engineering from National Chiao-Tung Uni-versity, Hsinchu, in 1997; and another M.S. de-gree from the Georgia Institute of Technology,Atlanta, GA, USA, in 2010, where he is currentlyworking toward the Ph.D. degree under the guidanceof Dr. A. Rohatgi with the University Center of Ex-cellence for Photovoltaics.

Upon graduating early from graduate school, hewas a Research Assistant with the Department of Bio-Industrial MechatronicsEngineering, National Taiwan University, Taipei, Taiwan. As a Principle Engi-neer with Taiwan Semiconductor Manufacturing Company from 2000 to 2007,he was responsible for developing control systems for gate formation of semi-conductor devices. He has been awarded two patents in this field of advancedprocess control. His research focuses on design and fabrication of commercialgrade low-cost high efficiency silicon solar cells.

Mr. Lai received the Best Student Paper Award at the 37th IEEE Photo-voltaics Specialists Conference, Seattle, WA, USA, in 2011.



Steven Ning received the B.S. degree in physics fromHarvey Mudd College, Claremont, CA, USA, and theM.S. degree in electrical and computer engineeringfrom the Georgia Institute of Technology (GeorgiaTech), Atlanta, GA, USA, where his research withthe University Center of Excellence for PhotovoltaicResearch and Education focused on fabrication ofnovel n-type silicon solar cell structures, as well asTechnology Computer-Aided Design simulation offabrication processes and device physics.

He served as the Project Manager for the GeorgiaTech Solar Jackets solar car racing team. He is currently working as a DesignEngineer for Space Exploration Technologies, Hawthorne, CA, USA.

Vijaykumar D. Upadhyaya received the B.Sc. de-gree in electrical and computer engineering from theGeorgia Institute of Technology (Georgia Tech), At-lanta, GA, USA, in 2003.

He is a currently a Research Engineer. He wasalso a Co-op student during his studies and workedfor SoC Solutions, Tech Center, and the University ofExcellence in Photovoltaics Research and Education(UCEP), Georgia Tech. After graduation, he becamea Full-Time Research Engineer with UCEP, wherehe contributed to the development, fabrication, and

characterization of low-cost, high-efficiency, Czochralski, and float-zone sil-icon solar cells. He has co-authored various technical papers, journals, andproceedings. He has also worked on emitter wrap-through/interdigitated back-contacts solar cell research that helped J. Gee of Advent Solar, Inc. He is alsoresponsible for sponsored research with various paste-manufacturing companieslike Ferro, Hereaus, Dupont, BASF, and Cermet, and he is currently workingwith companies like Suniva, Norcross, GA, USA, in advanced solar cell struc-tures and advance processing using screen-printed technology.

Ajeet Rohatgi (F’08) received the B.S. degree inelectrical engineering from the India Institute ofTechnology, Kanpur, India, in 1971, the M.S. degreein materials engineering from the Virginia Polytech-nic Institute and State University, Blacksburg, VA,USA, in 1973, and the Ph.D. degree in metallurgyand material science from Lehigh University, Beth-lehem, PA, USA, in 1977.

He is currently a Regent’s Professor and a GRAEminent Scholar with the School of Electrical En-gineering, Georgia Institute of Technology (Georgia

Tech), Atlanta, GA, USA. He is the Founding Director of the University Centerof Excellence for Photovoltaic Research and Education, Georgia Tech, and theFounder and CTO of Suniva, Inc., Norcross, GA, USA. Before joining the Elec-trical Engineering Faculty with Georgia Tech, in 1985, he was a WestinghouseFellow with the Research and Development Center, Pittsburgh, PA, USA. Hehas published more than 400 technical papers in this field and has received 16patents. His current research interests include the design and development oflow-cost and high-efficiency commercial ready Si solar cells and the economicsof photovoltaic systems.

Dr. Rohatgi received the Westinghouse Engineering Achievement Award in1985, the Georgia Tech Distinguished Professor Award in 1996, the IEEE PVSCWilliam Cherry Award in 2003, the NREL/DOE Rappaport Award in 2003, andthe EPA Climate Protection Award in 2009, and he was named a champion ofPV in 2011 by Renewable World Energy Magazine.

fully ion-implanted and screen-printed 20.2% efficient front junction silicon cells on 239 cm $^{\bf...

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