fullydigitalhysteretic_sep2009

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Fully Digital Hysteretic Modulator for

DC-DC Switching Converters

Luca Corradini, Aleksandar Bjeletić, Regan Zane, Dragan Maksimović Colorado Power Electronics Center

ECEE DepartmentUniversity of Colorado at Boulder

corradin, bjeletic, zane, [email protected]

Abstract – This paper presents an alternative modulation

approach for digitally controlled DC-DC switching converters,

which exploits the natural jittering activity of a digital hysteretic

feedback loop in order to provide an effective increase in

resolution. The proposed structure replaces conventional high-

resolution digital pulse-width modulators (DPWM) or sigma-

delta based ( -DPWM) solutions with a single, fully-digital

block featuring reduced complexity, high resolution, and

improved noise performance and small-signal dynamic

characteristics, enabling the design of accurate, high-bandwidth

digital feedback loops with minimum hardware resources. A

stochastic modeling approach is developed for the proposed

structure, which allows the derivation of a simple and effective

switching frequency control criterion. Analysis, simulation and

experimental tests are shown to validate the properties of the

proposed digital hysteretic modulator.

Index Terms – digital control, hysteretic modulator, sigma-

delta digital pulse width modulator.

I. I NTRODUCTION.

As digital control techniques for DC-DC switchingconverters are gaining popularity due to advantages such as

programmability, robustness and options for more advanced

controls [1]-[3], there are still challenges in digital design that

are not present in analog designs. An important issue is related

to the timing resolution of the digital modulator, i.e. the

portion of the digital controller that modulates the command

signal (e.g. duty cycle command d [k ]) calculated by the

compensator into a logic on/off switching signal S suitable for

driving the power stage at a desired switching frequency f s. It

is well known how time quantization effects induced by the

digital nature of the modulator limit the set of duty cycles that

can be represented, making the implementation of high-

resolution digital pulse-width modulators a nontrivial task.The block diagram in Fig. 1(a) illustrates a standard digital

voltage-mode control for a buck converter. Given the duty

cycle command signal d [k ] with a resolution of n bits, the

problem consists of implementing a modulator capable of

transmitting that resolution to the power converter, i.e. capable

of generating the signal S without resolution loss. Proposed

approaches and designs range from the simple counter-based

DPWM structure, in which the clock frequency f clk = 2n f s is an

exponential function of the desired resolution n, to hybrid

structures which limit the required clock frequency at the

expense of an increased hardware complexity by combining a

low-resolution, counter-based module with a fine-resolution

delay-line [4]. Sigma-delta digital pulse-width modulation

(ΣΔ-DPWM) is another well known technique, successfully

adapted from the field of digital signal processing, employed

to maintain a high effective resolution without the need for high clock frequencies [5], [6]. In this case the concept

consists of increasing the effective resolution by dithering the

input command to a low-resolution DPWM using a ΣΔ loop.

This paper proposes an alternative modulation strategy

based on the digital hysteretic feedback loop illustrated in

Fig. 1(b). A single, low-complexity digital block replaces the

typical ΣΔ-DPWM arrangement while still achieving a

significant increase in the effective resolution similar to multi-

bit ΣΔ structures.

V ref

Digital

Compensator +

-

A/D

f smp

C

L

V in Buck Converter

vo(t )

S Digital

Modulator

f clk

d [k ]

n

(a)

d

z -1

+

-

f clk

S 1

1

1−− z

Proposed

Hysteretic Modulator

r

0

1

-β/2 +β/20

S

r

n

d

z -1

+

-

f clk

S 1

1

1−− z

Proposed


r

0

1

-β/2 +β/20

S

r

0

1

-β/2 +β/20

S

r

n

(b) (c)

Fig. 1. Digitally-controlled DC-DC buck converter (a), proposed

hysteretic modulator (b), and transfer characteristic of the hysteretic

comparator (c).

3312978-1-4244-2893-9/09/$25.00 ©2009 IEEE

Authorized licensed use limited to: UNIVERSITY OF COLORADO. Downloaded on December 25, 2009 at 21:50 from IEEE Xplore. Restrictions apply.



Furthermore, the modulator has better noise performance in

terms of generated low-frequency tones compared to a

conventional first-order ΣΔ structure having the same core

DPWM resolution. Finally unlike ΣΔ-DPWM, the proposed

digital hysteretic modulator can be operated in a multi-sample

fashion [7], [8] with reduced small-signal delay [9], thus

enabling high-bandwidth closed-loop voltage regulation.

This paper discusses the structure of the hysteretic

modulator along with its operation in open-loop and closed-

loop converter configurations. Section II describes the

principle of operation of the proposed hysteretic modulator; a

stochastic analysis is presented that predicts the switching rate

of the modulator as a function of the hysteresis window β and

of the operating duty ratio D. A simple and effective criterion

to control the modulator switching rate is derived from the

proposed model and experimentally verified. Section III

discusses the effective increase in resolution and the noise

performance of the modulator, comparing the hysteretic

structure to a conventional ΣΔ-DPWM arrangement through

both simulation and experimental tests. Section IV addresses

the converter closed-loop operation using a complete digitalcontroller with the proposed modulator, experimentally

verifying the advantages of the multi-sampled operation.

II. DIGITAL HYSTERETIC MODULATOR

A. Description of Operation

Fig. 1(b) illustrates the block diagram of the proposed

digital hysteretic modulator. It consists of an entirely digital

system clocked at a fixed clock frequency f clk , typically in the

range of tens of megahertz. A digital integrator clocked at f clk

processes the error between the n-bit input duty-cycle

command d [k ] and the binary output S . The output r [nT clk ] of

the integrator is processed by a hysteretic digital comparator,whose transfer characteristic is sketched in Fig. 1(c). The

variable β is a programmable digital word that sets the

hysteresis window and facilitates a controllable switching rate.

Operation of the hysteretic modulator can be described with

reference to Fig. 2, assuming a constant input duty cycle

command d = D and with the output state initially at S = 0.

Given a constant input signal and the output state at S = 0,

the digital accumulator integrates the difference D – 0 = D,

therefore producing an increasing digital ramp. The output bit

remains at S = 0 as long as r < +β/2. As soon as the ramp

exceeds the positive threshold +β/2, the hysteretic comparator

switches to S = 1. This event marks the end of the turn-on

interval and the beginning of the turn-off interval.After the output has switched to S = 1 the digital

accumulator integrates the negative error D – 1, thus

generating a decreasing ramp. The switch signal remains at

S = 1 as long as r > −β/2. When r < −β/2 the switch signal

changes back to S = 0 and a new switching cycle begins.

It is important to realize that the switch turn-on and turn-off

events are synchronous with the clock frequency f clk due to the

0 0.5 1 1.5 2 2.5 3 3.5-8

-6

-4

-2

0

2

4

6

8

0 0.5 1 1.5 2 2.5 3 3.5-0.25

0

0.25

0.5

0.75

1

1.25

r [nT clk ]

S

Time (μs)

±β/2

⟨t OFF ⟩

⟨t ON ⟩ t ON and t OFF jittering

Switching Interval ⟨T s⟩

Fig. 2. Steady-state waveforms: of r and β (top) and switching signal S

(bottom).

entirely digital nature of the system. Therefore, the on-state

and off-state intervals t ON and t OFF are always integer

multiples of the clock period :

⎩⎨⎧

⋅=

⋅=

clk OFF OFF

clk ON ON

T nt

T nt , (1)

Similar to ΣΔ loops, the presence of the digital integrator

within the modulator digital loop forces the output average

value to be equal to D:

Dnn

nS

OFF ON

ON =+

= . (2)

Given (1), it is clear that (2) may not be true when averaged

over a single switching period T s. In this case, both nON andnOFF will vary cycle-by-cycle, and the steady-state operation

of the modulator will exhibit jittering of both the turn-on and

turn-off intervals. This jittering activity is exemplified in

Fig. 2 by the shaded areas around the switching transitions,

and will be referred to as the “jittered-t ON /jittered t OFF ” mode

of operation of the hysteretic modulator.

Therefore, although the cycle-by-cycle duty ratio is

produced only with a time resolution given by T clk , its value

over time is reproduced with higher resolution. In other words,

the jittering activity allows the modulator to reproduce duty

cycles with an effective time resolution finer than T clk .

Experimental evidence of this increase in effective resolution

is presented in Section III.

An immediate side-effect of this behavior is a

corresponding jittering of the switching period T s. In fact, the

very notion of “switching frequency” may appear ill-defined

in the context of the hysteretic modulator. However, the

average switching period ⟨T s⟩ and average switching

frequency ⟨ f s⟩ can be rigorously defined as the expected values

assumed by the per-cycle quantities:

3313




s

s

clk OFF ON OFF ON s

T f

T nnt t T

1≡

⋅+=+≡

. (3)

In the next subsection, a stochastic model is presented to

better analyze the switching behavior of the modulator. The

main purpose of the model is to express quantities (3) as

functions of the hysteresis window β and of the operating dutycycle D.

B. Analysis of the switching behavior

In this section a stochastic analysis is presented in order to

predict the average switching rate ⟨ f s⟩. In particular, the

average switching cycle ⟨T s⟩ will be derived as the expected

value of the quantity t ON + t OFF . Note that steady-state

operation of the modulator is assumed in the following

analysis, i.e. d = D = constant.

A primary consideration in the stochastic model presented

here is the assumption that in its steady-state operation the

modulator randomly spans all the possible switching

configurations compatible with the input duty cycle D. Inorder to formalize the concept, consider the switch turn-on

event detailed in Fig. 3, and assume D < 0.5. The quantity Δ

identifies one particular position of the ramp with respect to

the hysteresis window for a given input duty cycle D. As Δ

spans between 0 and 1, all possible switching configurations

for a given input duty cycle D are found. This assumption can

be formalized by letting Δ be a random variable uniformly

distributed between 0 and 1:

[ ]( )1,0U ∈Δ (4)

The situation presented holds when D < 0.5. Whenever

D > 0.5, a symmetric scenario must be considered with Δ associated with the switch turn-off event. As the problem is

symmetrical, the analysis is given here for the case of D < 0.5

to show that the assumption (4) explains the modulator

average switching rate as well as its dependence on the

hysteresis window β and duty cycle D with good accuracy. It

should be noted, however, that the system under consideration

is entirely deterministic, and that the assumption (4) is

introduced just to simplify the treatment using stochastic

analysis.

From Fig. 2 and based on simple geometrical

considerations, the number nON of clock cycles during the

turn-on interval is given by the total variation of the digital

ramp divided by its slope 1− D, the result rounded to the next

integer:

( )⎥⎦

⎤⎢⎣

⎡−

⋅Δ−+β=

D

Dceil nON

1

1. (5)

3 .33 3.34 3.35 3.36 3.37-0.25

0

0.25

0.5

0.75

1

1.253 .33 3.34 3.35 3.36 3.37

4.82

4.92

5.02

5.12

r

S

Time (μs)

+β/2

Δ·T clk

T clk

3 .33 3.34 3.35 3.36 3.37-0.25

0

0.25

0.5

0.75

1

1.253 .33 3.34 3.35 3.36 3.37

4.82

4.92

5.02

5.12

r

S

Time (μs)

+β/2

Δ·T clk

T clk

Fig. 3. Expanded view of the switch turn-on event.

In a similar way it is possible to express nOFF as:

( ) ( )⎥⎦

⎤⎢⎣

⎡ ⋅Δ−−−⋅=

D

D Dnceil n ON

OFF

11. (6)

Equations (5) and (6) express nON and nOFF as discrete

random variables which are functions of Δ. Stochastic analysis

can now be used to derive the turn-on and turn-off statistics,

and ultimately the expected switching rate (3). The results for

D < 0.5 can be summarized as follows:

1. The average switching rate ⟨ f s⟩ depends on both D

and β.

2. In general, nON jitters between at most two distinct,

consecutive values, while nOFF may jitter among

two to four distinct values. As already mentioned,

the mode of operation in which both the turn-on

and turn-off intervals are jittered during the

modulator steady-state operation is denoted as

“jittered-t ON /jittered-t OFF ”.

3. A discrete set of switching rates exists for which

nON assumes a single value with probability one;

correspondingly, nOFF jitters between at most two

consecutive values. This particular mode of

operation of the modulator will be denoted as

“constant-t ON /jittered-t OFF ”.

Examples of theoretical and experimental ⟨ f s⟩(β)

characteristics are shown in Fig. 4 for different values of D.

The clock frequency was set at f clk = 50 MHz. It can be seen

how the proposed stochastic analysis reproduces the ⟨ f s⟩(β) behavior with a fairly good accuracy over a wide range of

operating points and hysteresis windows.

3314




5 10 15 20 25400

450

500

550

600

5 10 15 20 25-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

β

⟨ f s(β)⟩kHz

D = 10%

20% 30%

40%

50%

− Theor.

o Exp.

Relative error %

5 10 15 20 25400

450

500

550

600

5 10 15 20 25-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

β

⟨ f s(β)⟩kHz

D = 10%

20% 30%

40%

50%

− Theor.

o Exp.

Relative error %

Fig. 4. Theoretical and experimental switching rate as a function of the

hysteresis window β and for different operating points

The latter point, i.e. the existence of a discrete set of

frequencies for which the modulator only jitters the turn-off

interval with a constant turn-on time, deserves a more detailed

discussion. Equation (5) predicts the existence of particular values of β for which nON assumes a single value with

probability one. This situation occurs when the argument of

the ceil (·) operator in (5) spans an interval strictly comprised

within two consecutive integers n and n+1 or, in other words,

when:

( ) ( ) D Dn Dn 21)1(1 −+−⋅≤β<−⋅ , (7)

where n is a natural number. Equation (7) identifies intervals

of β for which the constant-t ON /jittered-t OFF operation occurs.

It is easy to realize that n = nON −1, and therefore each possible

value of t ON generates an interval of the type (7) for β. When

the switching rate ⟨ f s⟩ is evaluated over intervals (7), a verysimple relationship is obtained:

ON

clk s

n

f D f

⋅= . (8)

In other words, when the modulator operates in constant-

t ON /jittered-t OFF mode, the average rate, which is given by (8),

does not depend on β. Intervals (7) therefore identify a

discrete set of frequencies associated with this particular mode

of operation.

Fig. 5(a) shows a detail of the ⟨ f s⟩(β) characteristic for

D = 0.2; intervals (7) are clearly visible, as well as the

corresponding discrete sets of frequencies. Fig. 5(b) reportstheoretical and experimental turn-on and turn-off probabilities

for a point inside the ⟨ f s⟩ = 500 kHz interval, confirming that

the modulator is jittering only the turn-off period.

1 3 13.5 14 1 4.5 15 15 .5 16 16.5 17400

450

500

550

600

β

⟨ f s(β)⟩, D = 20%

kHz − Theoretical

o Experimental

1 3 13.5 14 1 4.5 15 15 .5 16 16.5 17400

450

500

550

600

β

⟨ f s(β)⟩, D = 20%

kHz − Theoretical

o Experimental

(a)

14 15 16 17 18 19 20 21 22 23 24 250

0.25

0.5

0.75

1

1.25

73 74 75 76 77 78 79 80 81 82 83 840

0.25

0.5

0.75

1

1.25

nON

nOFF

p(nON )

p(nOFF )

Theoretical

x Experimental

Theoretical

x Experimental

(b)

Fig. 5. Detail of the ⟨ f s⟩ characteristic for D = 0.2 (a) and turn-on and turn-off

probabilities for β = 15.35 (b)

C. Control of the Average Switching Rate

One concern associated with the switching behavior of the

hysteretic modulator is the variation in the average switchingfrequency over converter operating duty cycles D. This section

shows how the hysteresis window β can be used to control the

average switching frequency to a nominal desired value over a

range of D.

The particularly simple expression (8), valid when the

modulator operates in the constant-t ON /jittered-t OFF mode,

lends itself to a straightforward switching frequency control

method. Consider β such that ⟨ f s⟩ is set as close as possible to a

nominal desired value f s. In this case:

⎟⎟ ⎠

⎞⎜⎜⎝

⎛ ⋅=

s

clk ON

f

f Dround n ~ . (9)

From (7) a unique β interval is selected by (9). Within this

interval, any choice of β would produce the same average

switching rate. Taking arbitrarily the midpoint of this interval

as the choice for β yields:

( )2

2111~

D D

f

f Dround

s

clk −+−⋅

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ −⎟

⎟ ⎠

⎞⎜⎜⎝

⎛ ⋅=β (10)

3315




Choice (10) allows selection of β as a function of the

converter operating duty cycle command D, which is a

quantity readily available in the digital controller. As the ratio

f clk / f s is a constant design parameter, evaluation of (10)

requires only simple arithmetic operations.

With choice (10), the average switching frequency is given

by:

⎟⎟ ⎠

⎞⎜⎜⎝

⎛ ⋅

⋅

⋅=

s

clk

s

clk

s s

f

f Dround

f f D

f f

~

~~

. (11)

It is important to note that an immediate drawback in using

(8) to control the switching frequency is a quantization effect

expressed by that very same equation. As a consequence,

exact tracking of an arbitrary f s cannot be achieved. This is

expressed, in (11), as the resulting average switching rate

being equal to the nominal value f s to within a factor of the

type x/round( x). However, the simple criterion expressed by

(10) justifies small residual variations in the average switchingrates. One may further observe that the higher the clock

frequency with respect to the nominal switching rate, the

closer ⟨ f s⟩ is to the nominal desired value f s.

Fig. 6 illustrates the theoretical and experimental plots of

(10) for f s = 390.625 kHz, f clk = 50 MHz and for different

values of the steady-state duty ratio D. As seen, the measured

switching rate matches the predicted value (11); as expected,

the x/round( x) factor generates residual variations of the

switching rate around f s. in spite of this slight non-ideality, the

criterion (10) limits the switching frequency deviation to

within few percentage points with respect to f s.

0.09 0.12 0.15 0.18 0.21 0.24370

380

390

400

410

Theoretical ⟨ f s⟩ Nominal f s

D

(kHz)

(a)

0.09 0.1 0.11 0.12370

380

390

400

410

D

(kHz)

Theoretical ⟨ f s⟩ Nominal f s

Experimental ⟨ f s⟩≈ ±4%

(b)

Fig. 6. Modulator nominal and average switching rate vs. operating point

with the proposed switching frequency control approach (a); expanded view

and experimental comparison (b)

D. Constant-t ON /jitterered-t OFF mode

The constant-t ON /jittered-t OFF option appears particularly

appealing especially at small duty cycles due to the higher

resolution compared to conventional constant-frequency

modulation techniques. To illustrate this point, consider first

the smallest duty cycle variation achievable through a

constant-frequency counter-based DPWM technique:

s N D

1min

=Δ , (12)

where N s = f clk / f s represents the number of modulator clock

cycles per switching period. A sigma-delta modulation

increases the resolution beyond (12) by dithering the duty ratio

command over several switching cycles. On the other hand, if

we consider a constant-t ON modulation scheme – i.e. a control

where the duty cycle is varied by modulating the turn-off

interval with a constant turn-on time – one has:

s N

D D =Δ

min, (13)

with a better resolution compared to (12), especially at small

duty cycles.

It is important to note that the proposed hysteretic

modulator does not implement a constant-t ON modulation,

since two different duty cycles are generally represented by

two different turn-on times. However, when operated in

constant-t ON /jittered-t OFF mode, each duty cycle is reproduced

in such a way that the turn-on interval does not change over

time. Therefore, through jittering of the turn-off interval

between two consecutive LSBs, resolution (13) or higher is

achieved.

Similar arguments regarding the modulator resolution have

been presented in [10] where it was recognized that a digital

constant-t ON modulation inherently has a higher resolution

than a constant-frequency modulation, with the main

disadvantage of having an extremely variable switching rate.

To address this issue, [10] proposes a modulation scheme in

which constant-t ON modulation and constant-frequency

modulation are combined.

In this context, the control criterion (10) can be thought of

as having a similar purpose: given a specific switching rate

given by (8), criterion (10) determines a particular nON . Once

nON has been selected to limit the switching rate variation, the

turn-off time is naturally jittered by the hysteretic modulator in

order to reproduce the duty cycle with high resolution. It isinteresting to observe that both of these goals – switching rate

control and constant-t ON operation – are simultaneously

achieved by a very simple control of the modulator hysteresis

window.

III. OPEN-LOOP PERFORMANCE

In this section the open-loop behavior of the proposed

hysteretic modulator is evaluated through computer

3316




simulations and experimental tests. In particular, it is of

interest to carry out a systematic comparison between the

proposed structure and a conventional first-order, multi-bit

ΣΔ-DPWM that would be slightly more complex in hardware

resources compared to the hysteretic modulator.

The configuration considered for this comparison consists

of the modulator under test – hysteretic or ΣΔ-DPWM –

followed by a power converter. The power stage taken as a

test case is a synchronous buck converter having V in = 12 V,

1.2 V nominal output voltage, L = 4.8 μH, C = 377 μF,

ESR = 1 mΩ.

The hysteretic modulator is clocked at f clk = 50 MHz, with a

nominal switching rate set to f s = 390.625 kHz, corresponding

to an average of 128 clock cycles per switching period. The

switching frequency control criterion (10) is employed to limit

the variations of ⟨ f s⟩ over the operating range.

For the ΣΔ-DPWM, the switching rate is set to f s in order to

provide a similar switching frequency as the hysteretic

modulator. The resolution of the core DPWM quantizer of the

ΣΔ-DPWM is set to 7 bits, corresponding to an LSB of 1/128

of the switching period. This choice allows a fair comparison between the two modulators, as both operate with the same

core time resolution T clk . Furthermore, the digital input duty

cycle command for both the hysteretic and the ΣΔ-DPWM

structure is assumed to be 13 bits wide.

The open-loop comparison was first simulated by slowly

sweeping the input duty cycle command and observing the

output voltage ramp waveform. The sweep was performed in

the range V o = 1V±100 mV, spanning about 137 LSB of the

13-bit input command. The comparison is shown in Fig. 7(a).

The output voltage of the ΣΔ-DPWM based system exhibits at

least three distinct spots where a significant perturbation is

observed. This well-known phenomenon is due to the

generation of low-frequency idle tones from the first-order ΣΔ

modulator [5], [6]. Interestingly, the voltage ramp generated

by means of the hysteretic modulator exhibits a different

behavior. From the expanded view shown in Fig. 7(b), the

hysteretic modulator is clearly able to transmit the 13-bit

resolution to the output voltage: the LSB step of the ramp is in

fact V in/213 = 1.5 mV. On the other hand, the resolution of the

ΣΔ-DPWM is clearly compromised by the idle tones

triggering rather large amplitude oscillations.

A similar test has been performed experimentally, with the

hysteretic modulator and the ΣΔ-DPWM coded in hardware

description language (HDL) and implemented on a Xilinx

Virtex-2 FPGA board. Fig. 8 and Fig. 9 illustrate the resultingoutput voltage ramp as the 13-bit input command is slowly

swept. The input sweep was performed at about 0.75 Hz and

spanned 64 LSB of the duty cycle command. The result of this

experiment is fully coherent with the foregoing simulation

test: though a 13-bit resolution is achieved in both cases, in the

ΣΔ-DPWM case regions are found in which the output voltage

is heavily corrupted by idle tones. No such phenomena are

observed with the hysteretic modulator.

0 2 4 6 8 10 12 14 16 1 8 200.9

0.92

0.94

0.96

0.98

1

1.02

1.04

1.06

1.08

1.1

0 2 4 6 8 10 12 14 16 1 8 200.9

0.92

0.94

0.96

0.98

1

1.02

1.04

1.06

1.08

1.1

time (ms)

vo (V)

ΣΔ-DPWM

vo (V)Hysteretic Modulator

Idle tones

(a)

3 3.5 4 4.5 50.93

0.94

0.95

time (ms)

vo (V)ΣΔ-DPWM


LSB = 1.5mV

(b)

Fig. 7. Simulated open-loop response to a duty cycle ramp; comparison

between the hysteretic modulator and a conventional first-order ΣΔ-DPWM

(a) and close-up comparison around a specific operating point (b)

10 mV/div

40 ms/div

LSB = 1.5mV

vo

Channel offset: 1.19V

10 mV/div

40 ms/div

LSB = 1.5mV

vo


Fig. 8. Experimental open-loop response to an input duty cycle ramp; proposed hysteretic modulator

3317




10 mV/div

40 ms/div

LSB = 1.5mV

vo


Idle Tones

10 mV/div

40 ms/div

LSB = 1.5mV

vo


Idle Tones

Fig. 9. Experimental open-loop response to an input duty cycle ramp;

conventional first-order ΣΔ-DPWM

To further investigate the open-loop noise performance, the

power spectral density (PSD) of the converter output voltage

was measured with the converter in open-loop, steady-stateoperation – i.e. at a constant input duty-cycle command D. A

comparison between the two systems under consideration is

exemplified in Fig. 10, which illustrates the two PSD

measured at D ≈ 8%, a particular operating point where the

ΣΔ-DPWM was recognized to generate particularly large idle-

tone oscillations. The most striking difference between the two

lies in the low-frequency range, where the tone-generation

activity of the hysteretic modulator is almost absent. Note,

however, that the hysteretic structure does generate low-

frequency tones – one is visible around 12 kHz.

More extensive experimental tests have shown that the

smaller the steady-state duty cycle, the less prone thehysteretic modulator is to generating low-frequency tones.

When the hysteretic modulator is operated at small D – e.g.

around 10% or less – its low-noise properties outperform those

of a first-order ΣΔ-DPWM having the same core hardware

resolution. At higher duty cycles, spots were found where the

tone generation of the hysteretic structure was slightly higher

than the ΣΔ-DPWM. Nevertheless, the hysteretic modulator

manifests a generally much less severe tone generation

activity compared with first-order ΣΔ-DPWM.

10 100 1k 10k 100k 1M 10M 62.5M-40

-30

-20

-10

0

Frequency (Hz)

(dB)

Hysteretic

ΣΔ-DPWM Switching

Harmonics

Fig. 10. Experimental power spectral density; comparison between

proposed hysteretic modulator and a conventional ΣΔ-DPWM; D=0.08

IV. CLOSED-LOOP PERFORMANCE

Compared with a conventional ΣΔ-DPWM, an important

advantage of the proposed structure is its ability to operate in a

multi-sampled fashion. Referring back to Fig. 1(a), this means

that the controller samples and processes the voltage error

with a sampling rate higher than the converter switching rate,

i.e. f smp = N · f s, N > 1. Similar to conventional DPWM

structures, the multi-sampling operation significantlydecreases the modulator small-signal phase lag [9], thus

enabling high-bandwidth designs [7], [8]. An important point

to be stressed is that conventional ΣΔ-DPWM structures

cannot be operated at f smp > f s because of the re-sampling

action of the PWM block following the ΣΔ modulator. This

represents a strong advantage of the proposed structure over

the entire class of ΣΔ-based PWM realizations.

The closed loop operation was tested through simulation

and experimental tests on the same setup described in

Section III. A simple digital PID structure was used as the

voltage loop compensator, with the output voltage regulated at

V ref = 1.2 V and sampled by a 12 bit, 4 V full-scale range

pipeline A/D converter clocked at 12.5 MHz. The output

stream of the A/D was then downsampled to the desired

sampling rate f smp.

As far as the switching rate control is concerned, criterion

(10) was employed. In order to avoid abrupt variations of the

modulator hysteresis window β during transients, the value of

D in (10) was substituted with the integral term of the PID

control command.

An important aspect to be considered when employing the

hysteretic modulator in a feedback loop is represented by its

inherent tendency of varying the switching rate with the

operating point, as exemplified in Fig. 4. Whenever a fixed

sampling rate f smp is adopted, any slight difference between f smp and ⟨ f s⟩ – or between f smp and N ·⟨ f s⟩ in multi-sampled designs –

will result in a sampling instant not synchronized with the

switching period. This situation can be detrimental, since a

sampling instant falling too close to a switching transition

could catch excessive noise and compromise the regulation. In

the experimental setup, a low-noise differential sensing of the

output voltage was implemented to mitigate the switching

noise effects.

A first single-sampled controller was designed for a

bandwidth f c = 20 kHz with 70º phase margin. A second, high-

bandwidth 4-sampled compensator was designed for a

f c ≈ 66 kHz and 62º phase margin. The target switching

frequency, the same in both cases, was

f s = 50 MHz/128 = 390.625 kHz. In the single-sampled design,

the output voltage sampling rate was set equal to f s and the

A/D resolution to qAD ≈ 8 mV by ignoring a number of LSBs

from the A/D output; this choice resulted in limit cycle-free

steady state operation. On the other hand, in the high

bandwidth multi-sampled design with the sampling rate equal

to 4· f s a small amount of steady-state limit cycling was

tolerated; the limit cycling amplitude was reduced to

3318




-20 0 20 40 60 80 100 1 20 140 1 60 1801.1

1.15

1.2

1.25

1.3

time (μs)

vo (V)

Single-sampled design

Multi-sampled design

Fig. 11. Simulated closed-loop transient response to a 0-4.6 A load step;

comparison between single-sampled and multi-sampled design using the

proposed hysteretic modulator.

negligible values by reducing A/D LSB down to ~2 mV.

The simulated transient responses of the two foregoing

controllers to a 0-4.6 A load step are compared in Fig. 11.

Corresponding experimental tests are shown in Fig. 12 and

Fig. 13 for the single-sampled and multi-sampled design

respectively. The multi-sampled design allowed by the

proposed modulator fully recovers the output voltage

deviation in less than seven switching cycles. On the other

hand, no ΣΔ-based design employing a conventional PID

compensator could achieve similar performances, due to theaforementioned limitation of the sampling frequency.

V. CONCLUSIONS

An alternative modulation approach for digitally controlled

DC-DC converters is proposed. By exploiting the inherent

jittering activity of a digital hysteretic loop, the proposed

modulator increases effective resolution without the need for a

high frequency clock. Control of the switching rate is achieved

through adjustment of the hysteresis window. When operated

at relatively small duty cycles, the proposed modulator

exhibits much better noise performance compared to

conventional first-order ΣΔ-DPWM of similar hardware

complexity and core resolution. Furthermore, in contrast toΣΔ-based solutions, the proposed hysteretic modulator can be

employed in a multi-sampled feedback control loop, thus

enabling high bandwidth designs. Simulation and

experimental results were presented for a 12V-to-1V, 5A

synchronous buck converter, validating the open-loop and

closed-loop characteristics of the proposed structure.

R EFERENCES

[1] D. Maksimovic, R. Zane, R. Erickson, “Impact of Digital Control inPower Electronics”, in Proc. 2004 ISPSD Conf., pp. 13-22

[2] B. J. Patella, A. Prodic, A. Zirger, D. Maksimovic, “High-FrequencyDigital PWM Controller IC for DC–DC Converters”, IEEE Trans. on

Power Electronics, vol. 18, no 1, pp. 438-446, Jan. 2003.[3] J. Xiao, A. V. Peterchev, S. R. Sanders, “Architecture and IC

implementation of a digital VRM controller”, IEEE Trans. on Power

Electronics, vol 18, no. 1, pp. 356-364, Jan. 2003.

[4] A. Syed, E. Ahmed, D. Maksimovic, “Digital Pulse-Width Modulator Architectures”, in 2004 IEEE Power Electronics Specialists Conf., pp.

4689-4695

[5] M. Norris, L. Marco Platon, E. Alarcon, D. Maksimovic, “Quantization Noise Shaping in Digital PWM Converters”, in 2008 IEEE Power

Electronics Specialists Conf., pp. 127-133

20μs/div

50mV/div

5A/div

vo

i L pwm

load enable

20μs/div

50mV/div

5A/div

vo

i L pwm

load enable

Fig. 12. Experimental closed-loop transient response to a 0-4.6 A load

step, single-sampled design; vo: 50mV/div, i L: 5A/div, time scale 20 μs/div

20μs/div

50mV/div

5A/div

vo

i L pwm

load enable

20μs/div

50mV/div

5A/div

vo

i L pwm

load enable

Fig. 13. Experimental closed-loop transient response to a 0-4.6 A load

step, multi-sampled design; vo: 50mV/div, i L: 5A/div, time scale 20 μs/div

[6] Z. Lukic, N. Rahman, A. Prodic, “Multibit Σ-Δ-PWM Digital Controller

IC for DC-DC Converters Operating at Switching Frequencies Beyond10 MHz”, IEEE Trans. on Power Electronics, vol. 22, no. 5, pp. 1693-

1707, Sept. 2007

[7] L. Corradini, P. Mattavelli, “Modeling of Multisampled Pulse WidthModulators for Digitally Controlled DC-DC Converters”, IEEE Trans.

on Power Electronics, vol. 23, no. 4, pp. 1839-1847, Jul. 2008

[8] L. Corradini, P. Mattavelli, E. Tedeschi, D. Trevisan, “High- BandwidthMultisampled Digitally Controlled DC-DC Converters Using Ripple

Compensation”, IEEE Trans. on Power Electronics, vol. 55, no. 4, pp.

1501-1508, Apr. 2008

[9]

D. M. Van de Sype, K. De Gussemé, F. M. L. L. De Belie, A. P. Vanden Bossche, J. A. Melkebeek, “Small-signal z-Domain Analysis of

Digitally Controlled Converters”, IEEE Trans. on Power Electronics,vol. 21, no. 2, March 2006, pp. 470-478

[10] J. Li, Y, Qium Y. Sun, B. Huang, M. Xu, D. S. Ha, F. C. Lee, “HighResolution Digital Duty Cycle Modulation Schemes for Voltage

Regulators”, in Proc.2007 APEC , Feb. 25-Mar 1 2007, pp. 871-876

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