Functionality

Functionality – the number of different Boolean function that the logical block can realise. For example:. 1. 2NAND realises 5 functions:

f = a b f = a f = b f = 0 f = 1

2. LUT 2 with three inputs =256 functions 3

Chip Area) Speed Performance Routing Resources. Routing resources

takes 70-90% of the chip area. depend upon the architecture of the block (functionality).

2

The functionality of the block and the effectiveness of the use of the chip area

If functionality increases: The number of logical blocks decreases

(more and more of logic is realised within a single block)

The block area increases ( it is more complicated)

The impact of the increase in functionality on routing:

The number of outputs of a logical block is likely to increase;

The number of connections between the logical blocks is likely to decrease;

Due to the smaller number of logical blocks the length of lines increases

The overall impact of the complexity of the logical block on routing is very important as routing takes most of the chip area.

Example.

Two-input LUT-s – 32 memory bits and 17 connections

Let us realise the function f = abc + bcd + a b c

AND

AND

AND

AND

AND

AND OR

OR

a

b

cb

c

c

da

Three-input LUT-s - 32 s memory bits and 13 connections

OR

AND

AND

AND

abc

b

c

c

d

a

b

b

Four input LUT-s - 16 memory bits and 5 connections

a

cb

d

Logical blocks based on LUT-s

LUT

LUT

S

MUX

0

1

S

MUX

0

1

T

T

Area of the logical block LBA = FA + (M BA 2 )

LBA –area of the logical blockFA – fixee areaM – number of LUT-sBA – area of the bit

xxk

Geometrical model

Logicalblock

CL

CL

W RPX

W RPX

CL + ( ) W RPX

RP – Routing Piich

Symmetrical FPGA.

RALB = 2(CL W RP) + (W RP) 2

x xx

RALB – Routing Area per LB

Row Based FPGA.

RALB = CL W RPx x

Total area

Total Area = Nblock (LBArea + RALB)

.

The number of LUT bits is constantly 5 .

M=1

LUT

IN1

IN5

.

.

.

OUT

M=2

LUT

IN1

IN4

.

.

.

LUT

IN10

IN5

IN9

.

.

.

MUX0

1 s

OUT

Logical blocks with decomposable LUT-s

M=4LUT

IN1

IN3

LUT

IN13

IN2

MUX00

01

s0 s1

OUT

Logical blocks with decomposable LUT-s II

10

11LUT

LUTIN10

IN12IN11

IN7

IN9IN8

IN4

IN6IN5

IN14

M=8

LUTIN1

LUT

IN19

IN2

MUX000

001

s0 s1 s2

OUT

Logical blocks with decomposable LUT-s III

010

011LUT

LUTIN7IN8

IN5IN6

IN3IN4

LUTIN9

LUT

IN10

LUT

LUTIN15IN16

IN13IN14

IN11IN12

100

101

110

111

IN17IN18

Experimental results:

Summary of the functionality and area-effectiveness of the logical block:

1. One-output LUT is the best while K=42. Pins waste area. The best solution is large functionality per pin. 3. LUT with several outputs is not effectual.4. The best block based on PLA has 8-10 inputs, 12-13 terms and 3-4

outputs.5. In case of decomposable LUT-s the best solution is M=46. Adding trigger to the logical block is effectual

Functionality of the logical block and its performance

Dtot = Nl (Dlb + Dr)

Dtot –total delayDlb – delay of the logical blockDlb –delay of routingNl – number of logical blocks at the critical path

x

If functionality increases:1. 1.    the number of levels (logical blocks) decreases at the path of

the signals;2. 2. the delay of the logical blocks increases (bigger and more

complex);3. 3.    the total routing delay decreases;4. 4.    total delay ?

Example.

&

&

&

&

&

&

&

&

&

&

a

b

c

d

a

c

d

a

b

c

d

a

a

b

c

d

The logical blocks contain NAND elements with two outputs

The logical blocks contain three-input LUT-s

2NAND delay 0,7 ns3-LUT delay 1,4 nsRouting delay >0

LUT is swifter

Two different realisations of the function f = a d b + a b c + a c d

1. LUT with 5-6 inputs is good in case of a medium-sized routing delay

2. Low functional logical blocks (such as 2NAND) are not swift;

3. It is effectual to add the inversion possibility in case of simple logical blocks.

4. It is effectual to increase the number of terms from three to five in case of large AND-OR blocks

Summary concerning the functionality and speed of the logical block

Summary

1. Logical blocks with a very low level of functionality are not good both from the point of view of speed and functionality;

2. Large functionality per output is good (e.g LUT-s)

3. The best LUT is with 4 inputs;

4. The best logical block from the point of view of area is the one where PLA structures are used;

5. Decomposable LUT-s can be effectual in solving some type of tasks;

6. Non-homogenuous structures can be more useful than homogenuous;

7. Hierarchical FPGA organisation may be more effective than a single-level organisation