fundamental of fpga design flow - duc.edu.iq filesynthesis: convert hdl code into fpga based...
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![Page 1: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/1.jpg)
Fundamental of FPGA Design Flow
by
Ass. Prof. Dr. Majid S.Naghmash Dijlah University College, Computer Engineering Techniques Department
2016
![Page 2: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/2.jpg)
FPGA design flow
EDIF UCF
HDL of Activation System
FPGA / ADC / DAC
![Page 3: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/3.jpg)
Synthesis : Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User Constraint File)
Translate : Merges the Netlist EDIF file with user constraint file UCF into Xilinx FPGA design file NGD ( Native Generic Database file )
Map : Map the logic defined by an NGD file into FPGA elements in NCD file NCD File ( Native Circuit Description file)
Place & Rout : Place and rout the design NCD file to the time constraint and produce PAR report ( place and rout report)
Programming File Generation : produce bit stream for FPGA Configuration BGN
EDIF UCF
NGD
NCD
PAR optimized NCD
BGN
FPGA
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Implementation results
project status and device utilization summary generated by ISE Software
![Page 5: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/5.jpg)
![Page 6: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/6.jpg)
![Page 7: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/7.jpg)
Mapping: NCD to Logic
![Page 8: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/8.jpg)
Placing: Logic file to FPGA hardware architecture
![Page 9: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/9.jpg)
Routing: convert the design to FPGA hardware and ruoting
![Page 10: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/10.jpg)
![Page 11: Fundamental of FPGA Design Flow - duc.edu.iq fileSynthesis: Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User](https://reader031.vdocument.in/reader031/viewer/2022022118/5cc1a15488c9933e3a8c93ec/html5/thumbnails/11.jpg)
No
Yes
No
No Yes
Yes
No
Yes
DSP modeling
Simulation of data flow at each stage of
DSP model
Generate HDL netlist of DSP model
Simulation of data flow at each stage of
HDL netlist of DSP model
START
HDL integration of DSP model netlist
and setup configuration
Simulation of data flow at each stage of
HDL integrated design
HDL design of setup configuration for
ADC, DAC, and clock synthesizer
Simulation of data flow at each stage of
HDL module of setup configuration
Result correct?
Result correct?
Result correct?
Result correct?
No Yes ModelSim
Environment
Xilinx
System Generator
+
Simulink (MATLAB)
Environment
Synthesis of HDL integrated design
Estimated timing simulation of
synthesized integrated design
Timing error? Increase latency at the
worst delayed path
Pin assignment of I/O ports on FPGA
2
2
2
Synplify Pro
Environment
1
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Thank you for your attention!
Questions?