fundamentals of hdl (first 4 chapters only) - godse

A. P. Goclse D.A.Goclse

Technical Publications Punes

Fundamentals of HDL ISBN 9788184314052

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Published by : Tuchnical Publications rune" # 1, Amit Residency, 412, Shaniwar Peth, Pun• - 411 030, Ind" ...

Printer : Ale<t DTPrintm Sr.no. 10/3,Sinlw51d Ro1d, l\.nt • 41 1 041

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Table of Contents

1.1WhyHDL? ........................................................................................... 1-1

1.2 A Brief History of HDL ......... .... ... ........................ ...... ...... .................. ... 1 - 2

1.2.1 A Brief History of VHDL . . .. . .... . . .. . ....... . . . ..... . . . . .. . .. . .. . ... . . . ..... 1 - 2

1.2.2 A Brief History of Verilog HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 1 - 3

1.3 Structure of the HDL Module ................ ........ ....... ..... ........ ....... ........ .... 1 - 3

1.3.1 Structure of the VHDL Module . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . .. .. . . . . . . 1 - 3 1.3.1.1 Package. . 1-4

1.3.1.2 Entity . . . . . 1 -5

1.3.1.3 Architecture . ·. 1 - 7

1.3.1.4 Configuration. . 1 -8 1.3.2 Structure of the Verilog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 9

1.4 Operators ............... ...... ................ ...................................................... 1 - 10 1.4.1 Operators in VHDL. . . . . . . . . . . . • . .. . .. . . . . .. . .. . . . . . .. .. . . . . . . .. . . . . . . .. .. . . 1 - 1 O

1.4 .1.1 Logical Operators . 1 - 11

1.4 .1.2 Relational Operators . . . 1 - 12

1.4.1.3 Arithmetic Operators . . . 1 -13

1.4.1.4 Shift and Rotate Operators . 1 -14

1.4.1.SOperatorPrecedence . 1- 14 1.4.2 Operators in Verilog HDL ..... . . . ............ . .... . ....... . . . .. . . . . .. . ...... . 1 -15

1.4.2.1 Boolean Logical Operators. . . . 1-15

1.4.2.2 Unary Reduction Logical Operators 1 -16

1.4.2.3 Bitwise Logical Operators . 1 -16

1.4.2.4 Relational Operators . . 1 - 16

1.4.2.5 Binary Arithmetic Operators 1 - 17

1.4.2.6 Unary Arithmetic Operators. 1 - 17

1.4.2.7 Other Operators . . 1 - 17

1.4.2.8 Operator Precedence. 1 - 18


1.5 Data Types .................................................... ....... ............. ......... ........ 1 - 18

1.5.1 VHDL Data Types .... . ...... . .. .. .. . .. ... .. . . ... . . . • . . . . . . . ......... .. .. .. 1 -19 1.5.1 .1 Scalar Types . . 1 - 19

1.5.1.2 Comoostte Types. 1-22

1.5.1.3AccessTypes . 1-25

1.5.1.4FileType . . .. 1-25

1.5.1.50therTypes. . . 1- 26 1.5.2 Verilog Data Type .. . . . . .. . .. ...... .. .. ..... . .............. . . ..... . ......... 1 - 27

1.5.2.1 Nets (Wire) and Registers . . . . . . 1-27

1.5.2.2 Abstract Data Types : integer, real time . . . . . . . . . . . . . . . . . . . 1 -28

1.5.2.3 Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 29

1.6 Styles or Types of Descriptions ....... ......... .......................... ........ ....... 1 - 29

1.6.1 Behavioral Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . 1 - 30

1.6.2 Dataflow Design Elements .. .. .. . .. .. .. .. .. . ............. .................... 1 - 31

1.6.3 Structural Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 32

1.6.4 Switch-Level Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 33

1.6.5 Mixed-Type Descriptions . .. .. .. ...... .. ..... .... ...... ...... ... .. . .. . .. . .. .. 1 - 34

1.6.6 Mixed Language Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 35

1.7 Simulation and Synthesis ...................... ......... .................................... 1 - 36

1.7.1 Synthesis . .. . . .... . .. .... .. . .. . .. . . .. .. . . . .. .. .. . .. . ..... ... .. .. .. . . . . ... 1 - 36

1.7.2 Simulation . . . .. . ......... .. . . .... ..... ...... . .. . ... . ............ . . .. . ... . . 1 - 37

1.8 Brief Comparison of VHDL and Verilog ...... ... ........ ............................ 1 - 38

1.9 Summary of Operators in VHDL and Verilog ......... ............................ 1 - 39

Review Questions ........... ................. ........... ............................................. 1 - 41

2.1 High Lights of Data-Flow Description ... ....... .. ....... .............................. .. 2 - 1

2.2 Structure of the Data-Flow Description ....... .. ....... ....... ............. ............ 2 - 1

2.2.1 Signal Declaration and Assignment Statement .. .. . .. . .... . ......... ....... .... .. . 2 - 2

2.2.2 Execution of Assignment Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2

2.2.3 Constant Declaration and Assignment Statement .. .. . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4

2.3 Data Type - Vectors ......................... ............ ........ ...... ....... ...... ............. 2 - 8

Review Questions .............. .......................................................... ......... ... 2 - 26

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3.1 Behavioral Description Highlights ............................. ......... .......... ........ 3 - 1

3.2 Structure of the HDL Behavioral Description ....................................... 3 - 1

3.3 The VHDL Variable Assignment Statement.. ....................................... 3 - 4

3.4 Sequential Statements ........... .............................................................. 3 - 4

3.4.1 IF Statement. . .......... . .... . .. ................. . .................... . .... 3 - 4

3.4.2 Signal and Variable Assignment ...... .. . . . ... . .. . .. . ........ . . . . ... . ...... .. . 3 - 10

3.4.3 Case Statement . . ...... . . .. ............. . .. . . .. . ..... . . ........ . . ......... 3 -13

3.4.4 Comparison between CASE and IF Statement ... . .... . ..... . . ........... . ...... . 3 - 14 3.4.4.1 Verilog Casex and Casez . . . . . . . . . . . . . . . . . . . . . . . . 3- 20

3.4.5 Loop Statement . .......... . . . . . . . . .. .. . ... . .. . . . ........... . ............. . 3 - 21 3.4.5.1 For-Loop Statement. . 3- 21

3.4.5.2 While-Loop Statement. 3-23

3.4.5.3 Verilog Repeat. . . 3-23

3.4.5.4 Verilog Forever . . . 3 -24

3.4.5.5 VHDL Next and Exit. . 3 - 24

Review Questions ....... ............................................................................ 3 - 35

4.1 Highlights of Structural Description .. ................. .... ........ .................... .. 4 - 1

4.2 Organization of the Structural Description ...... .............. .................... .. 4 - 1

4.3 Binding ........... ........ ........ ........................... .............. ............................. 4 - 4

4.3.1 Binding between Entity and Architecture in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 4 - 4

4.3.2 Binding between Entity and Component in VHDL . . . . . . . . . . • . . . . . . . . . . . . . . . . . • . . . . . 4 - 5

4.3.3 Binding between Library and Module in VHDL. ................. . .... . ............. 4 - 6

4.3.4 Binding between Two Modules in Verilog . . .. . . .. . .. .... .. . . .. . .. . .. . .. . ........ . 4 - 8

4.4 State Machine .................................................................................... 4 - 36

4.4.1 Types of Sequential Circuits .... . . . .. .. . . .. . . . . .. . .... .. . .. . . .... .. . . ..... . . . . 4 - 37

4.4.1.1 Moore Model . . . . . . . . 4 - 37

4.4.1 .2 Mealy Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 39

4.4.1.3 Moore Vs Mealy Circuit Modets . . . . . . . . . . . . . . . . . . . . . . 4-40 4.4.2 State Machine Notations . ......... ..... ... .. . . . . ...... . .. ..... .. . ..... . ..... 4 - 40

4 4 2 1 State and State Variable 4-40

4 4 2 2 Present State and Next State . . . . . . . . . . . . . . . . . . . . 4-40


4.4.2.3 State Transition Diagram

4.4.2.4 State Table . . . . . .

4 -41

4 -42

4.4.2.5 Transition Table . 4 -43

4.5 Design Equations and Circuit Diagram ............................................. 4 - 43

4.6 Generate (HDL), Generic (VHDL), and Parameter (Verilog) ............ 4 - 53

Review Questions ............................... .. ........ ......... .................................. 4 - 64

5.1 Highlights of Procedures, Tasks and Functions .................................. 5 - 1

5.2 Procedures and Tasks ......................................................................... 5 - 1

5.2.1 Procedures (VHDL) . .. .... · ..... . . ..... . ... .... ... .... ........ .. ... . .... . .... 5 - 2

5.2.2 Tasks (Verilog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3

5.2.3 Examples of Procedures and Tasks ....... . .. . ... . ... . .. .. . . . ..... ........ . ..... 5 - 4

5.3 Functions ........................................................................................... 5 - 21

5.3.1 VHDL Functions .. .. . . . .... . .... . ......................... ........ ..... .. .. 5 - 22

5.3.2 Verilog Functions .... . ..................................................... 5 • 22

5.3.3 Function Examples . .. .. . . .. . .. . ... . .. .. .. .. .. .. .. . .. . .. . .... . .. . ........... 5 - 23

5.4 Advanced HDL Descriptions : File Processing .................................. 5 - 27

5.4.1 VHDL File Processing .. . ....................................... . ........... 5 - 27

5.4.2 Verilog File Processing . ..... .. ...... . .. . .. .. ..... .. .. . .. .. ......... . .. . .. .. . 5 - 30

5.5 Examples of File Processing .............................................................. 5 - 33

5.5.1 Examples of VHDL File Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33

5.5.2 Example of Verilog File Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 · 40

Review Questions ................. ............................................... ...... ....... ,, .. ,, 5 - 41

6.1 Why Mixed-Type Description? ........... .......... ........ ...... ......................... 6 - 1

6.2 VHDL User-Defined Types ................. ......................................... ........ 6 - 1

6.3 VHDL Package .................................................................................... 6 - 2

6.3.1 Implementation of Arrays .. . .. . ... . .. .. .. .. .. . ... . .. . .. . .. .... . . .... .. . . ... . .. 6 - 4 6.3.1.1 Single-Dimensional Arrays in VHDL . . . 6 -4

6.3.1.2 Single - Dimensional Arrays in Verilog . . . . . . . . . . . . . . . . . . . . 6 -5

6.3.2.3 Two-Dimensional Arrays. . . . . . . . . . . . . . . . . . . . . . . . . 6 -11


6.4 Mixed-Type Description Examples ... ..... ........ .. .... .. ..... ....... .......... ...... 6 - 12

Review Questions ....... ........ ........ .... ........... ......... .............. ..... ,, 6 - 24

7.1 Highlights of Mixed-Language Description ............ ..... ....... ....... ........... 7 - 1

7.2 How to Invoke One Language from the Other ..... .. ........... ......... .. ..... ... 7 - 1

7.2.1 Invoking a VHDL Entity from a Verilog Module .. .. .. . . . . ..... • . . • . . • .. • ... . ... ... . 7. 1

7.2.2 Invoking a Verilog Module from a VHDL Module .. . . . .... . . .... ... . .. . ...... . .. . .. 7 • 3

7 .3 Mixed-Language Description Examples ............... ....... ........ ........ ........ 7 - 4

7.4 Limitations of Mixed Language Description ... .. ...... ........ ....... ........ ..... 7 - 16

Review Questions ... ..... ... ................ ......... .. ,, ........ ......... ,,... ... .... . 7 - 17

8.1 Highlights of Synthesis ........ ........ ........... ................ ........ .................... .. 8 - 1

8.2 Synthesis Information from Entity and Module .......................... .......... 8 - 3

8.2.1 Synthesis Information from Entity (VHDL) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 8 • 3

8.2.2 Verilog Synthesis Information from Module Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 • 9

8.3 Mapping Process and always in the Hardware Domain ........... ......... 8 - 11

8.3.1 Mapping the Signal-Assignment Statement to Gate-level. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 • 11

8.3.2 Mapping the Variable-Assignment Statement to Gate-Level Synthesis. . . . . . . . . . . . . . . . . 8 • 15

8.3.3 Mapping Logical Operators . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . 8 · 16

8.3.4 Mapping the IF Statement .. .. . . . .. . •.. • . . . . .. .• .. . .. • . . • .. • .. •. . . . . . . . . . . . .. 8 -19

8.3.5 Mapping the Case Statement. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 8 • 31

8.3.6 Mapping the Loop Statement .. . ... . .. . . .. . . .. . ... ..... . . ....... . . . . . ... . . . . . . 8 • 37

8.3.7 Mapping Procedure or Task .. ... . .. . . . . . . .. . . . . . .. . . . . .. . . . . .. . .. .. .. . ... . . .. 8 • 38

8.3.8 Mapping the Function Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 • 40

Review Questions ................................................................................... 8 - 43

A 1 VHDL Standards .. . ... . ,, ..... ........ . ,, .... ......... ................. ... ,, .. .. A - 1

A.2 Predefined Packages ... ........ ... ........ ... ....... .. ..... ... ...... ............... ........... A - 2

A.2.1 Standard . . . . ... . .. . .. . . . . . .. . ... . . . .. . . . ...... . .. . .. . ..... . .. . . . .. . .. . . . . A· 2

A.2.2 TEXTIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A • 4

A.2.3 STD LOGIC 1164 .. .. . . . . . .. . . .. . .. . .. . . .. .... . .. . .. .. ... . . .. .. ....... . .. A· 5

A.2.4 NUMERIC_BIT . . . .. . ... .. . • ... .. . . . ..... • . .. . ....... . .......... • .. • .. ... . . A- 8

A.2.5 NUMERIC STD .. . .. ...... . .. ......... . ...... . ... . .. . ..... . .. . .......... .. A-1 1

A.2.6 MATH REAL . .. . ......... .. . . .. .. .. . ....... . ..... . ........ .. . . . . ... . .. ... A-15

A.2.7 MATH_COMPLEX ..... . . ... . .................. . . ....... ............... ... . A - 16

B.1 Decoders in VHDL ...................... ....... .................... ...... ................. ..... B - 1

B 2 Encoders in VHDL. ....... ........ . .. .. .. ............. . B - 5

B.3 Three State Devices in VHDL ............................................................. B - 9

B.4 Multiplexers in VHDL. .............. ........... ......... ...................................... B - 12

B.5 Parity Circuits in VHDL. ...................................... , ............................. . B - 15

B.6 Comparators in VHDL .................... ............ ..................... ....... ........... B - 16

B 7 Adders and Subtracters in VHDL ... ........... .............................. .......... B - 18

B.8 ALU in VHDL ........................................................... .............. ............ B - 21

B.9 Multipliers in VHDL. .... ........ ........ , .................... .................................. B - 22

B.1 O VHDL Code for Barrel Shifter .......................................................... B - 23

B.10.1 Barrel Shifter . . . . . . . . .. . .. . . .. .. .. . .. . .. . .. . . . . . . . . . . . . . . . .. . .. .. . . .. . . . . B - 23

B.10.2 Barrel Shifter using VHDL ... . .. . ... . . .. . ..... . . .. .. ... . ... . .... . , . .. . ...... B • 25

B.11 VHDL Code for Simple Floating - Point Encoder ........................... B - 26

B.1 1.1 Simple Floating-Point Encoder . . . . .. . . . . .. . . .. . . . . . . . . . . . .. . . . . . . .. . . . .. . . .. B - 26

B.1 1.2 Simple Floating-Point Encoder in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B • 28

B.12 VHDL Code for Cascadina Comp.:.rators ................................... ..... B - 28

8.12.1 Cascading Comparators . . . . . . . .. .. .. . .. . . .. . . . .. . . . . . . . . . .. . . . . . . .. .. . . .. . B - 28

B.12.2 Cascading Compa1ators in VHDL ....... . ... .. . . . .. .. . . . . .. . .. .. .. . .. . ... .... B. 30

B.13 VHDL Code for Dual Priority Encoder ............ .......................... ....... B - 30

B.14 VHDL code for Ones Counter........................................................ B - 33

B 14 1 Behavioral VHDL Code for a 32-bit Ones Counter . . 8-33

8.14.2 Structural VHDL Code for a 32-bit Ones Counter . .. . ... . . . ..... . .. . .. .. .. . .. .. .. B - 34

B.15 VHDL Code for Binary to Gray Code Converter ... .............. ............ B - 38

B.16 VHDL Code for Gray to Binary Code Converter ............................. B - 40

B.17 VHDL Code for Latch ...................................... .............. .................. B - 42

B.18 VHDL Code for Flip-Flop ..... ........ ............ ........ ................................ B - 43

B.18.1 VHDL Code for a D Flip-Flop using IF-THEN Statement . . . . . . . . . . . . . . . . . . . . . . . . . . B • 43


B.18.2 VHDL Code for a D Flip-Flop using WAIT-UNTIL Statement . . .................. .. . B - 44

B.18.3 VHDL Code for a D Flip-Flop with Asynchronous ReseliClear . . . . . . . . . . . . . . . . . . . . . . B - 45

B.18.4 VHDL Code for a D Flip-Flop with Synchronous ReseVClear . . . . . . . . . . . . . . . . . . . . . . . B - 45

8.18.5 VHDL code for a DFF with a negative-edge clock and asynchronous dear .. . ... . .. . .. B - 46

8.18.6 DFF with Positive-Edge Clock and Synchronous Set ... . . . .... ... ... .. . . ... . .. ... B - 47

8.18.7 DFF with Positive-Edge Clock and Clock Enable . .. .. . .. .. . .. .. . .. .. ... ... .. . .. . B - 48

B.18.8 VHDL Code for JK Flip-Flop .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . B - 48

B.12 VHDL Code for Registers ................................................................ B - 49

8.19.1 VHDL Code for a Four-bit Register ... ... . ...... . .. . ....... .. .. .. . . ... . .. .. . .. B-49

8.19.2 4-bit Register with Positive-Edge Clock, Asynchronous Set and Clock Enable . . . . . . . . . B - 50

8.19.3 VHDL Code for an N-bit Register . .. . ... . .. . .. . ... . .. . ...... . . .... ... . ... . . .. B - 51

8.19.4 VHDL Code for a Shift Register. . ... . ... •.. . ..• . ........ . ...•..•..• .. . . .. . . .. 8 - 52

B.19.4.1 Using Sequential Statements . . . . . . B-52

B.19.4.2 Hierarchical Code for a 4-bit Shift Register . . . . . . . . . . B-53

B.19.4.3 VHDL Code for an n-bit Left-to-Right Shift Register. . . .... B-54

B.19.4.4 VHDL Code for a Left-to-Right Shift Register with an Enable Input. B -55

8.19.5 VHDL Code for a 4-bit Parallel Access Shift Register ... . . . . . . . ............ . .. . ... B- 55 B.19.5.1 Using Sequential Statements . . . . . . . . . . . . B - 55

B.19.5.2 Hierarchical Code for a 4-bit Parallel Access Shift Register. . . . . . . . . . . B - 57

8.19.6 8-bit Shift-Left Register with Positive-Edge Clock.

Asynchronous Parallel Load, SeriallN, and Serial OUT . .. . . . . .. . .. . . . . . . . . . . . . . . . B - 60

B.19.7 8-bit Shift-Left Registe:r with Positive-Edge Clock.

Synchronous Parallel Load, Serial IN. and Serial OUT . .. .. .. . .. .. ...... . . ..... ... B - 61

8.19.8 8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock, Serial IN, and Parallel OUT B - 62

B.20 VHDL Code for a Counter ............................................................... B - 62

B.20.1 VHDL Code for a Four-bit Up Counter . . . .. .. .. . .. . ..... • . ...•..•. .. .. • ... .. .. B - 62

8.20.2 VHDL Code for a 4-bit Up Counter using Integer Signals . .. . • . . ... .. •..... •.. • . ... B - 63

B.20.3 VHDL Code for a 4-bit Down Counter ...... . .. .. . . .. . .. .. . . ... .......... .. ... . B - 64

8.20.4 VHDL Code for a 3-bit Asynchronous Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B -65

B.20.5 VHDL Code for Asynchronous Counter with GLITCH . ...... . ..... . .. . .. .. . .. .. .. . 8 - 66

B.20.6 VHDL Code for Synchronous mod-6 Counter . . .. .. . ... . . .... ... ... . .. ...... .. .. B - 67

B.20.7 4-bit Unsigned Up Counter with Asynchronous Load from Primary Input . B- 68

B.20.8 4-bit Unsigned Up Counter with Synchronous Load with a Constant . . . . B - 69

B 21 VHDL Code for State Machines .. ... .. .. . .......................... B - 70

B.21.1 VHDL Code for Mealy-type State Machines .. . .. . . . .. .... .. .. . . . .. . ... . . . . ... . . B - 72


B.21.1.1 VHDL Code ror a Serial Adder. . . . . . . . . . . . . . . . . . . B -74 B.21.2 VHDL Code for Moore-type State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B - 78

B.22 VHDL Code for Guessing Game ... ....... ........... .. ........... ....... ............ B - 80

8.23 VHDL Code for Traffic Light Controller ........................................... B - 85

B.24 More Examples ................................................. .... ........ .................. B - 89

3.25 VHDL Code to Display Hex Key Input on the LCD Display ........... B - 107

B.26 VHDL Code to Display Message on the LCD Display .. ......... ........ B - 114

B.27 VHDL Code to Display Key Input on the LED Display .................. B - 120

B.28 VHDL Code to Display Message on the Multiplexed LED Display B - 122

B.29 VHDL Code for Stepper Motor Interfacing ...... ..... .............. ... ..... ... B - 124

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C.1 Gate Level Modeling .......... ................................................................. C - 1

C.2 Data Flow Modeling ........ ... .......... .................................. ......... ........ .... C - 6

C.3 Behavioral Modeling .... .......................................... ............. ................ C - 7

C.4 Description of D-Latch .... ........ ........... ................... .............................. C - 8

C.5 Description of Flip-Flops ......... ................... ......... ................................ C - 8

C.6 Description of Sequential Circuits ................................ ..................... C - 11

C.6.1 Description of Mealy Circuit .. . .. .. .. . ... ..... ... • .. • .. • .. • .. • .. •. . • . . • . . . ... C - 11

C.6.2 Description of Moore Circuit .. . . . .. . .. . .......... . ..... ... .............. .... . C - 13

C.7 HDL for Registers and Counters ...... ......... ........................................ C - 15

C.7 .1 Descriptions or Registers in Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C - 16

C. 7 .2 !::ascriptions of Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C - 20

C.8 Verilog Code for Generating Waveforms using DAC ........................ C - 25

C.9 Verilog Code for Elevator Controller .................. ................ ............... C - 31


Programming (using VHDL and Verilog) I. Write HDL code to realize all the logic ~ates : Refer Section C. l and listing 2.1

2. Write a HDL program for the following combinational designs. a. 2 to 4 decoder : Refer Section B. l . C.2 and listing 4.12. b. 8 to 3 (encoder without priority and with priority) : Refer Section B.2 and Listing 3.7. c. 8 to I multiplexer : Refer Se.ction B.4, C. I and listing. 2.3, 2.4. d. 4 bit binary to gray converter : Refer Section B. I 5. e. Multiplexer, de-multiplexer, comparator. : Refer Section B.4, B.6. B.12 and Listing 2. 7, 4.20.

3 . Write a HDL code to describe the functions of a Full Adder using three modelling styles. : Refer Section 1.6 and Listing 1.2, 1.3. !.4. 1.5, 1.9 and 1.10.

4. Write a model for ALU. : Refer Section B.8 and Listing C.6.

5 . Develop the HDL code for the following flip-flops, SR, D , JK, T . : Refer Section B.18, C.4. C.S and listing 3.2. 3.3, 3.4, 3.5. 4.16, 4 .18 and 4.19.

6. Design 4-bit binary, BCD counters (Synchronous reset and Asynchronous reset) and "any sequence" counters. : Refer Section B.20, C.6, C.7 and Listing 3.6, 4.24, 4.26, 6.8. 7.8, 7.9.

7. Write HDL code to display messages on the given seven segment display and LCD and accepting Hex key pad input data. : Refer Section B.25, B.26, B.27, B.28.

8. Write HDL code to control speed, direction of Stepper motor. : Refer Section B.29.

9. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using DAC change the frequency and amplitude. : Refer Section C.8.

I 0. Write HDL code to simulate Elevator operations. : Refer Section C.9.

Copyngh1ed f"'ater al

Listing 1.1 : Description of circuil using basic gates .. ... .... .. ...... .. .... .. .... .... ... ..... .. .. .. ..... .. ...... .. 1 - 9

Listing 1.2 : Example of VHDL behoviorol description ... .. .. .. .. . .. .. . .. ... .... .. .. ... ..... .. ... .. ..... .. .. . .. l - 30

Listing 1.3 : Example of Verilog behavioral description .. .... ..... ... ..... .. ... .. . .. .. .. .. ............... .. . .. 1 - 31

l isting ·1 .4 : Exomple of VHDL dote-flow description .. .. .. .... .. .. ..... .. .. .. ...... .. .. .... .. .. .. .. .. .. .. ...... 1 - 3 1

Listing 1.5 : Example of Verilog dole-flow description .. .... ....... .. .. .... .. .... .. .. .... ...... .... ...... .. .. .. 1 - 3 1

Lisling 1.6 : VHDL swilch-level description ....... .... ...... .. .. ... ..... .... ........ .... ..... .... .. .. .... .... ...... ... I - 33

Lisling 1.7: Veri log switch-level description ..... .. . .. .... ..... .... ... .. ... .... ........ ..... ..... .. .. .. ....... .. .. .. 1 - 34

Listing 1.8 : Exomple of VHDL mixed-type descriplion ...... ... .. .... ........ .. .. . .. ... .. .. ..... .. .. .. .. .. .... 1 - 34

Lisling 1 . 9 : Example of Verilog mixed-type descriplion .... ....... .. ......................... .. ..... .. .. ..... 1 - 35

Li sling 1 . 10 : Example of mixed language type descriplion ...... ...... .. .................................... 1 - 35

Listing 2 .1 : HDL code for AND-OR circuit - VHDL and Verilog .... .. .. . .. ........................... .. .. ... 2 - 1

Listing 2 .2 : HDL code for holf-odder-VHDL and Verilog .. .. .. ... .. .. ... .. .. .. .... . . ...... .. .... .. ...... ..... 2 • 6

Listing 2.3 : HDL code of o 2 x 1 mulliplexer • VHDL ond Verilog . ............. .......... .............. .... 2 - 7

Listing 2.4 : HDL code of o 4 x l mvlliplexer - VHDL and Verilog ... .......................... ........... 2 - 10

Lisling 2.5 : HDL code for o 2 x 2 unsigned combinational array multiplier

VHDL and Verilog . ............. .. .. .. .. .... .. .. .. .. .. ....... .. .. ........ ... .... .... .... .... .. ...... ... .. .. 2 • 13

Lisling 2 .6 : HDL code for a D-lolch.VHDL and Veri log . .... .. .. ......... .. ....... .. ...... . .. ... ..... .. .... ... 2 - 15

Lisling 2.7 : HDL code of o 2 x 2 magnitude comparator - VHDL and Verilog .... ........ .. ... .. .. .. 2 - 19

Listing 2 .8 : 4-bit ripple-corry odder case slvdy - VHDL ond Verilog .. .............. .... ..... .......... .. 2 - 20

Listing 2 .9 : 4-bil cony-lookahead odder - VHDL and Verilog . .. ...... .. .. ..... .. ......... .. .. .. ... .... .... 2 - 23

Listing 3 .1 : Example of on HDL behoviorol description- VHDL and Verilog ... .. .. ... .. .. .. ... .... .. ... 3 - 2

Listing 3.2 : VHDL code for behavioral description of D-Lolch using variable - assignment

statements - .. ......... .. .... .. .. ... ....... .. .. .... . .. .... .... ..... .. .... .. .. ... .... .... .... .. ........ .... .. .. 3 - 10

Listing 3.3 : VHDL code for behaviora l description of D-Lotch using signal-assignment

stotemenls .. .. .. .. . .. .. .. . .. .. .. .. .. . .. . .. .. .. .. .. . ... .. .. . .. . . .. .. . .. . .. .. . .. .. . .. . .. .. . .. .. .. .. .. . 3 - 11

Listing 3 .4 : Verilog code for behoviorol description of o D-Lotch .... ..... .... ..... .............. ......... 3 - 11

~~·~twtft~·mfi!m:;nwt~~iih'i&iWli$ii.5W M Gopyngh' !Cl rr 1 rial

Listing 3 .5 : HDL code for o positive edge-triggered JK fl ip-flop using the case

stotement-VHDL end Verilog ...... .. .... ................ ............................... ... ........ ... 3 . 16

Listing 3.6 : HDL code for a 3-bit binary counter using the cose statement .... ..... ..... .. ... .. .... ... 3 . 18

Listing 3. 7 : Verilog description for o 4-bit priority encoder ... ... .. ..... ........... ............. ..... ..... ... 3 • 21

l isting 3.8 : HDL code for colculoting the foctoriol of positive integers-VHDL end Verilog .. .. 3 · 26

listing 3. 9 : 4x4-bit booth algorithm- VHDL and Verilog .......... ...... .. ... .. ... ... ... .. ...... ... ......... 3 - 33

Listing 4 .1 : HDL structurol description- VHDL ond Verilog ..... ...... .. ..... .. ...................... ..... ... . 4 · 2

Listing 4.2 : HDL code of hell adder-VHDL end Veri log ........... .... .... .... .. .... ..... .... .. ..... ..... .. .. 4 · 3

Listing 4.3 : Binding between entity ond architecture ...... .. ............ .... ........... ...... ........... ...... ... 4 • 5

Listing 4.4 : Binding between entity ond component ... ... ... ..... .... ...... .. .. ................. ... ....... ..... .. 4 · 5

listing 4 .5 : Binding between library and module in VHDL. ..... ..... ... ..... .............. ... .. .......... .. .. . 4 • 6

Listing 4 .6 : Binding between o library ond component in VHDL.. ............ ..... ... ..... .............. .... 4 · 7

Listing 4.7 : Binding between two modules in Verilog . ... ... ..... ..... ..... ... ..... ...... ... ..... .. ... .. ..... .. .. 4 • 8

Listing 4 .8: VHDL code for inverter, AND, OR, NOR, NANO XOR gates ...... .... ... .... ........ ... .... 4 . 9

listing 4 .9: HDL description of o 2x1 multiplexer with active low enable . ........................ .... . 4 • 11

Listing 4 .10 : HDL description of o 2x4 decoder with enable input ............. ... .... .. ... ... ....... .... 4 . 14

Listing 4.11 : VHDL behovioro l description of o tri-stote buffer ..... ... ................... .. .. ........ ... ... 4 . 16

Listing 4. 12 : HDl. description of o 2x4 decoder with tri -stote output .............. ... .... ...... .. .... ... 4 • 17

Listing 4.13 : VHDL code for the holf odder . ... ............... ..... ... ....... ........... .. ..... ...... ...... ... .... 4 . 19

Listing 4.14 : HDL description of o lull odder - VHDL ond Verilog .... .. ... .. ........ .... .... ...... .. ... . 4 · 20

Listing 4.1 5 : HDL description of on SR latch with NOR gates ....... ............. ..... ....... ...... ...... .. 4 · 23

listing 4.16: HDL description of o D lotch-VHDL ond Verilog ....... .... ... ... ...... ... .. ........ ... .. 4 - 24

listing 4 .17: HDL description of o SR-Flip-Flop-VHDL ond Verilog ... ......... ..... ... .............. ... .. .4 - 26

l isting 4.18: HDL description of a D flip-flop-VHDl ond Verilog ... ..... ............................. ..... 4 · 28

listing 4.19 : HDL description of JK flip-flop .. ........ ... ....... .................................................. 4 · 29

listing 4.20 : HDL description of o 3-bit comporotor using adders .......... ..... ..... ..... .. ..... ..... .. 4 • 32

listing 4 .Ll : HDL description of SRAM memory cell. ...... ...... ..... .... ........ ..... ... ..... ........ ... ... .. 4 • 34

Listing 4.22 : HDL description for given sequential circuit ........... .. .... ..... ....... .. .... .... .... ..... ... 4 - 46

Listing 4 .23 : HDL description for given sequential circuit using • VHDL and Verilog ........ ..... 4 • 49

Listing 4 .24 : HDL description for 3-bit synchronous binary counter ................... .. ........... ... .. 4 - 52

listing 4 .25 : HDL description of N-bit magnitude comparator using generate statement ..... ... 4 - 56

Listing 4.26 : HDL description of on N -bit asynchronous down counter using generate statement

.... .... .. ...... 4. 58


listing 4.27 : .HDl description of N-bit memory word using genero te .. .. ...... ... ... . ... ..... ..... .. .. .. 4 · 60

listing 4 .28 : HDl descrip""n of N-bit reg ister using · VHDl ond Verilog . . ... ... .. .. ... .. ..... .... .. . 4 · 61

listing 4.29 : HDl description of N-bit left shift register ... ... .. ... ... . ...... ..... ... .. ... . .... .... ....... ... .. 4 · 62

listing 5.1 : HDl description of o full odder using procedure ond tosk-VH Dl ond Verilog .. .. .. 5 - 4

l isting 5.2 : HDl description of on N-bit ripple corry odder using procedure ond tosk-

VHDl ond Verilog ............ ....... ..... . .............. ... .. ..... ... ..... ........ .... ... ..... .. .... ... ..... 5 - 6

listing 5.3 : HDl code for converting on unsigned binary to on integer using procedure ond tosk

...... ........ ..... ..... ...... ............ .. .. .. ....... ... ... ..... ..... .......... ........ ......... ... .. 5 - 8

listing 5.4 : HDl code for converting o fraction binary to reol using procedure ond tosk . .. .. ... 5 - 10

listing 5.5 : VHDl code for converting on unsigned integer to binary using procedure ....... .. .. 5 - 12

listing 5.6 : VHDL code for converting o signed binary to integer using procedure .......... .. .. .. 5 - 14

listing 5.7 : VHDL code for converting on integer to signed binory using procedure . ....... ... .. .. 5 - 15

listing 5.8 : HDl code for signed vector multip lication using procedure ond tosk .................. 5 - 17

listing 5.9 : HDL function to find the greater of two signed numbers .. .. ... .... . ... ... ........ ... .. ... .. 5 · 24

listing 5.10: VHDL function to describe the edge trigger D flip-flop ... .. .. ... .... . .. .... ... ...... .. ..... 5 · 26

listing 5.11 : Verilog function thot calcula tes loctoriol of o number . ............ ..... ... ... .. .... ... .... . 5 · 27

l isting 5.12 : VHDL code for reading ond processing a text file containing integer numbers . .. 5 · 33

listing 5.13 : VHDL code for reading ond processing o text file containing reol numbers .. .... .. 5 · 35

listing 5.14 : VHDL code for reading o string of chorocters into on orroy ...................... ........ 5 - 36

l isting 5 .1 5 : HDl code for writing integer numbers too file . ... .... . .. .... . ... .. ... .. .. .... . ........ ...... . 5 - 37

listing 5.16 : VHDl code for finding the percentage morks for o porticulor student. ... ..... .... ... 5 . 38

listing 5.17: Verilog code for storing y = x + 10 in lodd.txt .... .. ... ... .... ........ .. ... .... ... .... .. ... ... 5 · 40

listing 6.1 : Pockoge declorotion ..... ...... ... .. ... ........... ... ..... .. ............. .... .. .. ...... .. ... ..... ..... ..... . 6 · 2

listing 6.2 : Package body .. ... .. ..... ... .. ...... . .... .. .. .... ... .. .. .. ..... . .... . .... ... . .... .. .. .. .... ... .. .. .... ... ... .. 6 - 3

listing 6.3 : HDl code for finding the largest e lement of on orray .. .... .......... .. ... ... .... .. .. . .. .... ... 6 · 5

listing 6.4 : Multiplication of two signed N-element vectors-VHDL and Verilog . .. .... .. ... ... .. . 6 - 7

listing 6.5: VHDL Description for addition of two (5x 5] matrices. . .. . ... ... . .... ........ ...... .. ... . 6 · 11

listing 6.6 : HDL description of on Al U-VHDL ond Verilog ..... .......... ... .. ..... .... ... .............. .. 6 . 13

listing 6.7: HDL description of 32x 8 SRAM-VHDl ond Verilog . . ....... .. ............. . ..... . ...... . 6. 17

listing 6.8 : HDL code for the sta te machine in figure - VHDL ond Verilag ... ... ... .. ... ..... .. 6 . 20


Listing 7.1 : M ixed-language description of o full odder ... . .... ... ... .. . ... .. ... .. . ... .. .... .. ... .. .... .. .. .. . 7 . 2

listing 7.2 : Mixed-language description of on or gate .. .... . ... .. ..... ... .. .... . .......... . .. .... .. .. ..... .. .. 7. 3

listing 7.3: Mixed-language description of o 12-bit odder ... .... . .. ... .. .... . ... .... .. .. .. . .. .. . ...... .... .. 7 - 4

Listing 7.4 : Mixed-language description of o 4-bit odder with o zero flog .. .... ...... .. .. .. .... .. ... ... 7. 6

Listing 7 .5 : Mixed-language description of o master-slave D fl ip-flop .. .... ... . ... .. ... ... ... .. ... ... ... 7 . 8

Listing 7.6 : Mixed-language description of o 4x4 comparator ... ... .. ... ... . ... ... .. ... .. ... ..... ... .. .. ... 7. 9

Listing 7. 7 : Mixed-language description of o JK flip-flop .. ... .. ... .. ..... ... ... .. ... ... .. ... .. .. .... .. ... .. 7 · 11

Listing 7 .8 : M ixed-language description of 3-bit counter with clear .. ... ... ..... .. ... ... . ......... .. ... 7 • 12

Listing 7.9 : Mixed-language description of on N-bit asynchronous counter .. .... . .. ... ... .. ... .. ... 7 • 15

Listing 8. 1 : VHDL code for entily system 1 .. . ... ... ..... .. ... ..... ... .. ... .. .. . .. ... .... . .. . .. .... . .. . ..... .. .... .... . 8 • 3

Listing 8 .2 : VHDL code for entily system2 .. .... ... ... ..... . .... ... . ... ... ... .. ... ... . ......... .. .. .. ... .... . ... .. . ... 8 · 3

Listing 8.3 : VHDL code for entity system3 ... ..... ... ... ..... ... .. .. . ... .. ..... .... .. . .... .. .. ... .. ... ... .... . ... ... .. 8 • 3

Listing 8.4 : VHDL code for entity system4 ... .... .. .. .. .... .. ... .. ....... . ..... ... ... .. .... . .. ..... .... .. ... .. .. .. .. .. 8 • 4

Listing 8 .5 : VHDL code for entily systems .. . .. ... .... ... .. .. .... .. .. .. ........ ... ..... .. ... .. ... .. . ... .. .. .... ... . ... 8 . 4

listing 8.6 : VHDL code for entily system6 .. . .. .... .. . ... ... .. ...... ... ..... . .... .. ... ... . ... ...... .. .. ... .... .... ... 8 • 4

Listing 8.7 : VHDL code for entity system? ... ... .. .. ..... . .. .... ..... .. .... . ... .. .. .. .. .. ... ... . ..... ... ... .. .... ... .. 8 · 5

Listing 8. 8 : VHDL code for entity ALU ..... .... . ... ... . ... .. .. . .. .... . .. . ..... .. ..... . ...... ... .. .. .. .... . ... ..... .. . . 8 · 5

listing 8. 9 : VHDL code for entity orroy 1 . .. .. .. . .... .. .. .. .. . ... .. ... ...... ... . .... .. ... .. ... ... .. ........ ... .. .. . ... 8 · 6

listing 8. 10 : VHDL code for entity weekly activity .. ... ..... ... ... .. ... .. ... . .... . ...... ..... ... .......... . ... .... 8 · 7

Listing 8. 11 : VHDL code for entity seguentiol circuit . .... .. ... .. .. ... ...... ... .. .. ... .. .... . .... . .. ...... ... ... . 8 · 9

Listing 8 .12 : Verilog code for module system 1 .... .. .. . ... .. . .... . .. ... .. .. . .. ... .. ... . ...... .. ... ... .. ... ... ... . 8 · 9

Listing 8 .13 : Verilog code for module system2 ..... . ......... ... ..... .. ... .. ... ... . .... ... ... ... ... ............. 8 • l 0

Listing 8 .14 : Verilog code for module system3 ..... . .. . .... . ......... ... . ... ... ... .. ..... .. ... .. ...... .. ... ... .. 8 • 10

Listing 8.15 : Verilog code for module orroy 1 .... .. .. ..... . .... . ... ... ... . ... .. ... .. .... . .. .... . .... .. .. .. ... .. .. 8 · 11

listing 8. 16 : VHDL code for o signal-assignment statement, 6 = A .. . .... . ... .. .. .... .. .... . .... .... . .. 8 · 11

Listing 8 .17 : VHDL code for o signal-assignment statement, 6 = 3 • A + 4 ...... ... . .... .. ... .... .. 8 · 13

Listing 8 .1 8 : Struclurol Veri log code for the logic diagram in Fig. 8 .1 5 (b) . ... .. .... . .... .. .. .. ..... 8 · 14

Listing 8 .19 : VHDL voriobie-ossignment statement . ... ... .... ... .. .. . .. ... .. ... .. ... .. ... ... .. ... .... . .... ... .. 8 · 15

Listing 8 .20 : Mopping logical operators In HDL .. .. ... ........ ..... ..... ... .. ............... .. .. . .. . , .. ... ..... 8 • 17

Listing 8.21 : Example of if-else statement... .. ... ... . .... .. ...... .. ... .. .. .... . ..... ... .... . ... ... .. .. ... .. .. ..... 8 • 19

Listing 8 .22 : Example of if-else statement ...... .. .. .... ... .. ... .. ....... ... . .. ... .. .. ..... ..... .. .... .... .. ..... .. 8 • 19

Listing 8 .23 : Example of comparison using if-else sta tement .. ........ .. ..... ... ..... ... ... .. .. ... . .... ... 8 • 20


Listing 8.24 : Example of elseil and else-ii. ...... ..... ...... .. .. . ... ... ... ..... ... ..... .... ............ ........ ..... 8 · 22

Listing 8.25 : Example al ii statement with storage .......................... .. .. .......... .. .... .............. .. 8 • 24

Listing 8.26 : Else-ii statement with gate-level logic ... .... .... .. ..... ..... .. ... ..... ..... ..... . .. .. .. ... .. ..... 8 · 26

Listing 8.27 : Example of case mopping ...... ... .. .. ................ ...... .... ..... ....... ..... ..... .. ..... ..... ... 8 • 31

Listing 8.28 : Example of case mopping ............ ...... . .. .... .. ... ... ........ ..... ..... .... .... ....... ......... . 8 · 32

Listing 8.29 : Verila"g cosex .... ..... ... ..... ........ ........ ...... ... ... ........ .. ..... ... ..... .......... ..... ... ... .... .. 8 • 32

listing 8.30 : Example of case with storage ... ..... ... ... . .. ................ ... ...... .... ..... ...... ... ........ .. .. 8 • 34

Listing 8.31 : A for-loop statement. . ... ....... ..... ... .. ........... ....... .... ..... ..... .......... ........ ...... .... 8 · 37

Listing 8.32 : A Veri log example of task .... ... ........ .. .. .. .. .... .... ... ... .. .. ....... ............ .... .. ........... 8 • 38

Listing 8.33 : Verilog example of a lundion ....... ... .. ....... .. . .. ... ................... ........ ... .. ............ 8 • 40

Listing 8.34 : Example of function synthesis ...... .. .. ... ........ .. ... .. .. .... .... .. .. .. .. ... .. ..... .... .. ... ...... . 8 · 40


Introduction

1.1 Why HDL?

We are familiar with the design of a digital system. The basic steps involved in this process are,

a. Specify the desired behaviour of the circuit.

b. Synthesize the circuit.

c. Implement the circuit.

d. Test the circuit to check whether the desired specifications meet.

But as the size and complexity of digital systems increase, they can not be designed manually; their design becomes highly complex. At their most detailed level, they may consists of millions of elements, i.e. transistors or logic gates. So Computer Aided Design (CAD) tools are used in the design of such systems. One such a tool is a Hardware Description Language (HDL).

HDL describes the hardware of digital systems. This description is in textual form. The Boolean expressions, logic diagrams and digital circuits (simple and complex) can be represented using HDL.

• The HDL provides the digital designer with a means of describing a digital system at a wide range of levels of abstraction and at the same time, provides access to computer-aided design tools to aid in the design process at these levels.

• The HDL, represents digital systems in the form of documentation which can be understood by human as well as computers.

• It allows hardware designers to express their design with behavioral constructs. An abstract representation helps the designer explore architectural alternatives through simulations and to detect design bottlenecks before detailed design begins.

• The HDL makes it easy to exchange the ideas between the designers.

(1 - 1)


Fundamentals of HDL 1 - 2 Introduction

• It resembles a programming language, but the orientation of the HDL is specifically towards describing hardware structures and behavior. The storage, retrieval and processing of programs written using HDL can be performed easily and efficiently.

• HDLs are used to describe hardware for the purpose of simuJation, modelling, testing, design and documentation.

1.2 A Brief History of HDL

The most prominent modern HDLs in industry are Verilog and VHDL. Verilog is one of the two major Hardware Description Languages (HDLs) used by hardware designers in industry and academia. Of course, VHDL is the other one. The industry is currently split on which is better. Many feel that Verilog is easier to learn and use than VHDL. Verilog is very C-like and liked by electrical and computer engineers as most learn the C language in college. VHDL is very Ada-like and most engineers have no experience with Ada. Let us take an overview of the brief history of both the languages.

1.2.1 A Brief History of VHDL VHDL is an acronym for "VHSIC Hardware Description Language" while VHSIC

is an acronym for "Very High Speed Integrated Circuits". VHDL is a hardware description language that can be used to model a digital system at many levels of abstraction, ranging from the algorithmic level to the gate level.

In 1981, in United States many companies were involved in designing the VHSIC chips for Department of Defence. At that time, most of the companies were using different hardware description languages to describe and develop their integrated circuits. As a result, different vendors could not effectively exchange designs with one another. Thus a need for standardized hardware description language for the designs, documentation, and verification of the digital systems was generated. A team of three companies, IBM, Texas instruments, and Intermetrics developed first version of VHDL. To make this language an industry wide standard, the language transferred to IEEE for standardization in 1986.

The standardization of VHDL began in February 1986 with adaptation of the VHDL version 7.2. In 1987, the IEEE completed their mission and added several enhancements to the language. These efforts introduced the IEEE Standard 1076-1987 version of VHDL, which was also recognized by American National Standards Institute (ANSI). In 1993, some more features are added to VHDL to give the updated version IEEE Standard 1076-1993. Later on many packages, for example, std_logic_l164 are added with the addition of several logic levels to the existing two logic levels.


Fundamentals of HDL 1 . 3 Introduction

1.2.2 A Brief History of Verilog HDL

Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems, Inc's Systems Division. Until May, 1990, with the formation of Open Verilog International (OVI), Verilog HDL was a proprietary language of Cadence. It is the top HDL used by over 10,000 designers at such hardware vendors as Sun Microsystems, Apple Computer and Motorola. Industrial designers like Verilog. It provides the d igital designer with a means of describing a digital system at a wide range of levels of abstraction, and at the same time, provides access to computer-aided design tools to aid in the design process at these levels. Jt allows hardware designers to express their design with behavioral constructs, deterring the details of implementation to a latter stage of design in the design. An abstract representation helps the designer to explore architectural alternatives through simulations and to detect design bottlenecks before detailed design begins.

Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i.e. gate and switch levels) leading to Very Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use of HDLs is the simulation of designs before the designer must commit to fabrication.

1.3 Structure of the HDL Module

HDL contains the features of conventional programming languages such as Pascal or C, logic description languages such as ABEL-HDL, an~. netlist languages such as EDlF. The HDL module follows the general structure of software languages such as C It has a source code that is written in high-level language style using text editors provided by the HDL package, or it can be written using external text editors and imported to the HDL package by copy and paste.

Verilog HDL, simply referred to as Verilog has different structure than the VHDL. Let us discuss the structure of both the HDLs.

1.3.1 Structure of the VHDL Module The main components of a VHDL description consists of following kinds of

declarations :

• Package (optional)

• Entity

• Architecture

• Configuration (optional)

The Fig. 1.1 shows the relationship of these basic blocks of VHDL program. A design may include any number of package, entity, architecture and configuration


Fundamentals of HDL 1 • 4 Introduction

declarations. It is important to note that the entity and archit~ture blocks are compulsorily required; however, the package and configuration blocks are optional.

Package

Configuration

Fig. 1.1 Relationship of VHDL design units

1.3.1.1 Package

There are some declarations which are common across many design units. A package is a convenient mechanism to store and share such declarations. It is an optional design unit. A set of declarations contained in a package declaration may be shared by many design units. It defines items that can be made visible to other design units. A package is represented by :

• Package declaration

• Package body (optional)

Package declaration

It defines the interface to the package. The syntax of a package declaration is given below.

PACKAGE package_name IS

type declarations

subtype declarations

constant declarations

signal declarations

variable declarations

subprogram declarations

file declarations

alise declarations

component declarations

attribute declarations


Fundamentals of HDL

attribute specifications

disconnection specifications

use clauses

END package_name;

1 • 5 Introduction

The items declared in a package declaration can be accessed by other design units by. using the 'library' and 'use' clauses. This is explained in the further section. The example of package declaration is given below.

package MUX 4-to-l_package is

component MUX 4-to-1

pon (MO, Ml, M2, M3

s

f

and component;

and MUX 4-to-l_package;

IN STD _LOGIC;

IN STD_LOGIC_VECTOR (1downto 0)

OUT STD_LOGIC;

Fig. 1.2 Package declaration for 4-to-1 multiplexer

Package body

It contains the details of a package, that is the behavior of the subprograms and the values of the deferred constants which are declared in a package declaration. The package body may contain other declarations. The syntax of it is as given below.

package body package_ name is

subprogram bodies

complete constant declarations

subprogram declarations

type and subtype declarations

file and alias declarations

use clauses

and package_name;

The name of the package must be same as the name of its corresponding package declaration. If the package declaration does not have any subprogram or deferred constant declarations, a package body is not necessary.

1.3.1.2 Entity

It gives the specification of input/ output signals to external circuitry. An entity is modelled using an entity de<;laration and atleast one architecture body. An entity X, when used in another entity Y, becomes a component for the entity Y. Entity gives interfacing between device and the other peripherals. An entity usually has one or more ports, which are analogous to the pins on a schematic symbol. All information



must flow into and out of the entity through the ports. Each port must contain name, data flow direction and type.

The syntax of a VHDL entity declaration is as shown below. entity entity_name is

port ( signal_names : mode signal_type;

signal_names: mode signal_ type;

signal_names : mode signal_ type);

end entity_ name ;

The following section describes the different elements of entity declaration.

entity_name

signal_names

mode

in

out

inout

buffer

It is an identifier selected by the user to name the entity.

It is a List of user selected identifiers to name external interface signals.

The ports can be declared in four types which specify the signal direction.

This mode is used for a signal that is an input to an entity (value is read not written).

It is used for a signal that is an output from an entity. The value of such a signal can not be read inside the entity's architecture. But it can be read by other entities those use it.

It is used for a signal that is both, an input to an entity and an output from the entity.

The signal is an output from the entity and its value can also be read inside the entity's architecture.

slgnal_type : It is a built-in or user defined signal type.

For example, there is a system having its inputs and outputs like rd, wr, ADD, x, y, z, ad, al. The entity for this can be written as shown below.

entity gate_logic is

port (

wr : in std_logic;

rd : In std _logic;

ad : inout std_logic_vector (7 downto 0);

ADD : in std_logic_vector (0 to 3);

x,y,z : out std_logic;



al : buffer std_logic_vector (7 downto 0)

);

end gate_logic ;

Here rd, wr are inputs to the system so they are input ports. The ad is also input signal but it is 8 bit so it is defined as vector (7 downto 0). It means 7 is assigned to MSB of your signal and 0 is assigned to LSB of your signal. Similarly x, y, z are output signals so they are defined as output ports. The al is coming out and is defined as buffer signal, so that you can also read this signal.

1.3.1.3 Architecture

Architecture specifies behavior, functionality, interconnections or relationship between inputs and outputs. It is the actual description of the design. An architecture consists of two portions : architecture declaration and architecture body. An architecture body specifies the internal details of an entity.

• As a set of concurrent assignment statements (to represent dataflow)

• As a set of interconnected components (to represent structure)

• As a set of sequential assignment statement (to represent behavior)

• As any combination of above three.

The syntax for architecture is given below

architecture architecture_ name of entity_ name is

Declarations

begin

concurrent statements;

sequential statements;

end architecture_name;

To design any system, first we have to write the entity. In the architecture, we write architecture_name for that entity. In declaration part, types, signals, constants, function definitions, procedure definitions, component definitions etc. can be declared. The variables can also be declared here. VHDL variables are similar to signals, except that they usually do not have physical significance in a circuit. A variable declaration is similar to a signal declaration, except that the 'variable' keyword is used as shown below.

variable variable_names : variables_type;


Fundamentals of HDL

Example:

1. 8

architecture gate of or _gate Is begin

Architecture process (a,b) begin

1.3.1.4 Configuration

Process statement if a = 'O' and b = 'O' then

c< = ·o·: else

Sequential --+--+---t statements

c < = '1'; end if:

end process;

end gate;

Introduction

Configuration declarations may be used to associate particular design entities to component instances (unique references to lower-level components) in a hierarchical design, or to associate a particular architecture to an entity. As their name implies, configuration declarations are used to provide configuration management and project organization for a large design.

Important points to remember while representing any module us!ng VHDL

1. Each statement in VHDL is terminated with a semicolon (;).

2. The language is case insensitive. Le. the uppercase and lowercase letters are considered as same.

3. The name should start with an alphabet letter and can include the special char::.crer underscore LJ.

4. The name of the ports must be followed by a colon (:).

5. The architecture body starts with the predefined word begin, followed by statements that detail the relationship between the outputs and inputs.

6. The comment should begin with two hyphens (--).

7. Leaving the blank spaces between two words or at the beginning of the line are allowed.

8. Leaving the blank line(s) is allowed in the module.



1.3.2 Structure of the Verilog Module

The Verilog HDL describes a digital system as a set of modules. Each of these modules has an interface to other modules to describe how they are interconnected. Each module consists of a declaration and a body. In the declaration, name, inputs and outputs of the module are listed. The body shows the relationship between the inputs and the outputs. Usually, we place one module per file but that is not a requirement. The mod ules may run concurrently, but usually we have one top level module which specifies a closed system containing both test data . and hardware models.

A module is a basic building block of Verilog HDL. Modules can represent pieces of hardware ranging from simple gate to complete systems. e.g. a microprocessor. The struture of module is,

module <mod ule name> <port list>;

< declares>

< module items>

endmodule

The <module name> is an identifier that uniquely names the module. The module name is user selected . It should start with alphabetical letter and it can include the special character underscore (j. In contrast to VHDL, Verilog is a case sensitive. The <port list> is a list of input, inout and output ports which are used to connect to other modules. The <declares> section specifies data objects as registers, memories and wires as wells as procedural constructs such as functions and tasks.

The Listing. 1.1 shows the example Verilog code. This code is the description for the logic circuit shown in the Fig. 1.3.

.... Listing 1.1: Description of circuit using basic gates module BG_circuit (P, Q , R, Y);

input P, Q, R;

output Y;

wires, t;

assign s = -P;

assign t = s & O;

assign Y = t I R;

endmodule

Fig. 1.3 Circuit using basic gates


Fundamentals of HDL 1 -10 Introduction

1n contrast to VHDL, in Verilog, input and output port signal types are implicitly declared. We can declare more than one input or output on the same line using a comma (,) to separate each input as shown in the Listing 1.1.

Important points to remember while representing any module using Verilog HDL.

1. Each statement in Verilog HDL except comment and last statement (endmodule) is terminated with a semicolon (;).

2. The blank lines are allowed in the module and also spaces between the words or at the begi1ming of the line are allowed.

3. The language is case sensitive. i.!?. the uppercase and lowercase letters are considered as different.

4. The function of a circuit is indicated by the text between two slashes (I/) and the end of the line which is interpreted as a comment.

5. Verilog uses about 100 keywords. All must be given in lowercase.

6. Identifiers are the names given to variables. With these names, they can be referred in the design. They consist of alphanumeric characters and underscore (-). They can not start with a number.

7. The input and output keywords are used for declaring inputs and outputs. The keyword inout is used for a signal that is both, an input and an output.

8. Internal connections within the circuit are declared with the keyword wire.

Note : The ke}"vords are highlighted by printing them in bold. But it is not the requirement of Verilog HDL.

1.4 Operators

HDL has an extensive list of operators to perform a wide variety of functions. Let U $ :.ee the operators in VHDL and Verilog HDL.

1.4.1 Operators in VHDL

VHDL includes the following kinds of operators :

• Logical

• Relational

• Arithmetic

• Shift and Rotate



1.4.1.1 Logical Operators

Logical operators, when combined with signals and/or variables, are used to create combinational logic. VHDL provides the logical operators as shown in the Table 1.1.

Operator Equivalent Logic Operand Type Result Type

AND =V- Bit Bit

OR =C>- Bit Bit

NANO =D- Bit Bit

NOR =D- Bit Bit

XOR =lD-- Bit Bit

XNOR =)[>-- Bit Bit

NOT -I>-- Bit Bit

Table 1.1 VHDL logical operators These operators are defined for the types bit:' std_logic and Boolean, and for

one-dimensi011al arrays of these types (for example, an array of type bit_vector or std_logic_ vector).

The effects of the logical operators are defined in the follow ing tables. The symbol T represents TRUE for type BOOLEAN, '1' for type BIT; the symbol F represents FALSE for type BOOLEAN, 'O' for type BIT.



A B A and B A B A or B A B A xor B

T T T T T T T T F

T F F T F T T F T

F T F F T T F T T

F F F F F F F F F

A B Anand B A B A nor B A not A

T T F T T F T F

T F T T F F F T

F T T F T F

F F T F F T

1.4.1.2 Relational Operators

Relational operators are used to create equality or magnitude comparison functions. VHDL provides the relational operators as shown in the Table 1.2.

Operator Description Operand Type Result Type

= Equality Any type Boolean

I= Inequality Any type Boolean

< Less than Scalar or discrete array type Boolean

<= Less than or equal Scalar or discrete array type Boolean

> Greater than Scalar or discrete array type Boolean

>= Greater than or equal Scalar or discrete array type Boolean

Table 1.2 The following statement demonstrates the use of some of the above relational

operators : if (A/= B) then ...

A is compared to B. If A is equal to B, then the value of the expression (A/= B) is false (O}; otherwise it is true (1 ).

if (A> B) then ...

If A is greater than B, the value of the expression (A > B) is true (1); otherwise it is false (0).

Note : The operands of each relational operator must be of the same type. The result type of each relational operator is the predefined type Boolean.



1.4.1.3 Arithmetic Operators

Arithmetic operators are used to create arithmetic functions. Arithmetic operators provided by VHDL are listed in Table 1.3.

Operator Operation Operands (A or Result Type B) Type

Addition A numeric numeric +

A+B B numeric

Subtraction A numeric numeric -

A-B B numeric

. Multiplication A integer or real Same as A

AxB B integer or real

. Multiplication A physical Same as A

A x B B integer or real

. Multiplication A integer or real Same as B

A x B B physical

I Division A integer or real

Same as A A + B B integer or real

Division A integer or real Same as B I

A + B B physical

I Division A physical

Same as A A + B B integer or real

Modulus A only integer integer mod

A mod B B only integer

Remainder A only integer integer rem

A rem B B only integer

Absolute A numeric positive numeric abs

abs (A)

Concatenation A numeric or

& (A & B) array Same as A

B numeric or array

.. Exponent A real or integer Same as A A•• B B only integer

Table 1.3 Arithmetic operators in VHDL



1.4.1.4 Shift and Rotate Operators

These operators shift or rotate the bits of the operand right or left by some specified number of bit positions. There are two types of shift operators : Logic shift operator and arithmetic shift operator. When logical shift operator is used, the vacant positions created due to shift operation are filled with zeros. On the other hand, when arithmetic right shift operator is used the vacant positions created due to shift operation are filled with MSB (sign bit). The arithmetic left shift is same as the logical left shift.

The Table 1.4 shows the shift and rotate operators supported in VHDL. To understand the function of these operators, assume that operand A is the 4-bit vector with value 1101.

Operator Operation Description Operand A Operand A after before operation operation

sll A sll 1 Shift A one position left 1 1 0 1 1 0 1 0 logical

Sil A sll 2 Shift A two positions left 1 1 0 1 0 1 0 0 logical

srl A Sri 1 Shift A one position 1 1 0 1 0 1 1 0 right logical

srl A Sri 2 Shift A two positions 1 1 0 1 0 0 1 1 right logical

sla A sla 1 Shift A one position left 1 1 0 1 1 0 1 0 arithmetic

sra A sra 1 Shift A one position 1 1 0 1 1 1 1 0 right arithmetic

rol A rol 1 Rotate A one posttion 1 1 0 1 1 0 1 1 left

ror A ror 1 Rotate A one position 1 1 0 1 1 1 1 0 right

Table 1.4 Shift and rotate operators in VHDL Note:

• Shift left by 1 bit performs multiplication by two while shift right by 1 bit performs division by two.

• With rotate operation we can restore the original contents after one complete cyclic rotation. This is not the case with shift operation.

1.4.1 .5 Operator Precedence

The precedence of operators is shown in Table 1.5. The operators belongs to same row have the same precedence level. Operators are listed in order of decreasing precedence.



Type Operators

Miscellaneous operators -. abs not (Highest precedence)

Multiplying operators . I mod rem

Sign + -Adding operators + - &

Relational operators = I= < <= > >=

Logical operators and or nand nor xor xnor (Lowest precedence)

Table 1.5

Operators of higher precedence are associated with their operands before operators of lower precedence. For a sequence of operators wi~ the same precedence level, the operators are associated with their operands in textual order, from left to right. The precedence of an operator is fixed and may not be changed by the user, but parentheses can be used to control the association of operators and operands.

1.4.2 Operators in Verilog HDL

Verilog HDL includes following kinds of operators :

• Boolean Logical

• Unary Reduction Logical

• Bitwise logical

• Relational

• Binary Arithmetic

• Unary Arithmetic

• Other

1.4.2.1 Boolean Logical Operators

Logical operators operate on logical operands and return a logical value, i.e., TRUE(!) or FALSE(O). Used typically in if and while statements. Do not confuse logical operators with the bitwise Boolean operators. For example, 1 is a logical NOT and - is a bitwise NOT. The first negates, e.g. !(5 == 6) is TRUE. The second complements the bits, e.g. -{l,0,1,1) is 0100.

Operator Name

! Logical negation

&& Logical AND

11 Logical OR


Fundamentals of HDL. 1 -16 Introduction

1.4.2.2 Unary Reduction Logical Operators

Unary reduction operators operate on a single operand. They produce a single bit result from applying the operator to all of the bits of the operand. For example, in statement B =&A, if A. = 1101, then B = (1 & 1 & 0 & 1) = 0.

Operator Name

& ANO reduction

I OR reduction

• XOR reduction

-& NANO reduction

-1 NOR reduction

-· XNOR reduction

1.4.2.3 Bitwise Logical Operators

Bitwise operators operate on the bits of the operand or operands. The result of A & B is the AND of each corresponding bit of A with B. For example, if A = 1011 and B = 0101, then C= A & B gives C = 0001. Except for bitwise .negation, these operators operate on a two operands.

Operator Operation

- Bitwise negation

& Bitwise ANO

I Bitwise OR

• Bitwise XOR

-& Bitwise NANO

- 1 Bitwise NOR

_11. or"'- Equivalence bitwise NOT XOR

1.4.2.4 Relational Operators

Relational operators compare two operands and return a logical value, i.e. TRUE(l) or FALSE(O). For example, if A = 0100 and B = 0100, then statement if (A== B) results True(l). If any bit is unknown, the relation is ambiguous and the result is unknown(X).



Operator Operation

> Greater than

>= Greater than or equal

< Less than

<= Less than or equal

-- Logical equality

!= Logical inequality

1.4.2.5 Binary Arithmetic Operators

Binary arithmetic operators operate on two operands. Register and net, i.e. wire, operands are treated as unsigned. However, real and integer operands may be signed. U any bit of an operand is unknown ('x') then the result is unknown.

Operator Operation Comments

+ Add ition

- Subtraction

. Multiplication

I Division Divide by zero produces an x. i.e. unknown.

% Modulus

1.4.2.6 Unary Arithmetic Operators

Operator Operation Comments

- Unary minus Changes sign of its operand.

1.4.2. 7 Other Operators

The conditional operator operates much like in the language C.

Operator Operatio n Comm ents

--- Case equality The bitwise comparison includes comparison of x and z values. All bits must match for equality. Returns TRUE or FALSE.

!== Case inequality The bitwise comparison includes comparison of x and z values. Ally bit difference produces inequality. Returns TRUE or FALSE.

{ ' } Concatenation joins bits together with 2 or more comma-separated expressions. e.g. (A{O], 0(1 :7]} concatenates the zero bit of A to bits 1 to 7 of B.


• Fundamentals of HDL 1 -18 Introduction

<< Shift left Vacated bit positions are filled with zeros, e.g. A = A < 2; //shifts A two bits to left with zero fill.

» Shift right Vacated bit positions are filled with zeros.

?: Conditional Assigns one of two values depending on the conditional expression

e.g. A = C>D ? B+3 : B-2 means if C greater than D, the value of A is B+3 otherwise B - 2.

1.4.2.8 Operator Precedence

The precedence of operators is shown in Table 1.6. The top of the table is the highest precedence and the bottom is the lowest. Operators on the same line have the same precedence and associate left to right in an expression. Parentheses can be used to change the precedence or clarify the situation. We strongly urge you to use parentheses to improve readability.

Type Operators

Unary operators ! & -& I - I ' _, + - (Highest precedence)

Multiplying operators .. I o/o

Sign operators + -

Relational operators << >>

< <= > >=

== != === -==

Logical operators & -& • -· I - I

&&

II

Conditional operators ?: (Lowest precedence)

Table 1.6 Operator precedence in Verilog HDL

1.5 Data Types

To match the need for the hardware, the HDL supports variety of data types. For example, if we are describing a signal, we need to specify its type (i.e. the values that the signal can take), such as type bit, which means that the signal can have values either 0 or 1; or type std_logic, in which the signal can have eight values that include 0, 1 and high impedance.

In this section, we discuss the data types supported by VHDL and Verilog HDL.



1.5.1 VHDL Data Types

VHDL supports a variety of data types. The type of a variable, signal, or constant determines the operators that are predefined for that object as well as the range of values that it can take on. The VHDL data types can be broadly classified into following five data types :

• Scalar types : The scalar types include numeric data types and enumerated data types. The numeric types consist of integer, floating point (real) and physical types. Bit, Boolean and character are all enumerated types.

• Composite types : Array and record types are composite da ta types. The values of these types are collection of their elements.

• Access types : They are pointers; they provide access to objects of a given data type.

• File type : They provide access to object tha t contain a sequence of values of a given type.

• Other types : They include the data types provided by the several external libraries.

1.5.1 .1 Scalar Types

We have seen that, the scalar types consist of enumeration types, integer types, physical types, and floating point types. Enumeration, data types and integer types are called discrete types. On the other hand, in teger types, floating point types and physical types are called numeric types.

Integer type

As the name indicates, it covers all integer values, the values can be positive or negative. The default range of Integer is -2147483647 to +2147483647. However, user can specify a shorter range by using the pre-defined word range. The shorter range may require less bits to represent the number when binary encoded. We can define the subtype of base type whose range must be wholly contained within the bounds of the range of base type.

Examples:

type num is integer;

type long is range -32768 to 32768; -- 16 bit b inary encoding.

type short is range 0 to 255; -- 8 bit binary encoding.

sub type shorter is short range 0 to 31; -- 5 bit binary encod ing.

sub type shortest is short range 0 to 15; -- 4 bit binary encoding.



Note : The encoding of integers in a binary format means that all ranges are rounded up to the nearest power of two. This means that if shorter had been declared as:

subtype shorter is short range 0 to 15;

Then the object is synthesized into 4 wires. Objects declared type of type integer without a range constraint will be synthesized into 32 wires.

Real (floating point) type

Floating point type definition defines both a type and subtype of that types. The default range of floating point is -1E38 to + IE38. Like integer type, here also we can specify the shorter range by using the predefined word range.

Examples :

type Real_ data is real;

type Voltage is range to -12.0 to + 12.0;

Subtype min voltage is range - 5.0 to +5.0;

Enumerated types

Bit, Boolean, Character and severity_level are the enumerated types. These are defined in a library such as std or ieee.

Bit data type allows only two values 0 or 1. It is used to describe a signal that takes only l(High) or O(Low). The type Boolean has two values, True(l) or False(O). Both True and False are predefined words.

The type character constitutes the 128 characters of the ASCII character set. These character values are called character literals and are always written between two single quotes (' '). For example, 'A', '_', ' 3 ' and so on.

An object with type severity can take one of four values : note, warning, error or failure. This type is typically used in assertion statements.

Copynqhted material


Examples :

type Bit is ('O', '1');

type Switch _level is ( 'O', ' 1 ', 'x');

Physical type

Values of a physical type represent measurements of some quantity. Any value of a physical type is an integral multiple of the base unit of measurement for that type. For example, time (e.g. second, millisecond, microsecond, etc.) and voltage (e.g., volt, millivolt, microvolt, etc.)

A physical type definition defines both a type and a subtype of that type. Each unit declaration (either the base unit declaration or a secondary unit declaration) defines a unit name. Unit name declared in secondary unit declaration must be directly or indirectly defined in terms of integral multiples of the base unit of the type declaration in which they appear.

Examples :

type time is range -1E18 to 1E18

units

fs; -- femtosecond

ps = 1000 fs; •• picosecond

ns = 1000 ps; ·· nanosecond

us = 1000 ns; -- microsecond

ms= 1000 us; -- millisecond

sec 1000 ms; -- second

min = 60 sec; -- minute

end units;

type distance is range 0 to 1E16

units

-- base unit :

A' ' -- angstrom

-- metric lengths; nm 10A; ··nanometer

um = 1000 run; •• micrometer (or micron)

mm = 1000 um; -- millimeter cm= 10 mm; -- centimeter

Copynqhted material

Fundamentals of HDL

m = 1000 mm;

km= 1000 m;

-- English lengths :

mil= 254000 A;

inch = 1000 mil;

ft = 12 inch;

yd= 3 ft;

fin = 6 ft;

mi= 5280 ft;

lg = 3 mi;

end units;

1 - 22

-·meter

··kilometer

.. mil

-- inch

··foot

·· yard

··fathom

-- mile

·· league

x : distance; y : time; z : integer:

x := SA + 13 ft - 27 inch; ··arithmetic operations

y := 3ns + 5 min;

z := ns/ps;

x := z* mi;

y := y/10;

· · on physical data type

Introduction

The arithmetic operations are predefined for all physical types. It is an error if the execution of such an operation cannot deliver the correct result (that is, if the value corresponding to the mathematical result is not a value of the physical type).

User-defined types

The user can define a type by using the predefined word type.

Example :

type Multi_leveUogic is (low, high, rising, falling);

type arith_op is (add, sub, mul, div);

Here, multi_level_logic and arith_op are the user defined types. The variables declared using such data types can take values mentioned in the data type definition. For example,

Variable operation : arith_op := sub;

Variable level : Multi_level_logic := high;

1.5.1.2 Composite Types

Composite types are used to define collection of values. These include both arrays of values (collection of values of a single type) and records of values (collection of values of the same or different types).



An object of a composite type represents a collection of objects, one for each element of the composite object. A composite type may only contain elements that are of scalar, composite, or access types; elements of file types are not allowed in a composite type. Thus, an object of a composite type ultimately represents a collection of objects of scalar or access types, one for each non-composite subelement of the composite object.

Array types

An array object is a composite object consisting of elements that have the same subtype. The name for an element of an array uses one or more index values belonging to specified discrete types. The value of an array object is a composite value consisting of the values of its elements.

An array object is characterized by the number of indices (the dimensionality of the array), the type, position and range of each index and the type and possible constraints of the elements. The order of the indices is significant.

A one-dimensional array has a distinct element for each possible index value. A multidimensional array has a distinct element for each possible sequence of index values that can be formed by selecting one value for each index (in the given order). The possible values for a given index are all the values that belong to the corresponding range; this range of values is called the index range.

Example:

type num is integer ;

type numarr is array (7 downto 0) of num;

-- numarr is an array of 8 integer numbers

type my_ word is array (0 to 31) of BIT;

-- a memory word type with an ascending range

type data_in is array (7 downto 0) of five_level_logic;

-- an input port type with a descending range

-- Example of unconstrained array declarations

type memory is array (integer range <>) of my_ word;

-- a memory array type



string and bit_vector are the predefined array types, which are defined in package std.

The values of the predefined type string are one-dimensional arrays of the predefined type character, indexed by values of the predefined subtype positive;

subtype pos!tive is integer range 1 to integerhigh;

type string is array (positive range <>) of character;

The values of the predefined type bit_vector are one-dimensional arrays of the predefined type BIT, indexed by values of the predefined subtype natural:

subtype natural is integer range 0 to integerhigh;

type bit_ vector is array (natural range <>) of bit;

Record type

A reco•d type is a composite type, objects of which consist of named elements. The value of a record object is a composite value consisting of the values of its ~iements. The record type is analogous to the record datatype in pascal and the struct decl:uation in C.

A record type definition creates a record types; it consists of the element declarations, in the order in which they appear in the type definition.

Example :

type DATE is

record DAY : INTEGER range 1 to 31

MONTH : MONTH_NAME;

YEAR : INTEGER range 0 to 4000;

end record;

Copynght8d maten:il


1.5.1.3 Access Types

Values belonging to an access type are pointers to a dynamically allocated object of some other type. These are similar to pointers in pascal or C languages.

Example:

type ptr is access date;

ptr is an access type w hose values are

-- addresses that point to object of type date.

1.5.1.4 Fi le Type

File types are used to define objects representing files in the host system environment. The value of a file object is the sequence of values contained in the host system file.

type_file _type_name Is file of type_name;

The type mark in a file type definition defines the subtype of the values contained in the file. The type mark may denote either a constrained or an unconstrained subtype. The base type of this subtype must not be a fi le type or an access type. If the base type is a composite type, it must not contain a subelement of an access type. If the base type is an array type, it must be a one-dimensional array type.

Examples :

file of string -- Defines a file type that can contain

-- an indefinite number of strings

file of natural ·• Defines a file type that can contain

-· only non-negative integer values

Three operations are provided for objects of a file type. Given the following file type declaration :

type FT is file of TM :

Where type mark TM denotes a scalar type, a record type, or a constrained array subtype, the following operations are implicitly declared immediately following the file type declaration :

procedure read (F : in FT; value : out TM);

proced ure write (F : out FT; value: in TM);

function endfile (F: in FT) return boolean;

Procedure read retrieves the next value from a file. Procedure write appends a value to a file. Function endfile returns False if a subsequent read operation on an input file can retrieve another value from the file; otherwise it returns true. Function endfile always returns true for an output file.



1.5.1.5 Other Types

There are several other types provided by external library, IEEE. This library contains a std_logic_l 164 package which supports more types. Let us discuss them.

std_Logic type

std_logic is a data type defined by IEEE standard 1164, and defined in the file ieee.vhd.std_logic is an enumerated type. This logic has nine v'llues as listed in Table. 1.7.

Value Definition

u - Uninitialized

x - Forcing unknown

0 -· Forcing 0

1 - Forcing 1

z - High impedance

w - Weak unknown

L - Weak 0

H - Weak 1

. - Don't care

Table 1.7 The std_logic data type is very important for both simulation and synthesis.

Std_logic includes values that allow us to accurately simulate such circuit conditions as unknowns and high-impedance stages. For synthesis purposes, the high-impedance and don't -care values provide a convenient and easily recognizable way to represent three-state enables and don't-care logic. For synthesis, only the values 0, 1, z and -have meaning and are supported.

std_lugic_vector type

The type std_logic_vector represents an array of bits whose type is std_logic.

Example:

Port (I : in std_logic_vector (7 downto O);

0: out bit);

In the above example, port I is declared as type std_logic_vector which has 8 bits.

Signed

The type signed is a numeric type. It is declared in the external package numeric_std and represents signed integer data in the form of an array. The left most



bit of objects of signed type represents sign and such objects are represented in 2's complement form. let us see the object definition.

In the above definition, the variable difference is declared as signed type and has 5 bits with initial value 10011, or - 13.

Unsigned

The type unsigned represents integer data in the form of an array of std_logic and it is declared in the external package numeric_std. Let us see the object definition variable num : unsigned (4 downto 0) := 10011; In the above definition, the variable num is declared as unsigned type and has 5 bits with initial value 10011, or 19.

1.5.2 Verilog Data Type

The set of Verilog HDL data types is designed to represent the data storage and transmission elements found in digital hardware. Since the purpose of Verilog HDL is to model digital hardware, the primary data types are for modeling registers (reg)

and nets (wire). The reg variables store the last value that was procedurally assigned to them whereas the wire variables represent physical connections between structural entities such as gates. A wire does not store a value; its value changes continuously by the circuit that are driving it.

The Verilog HDL also supports several other data types including integers, real, parameters and arrays.

1.5.2.1 Nets (Wire) and Registers

The reg and wire data objects may have the following possible values :

Value Definition

0 logical zero or false

1 logical one or true

x unknown logical value

z high impedance of tristate gate

The reg variables are initialized to x (unknown logic value) at the start of the simulation. Any wire variable not connected to something has the x value. We may specify the size of a register or wire in the declaration. For example, the declarations

wire Dl;

wire DO = t 'bO;

reg flag;


Fundamentals of HDL 1. 28 Introduction

Specify wires 0 1 and DO to be single bit wide. The initial value of DO is l'bO, which represents 1 bit with value 0.

When the size of the reg or wire is more than 1 bit then registers and wires are declared as vectors. Vectors are declared by brackets. The bits in vectors can be referenced by the notation (<start-bit>:<end-bit>]. For example, the declarations

reg (0:7( A, B;

wire 10:3) Dataout; reg (7:0) C = 8'b10001010;

reg (7:0) D ~ 3'd138;

A = 8'b01011010 B = {A(0:3) I A(4:7(, 4'b0000};

Specify registers A and B to be 8-bit wide with the most significant bit the zeroth bit, whereas the most significant bit of register C and register D is bit seven. The wire Dataout is 4 bits wide. C holds a value of 10001010 (b stands for binary). D holds the same value as C (10001010); however it is specified in decimal 138 (d stands for decimal).

B is set to the first four bits of A bitwise or-ed with the last four bits of A and then concatenated with 0000. B now holds a value of 11110000. The II brackets means the bits of the two or more arguments separated by commas are concatenated together.

An argument may be replicated by specifying a repetition number of the form :

Here are some examples : c = {2{4'b1011}}; C = { {4{A(41} }, A[4:71};

Memories are specified as each 32-bits.

reg [31:0) Mem (0:1023);

II C assigned the bit vector 8'b10111011

11 first 4 bits are sign extension vectors of registers. For example, Mem is 1 K words

The notation Mem(O) references the zeroth word of memory. The array index for memory (register vector) may be a register. Notice that one can not refer a memory at the bit-level in Verilog HDL. If we want a specific range of bits in a word of memory, we must first transfer the data in the word to a temporary register.

1.5.2.2 Abstract Data Types : integer, real time

In addition to modeling hardware, there are other uses for variables in a hardware model. For example, the designer might want to use an integer variable to count the number of times an event occurs. For the convenience of the designer, Verilog HDL



has several data types which do not have a corresponding hardware realization. These data types include integer, real and time. The data types integer and real behave pretty much as in other languages, e.g. C. Be warned that a rag variable is unsigned and that an integer variable is a signed 32-bit integer. This has important consequences when we subtract.

time variables hold 64-bit quantities and are used in conjunction with the $time system function. Arrays of integer and time variables (but not reals) are allowed. Multiple dimensional arrays are not allowed in Verilog HDL.

Examples:

integer Count; //simple signed 32-bit integer

integer K(1:64J; //an array of 64 integers real cost; // declares cost as real

time Start, Stop; // Two 64-bit time variables

1.5.2.3 Parameter

Parameter type is used to define global constants. We can declare global constants by predefined word parameter.

Examples:

parameter N = 0; parameter M = 7;

reg (M:NJ C = 8'b10001010; //use of constants to define register width

1.6 Styles or Types of Descriptions

In a VHDL or Verilog program, architecture body (VHDL) or the module (Verilog) contains a series of concurrent statements. All concurrent statements execute simultaneously. HDL has several different concurrent statements. Also, it has a mechanism which bundles a set of sequential statements which operate as a single concurrent statement. The way in which these statements are used is called the modeling style or types of descriptions". Thus these statements give rise to six different modeling styles or types of descriptions a~,

• Behavioral

• Data flow

• Structural

• Switch-level

• Mixed-Type

• Mixed-Language


Fundamentals of HDL 1 • 30

Let us see the HDL uescription of full adder shown in the Fig. 1.4

Fig. 1.4 Implementation of full-adder

1.6.1 Behavioral Descriptions

Introduction

It is sometimes possible to directly describe the behavior or the functionality of a circuit. Such a modeling style is called behavioral modeling which is very similar in syntax and semantics to that of a high-level programming language (For example : C, Pascal). A behavioral description models the system as to how the outputs behave with the inputs.

In VHDL, the behavior of the entity is expressed using sequentially executed, procedural code. The key mechanism used to model the behavior of the entity is, a

process statement.

)II- Listing 1.2 : Example of VHDL behavioral description entity full_ add is

port (A, B, Cin : in bit;

Sum, Cout : out bit);

end full_add;

architecture adder of full add is

begin

process (A, B, Cin) begin

Sum < = A xor B xor Cin;

Cout < = (A and B) or (Cin and A) or (Cin and B);

end process;

end adder;

In Verilog, the key mechanism used to model the behavior is predefined words always or initial.


Fundamentals of HDL 1 - 31

.... Listing 1.3 : Example of Verilog behavioral description module full_ add (A, B, Cin, Cout, Sum);

input A, B, Cin;

output Sum, Cout;

re g Sum, Cout;

always @(A, B, Cin)

begin

Sum = (A A B) A Cin;

Cout = (A & B) I (Cin & A) I (Cin & B);

end

endmodule

1.6.2 Dataflow Design Elements

lntrQduction

Data flow describes how the circuit signals flow from the inputs to the outputs. There are some concurrent statements which allow to describe the circuit in terms of operations on signals and flow of signals in the circuit. When such concurrent statements are used in a program, the style is called a 'dataflow design'. Concurrent signal assignment statements are used in. this type of modeling style.

.... Listing 1.4 : Example of VHDL data-flow description entity full_add is


Sum, Cout : out b it);

e nd full_ add;


begin



end adder;

In Verilog, predefined word assign is used to assign a value to the left-hand side of a s ignal-ass ignme nt s ta te ment.

.... Listing 1.5 : Example of Verilog data-flow description module full_ add (A, B, Cin , Cout, Sum);

input A, B, Cin;

output Sum, Cout;

ass ign Sum = (A A B) A Cin;

assign Cout = (A & B) I (Cin & A) I (Cin & B);

endmodule



The built in operators of VHDL (for example : AND, OR,"NOT) and Verilog (for example & I ") are used in the expression.

Here, the data flow model for the full_add is described using a two concurrent signal assignment. In a signal assignment statement, the symbol <= implies an assignment of a value to a signal ·in VHDL. The value of the expression on the right-hand-side of the statement is computed and is assigned to the signal on the left-hand-side, called a target signal. In Verilog, predefined word assign is used to assign a value to a signal. A concurrent signal assignment is executed only when any signal in the expression on the right-hand-side has an event on it, that is, the value of the signal changes.

1.6.3 Structural Design Elements

In structural design, a VHDL and Verilog uses components or gates to model the system. The important features of VHDL structural type of architecture body are :

• Design hierarchy

• Components are used

• Each component is simulated separately

In the structural modeling, an entity is described as a set of components connected by signals, that is, as a netlist. The components used in an architecture may be from a library or may be ones that were previously defined as part of a design.

entity full_ add is



end full_ add;


component xor3

port ( 11, 12, 13 : in bit;

01 : out bit );

end component; component and2

port ( 11, 12 : in bit;

01 : out bit );

end component;

component or3

port ( I1. 12, 13 : in bit;

01 : out bit );

end component; signal S1, S2, SJ : bit;



begin

Y1 : xor3 port map (A, B, Cin, Sum); Xl : and2 port map (A, B, S1); X2 : and2 port map (A, Cin, S2);

X3 : and2 port map (B, Cin, S3);

Y2 : or3 port map (Sl, S2, SJ, Cout); end adder;

Introduction

The name of the architecture body is adder. The entity declaration for full_add specifies the interface ports for this architecture body. The architecture body is composed of two parts : the declarative part (before the keyword begin) and the statement parts (after the keyword begin). The components may either be predefined components in a library or they may later be bound to other components in a. library. The declared components are instantiated in the statement part of the architecture body using component instantiation statement. Yl, Xl, X2, X3, Y2 are component labels for this component instantiations. I1 is connected to signal A, 12 is connected to signal B, 13 is connected to signal Cin, and 01 is connected to Sum in portmap xor3 gate. Similarly, port maps for and2 and or3 are defined. Note that in this case, the signals in the port map of a component instantiation and the port signals in the component declaration are associated by position. A component instantiation statement is a concurrent statement.

1.6.4 Switch-Level Descriptions

In switch-level description the system is described using transistors which are operated as switches. They are usually used to describe relatively small-scale digital systems. The verilog uses keywords nmos, . pmos, cmos, tranifo, tran and tranifl to describe the system. The VHDL does not have built-in .switch-level primitives; however we can construct packages to include such primitives and attach them to the VHDL module.

.... Listing 1.6 : VHDL switch-level description library ieee ;

use ieee.std_logic_1164.all; entity Inv la

port (X : in std_logic; Y : out std_logic);

end Inv; architecture Inverter of Inv la

component nmos port (01 : out std_logic;

11, 12 : in std_logic);


Fundamentals of HDL

end component;

Component pmos

port (01 : out std_logic;

11, 12 : in std_logic);

end component;

1 . 34

·- pmos and nmos are keywords for switch level

for all : pmos use entity work.mos (pmos_behavioral);

for all: nmos use entity work.mos (nmos_behavioral);

-- above two statements refer the mos package.

constant vdd : std_ logic : = '1 ';

constant gnd: std_logic := 'O';

begin

p : pmos port map (Y, vdd, X);

n : nmos port map (Y, gnd, X);

end inverter;

.... Listing 1.7 : Verilog switch-level description module Inv (Y, X);

inputX;

output Y;

supply 1 vdd;

supply 0 gnd;

pmos p(Y, vdd, X);

nmos n(Y, gnd, X);

endmodule

1.6.5 Mixed-Type Descriptions

Introduction

Mixed type or mixed-style descriptions use more than one type or style of the basic styles discussed above. The listing 1.8 and 1.9 show an example of mixed type description which uses data-flow and behavioral descriptions .

..,. Listing 1.8 : Example of VHDL mixed-type description entity full_ add is



end full_ add; architecture adder of full_add is

begin

-- data-flow description


Fundamentals of HDL


p rocess (A, B, Cin)

begin

1 . 35

-- behavioral description


end process;

end adder;

... Listing 1.9 : Example of Verilog mixed-type description mod ule full_add (A, B, Cin, Cout, Sum);

input A, B, Cin;

outpu t Sum, Cout;

reg Sum, Cout;

assign Sum = (A " B) " Cin;

always @(A, B, Cin)

begin

11 data-flow description

11 behavioral description

Cout = (A & B) I (Cin & A) I (Cin & B);

end

e ndmod ule

1.6.6 Mixed Language Descriptions

Introduction

Mixed language descriptions is the latest tool for HDL description in which we can write a module or entity in one language and invoke or import a modul~ or entity written in the other language. The listing 1.10 shows verilog module for full-adder in which we instantiate (import) the VHDL entity HA (Half-adder).

... Listing 1.10 : Example of mixed language type description module full_add (A, B, Cin, Cout, Sum);

input A, B, Cin;

ou tput Sum, Cout;

wire CO, Cl, SO;

Half_adder Hl (A, B, SO, CO);

Half_adder H2(SO, Cin, Sum, Cl);

assign Cout =CO I Cl ;

endmodule

II Description of Half-Adder (HA) is written in VHDL

···-...


Fundamentals of HDL 1 . 36 Introduction

library ieee;

use ieee.std_logic_1164.all;

-- For correct mixing of two codes the entity name should be same, i.e., Half_adder entity Half_ adder is

port ( X, Y : in std_logic;

S, C : out std_logic);

end Half_adder;

architecture adder of Half adder is

begin

S <= A xor B;

C <=A and B;

end adder;

1.7 Simulation and Synthesis

This section explains two main applications of hardware description languages, namely synthesis and simulation. These two are complementary design processes.

1.7.1 Synthesis

The task of designing a digital system that implements a desired functional behaviour is referred to as the "synthesis'. Simply we can say, synthesis is the process of generating a logic circuit from a truth table. For performing this process automatically, synthesis CAD tools are available.

Let us see, how HDL is useful for the synthesis of a digital circuit. A HDL program is the input to a synthesis cotnpiler. When this HDL code is passed throngh initial synthesis tool, a lower-level description of the circuit is generated as an output. With this process, a set of logic expressions which describes the logic functions required to realize the circuit is produced. After this, these expressions are manipulated further by the synthesis tools. The design entry may be in the form of schematic capture or truth table. The logic expressions produced by the synthesis tool are not likely to be in an optimal form. It is the task of the synthesis tool to manipulate the user's design to produce an equivalent but better circuit automatically. This step of synthesis process is called 'logic synthesis' or 'logic optimization'. Still the optimized circuit is in the form of logic equations. In the last step of synthesis, it is determined exactly, how the circuit will be realized in a specific hardware technology. For executing this task, according to the physical resources available, it is decided how to implement each logic function given by an expression. In this process a list of components and their interconnections is derived from the model of a digital system described in HDL. This list is called a 'netlist'. An integrated circuit or a layout of a printed circuit board can be obtained by using a gate-level netlist. Thus a logic synthesis produces a database with instructions on how to fabricate a physical piece of


Fundamentals of HDL 1. 37 Introduction

digital hardware. Logic synthesis consists of that part of a digital system design that can be automated with computer software.

1.7.2 Simulation

In any design process, there are the basic tasks which should be performed in a sequence. The flow-chart shown in Fig. 1.5 gives this basic sequence of tasks.

START

Initial design

Simulation

Successful design

Fig. 1.5 Basic design steps

First, the initial design is generated manually by the designer according to his views, skills and knowledge. After this, the simulation of the design is carried out mostly with the help of CAD tools. For the successful simulation, it is necessary to apply adequate input conditions to the design as well as to the final product which has to be tested. The simulator checks the designed product under the original product specifications. This is known that what should be achieved. So if there are errors, then those are removed and redesigned product is again simulated. This loop is repeated until the simulation gives problem-free/error-free product. Once the designed product performs correctly all of its functions, we call it the 'successful design'.

The operation of a digital circuit can be verified fastly and accurately using logic simulation. There are two types of verification techniques, functional and timing.

The simulation is referred to as ' functional simulation' when all the functions of the circuit are verified. After completion of successful functional simulation, the



'physical design' step is carried out. Physical design includes the physical location of each chip on the board and the needed wiring pattern. CAD tools are used for performing this task automatically. After physical design, the functionality of the circuit is checked. But, eventhough the functional behaviour is correct, the circuit may operate more slowly than the desired. The physical wiring on board introduces resistance and capacitance of electrical signals. The delays are introduced because of logic circuits such as gates. This reduces the speed of operation of the circuit and thus lead to inadequate performance. So timing behaviour of the circuit should also be considered. The simulation which also considers the timing behavior of the circuit is referred to as 'timing simulation'.

Thus in functional simulation, the circuit logical operation is studied by deriving the truth table of the circuit independent of timing considerations. In timing simulation, the circuit operation is studied by considering timing behaviour of the circuit. For example, the waveforms at the output of the gate are observed when they respond to a given input.

1.8 Brief Comparison of VHDL and Verilog

The Table 1.8 gives brief comparison between VHDL and Veriiog.

Parameter VHOL Verilog

Application • In general. VHDL is better for • In general, verilog is better for describing complex systems since describing systems at the gate or multiple entity/architecture pair leads to switch (transistor) level due to its use nexibilitv and ease in writinn code. of nredefined nrimttives at this level.

Data type • Supports more data types. • Supports less data type.

• Supports user-defined data type which • Does not support user-defined data enables more efficient and flexible type. coding.

• Can handle objects with • Does not support multidimensional array multidimensional array types. type.

• Supports physical data type • Does not support physical data type.

Easy of • Hard to learn for beginners because of • Easy to learn; very similar to C learning tts riQid tvoe requirements. lanquaQe.

libraries and • Supports packages and libraries. • Does not support libraries and packages Package can include procedures and packages.

functions and it can be made available to any module. It allows reusability of code.

Operators Does not support predefined unary Supports predefined unary operators. operators supports arithmetic shift and Does not support arithmetic shift and rotate operators. rotate operators.



Procedures Concurrent procedure calls are allowed. Concurrent task (Procedure in VHDL) are and Tasks Functions are allowed to be written Inside allowed. However, functions are not

the procedure's body. allowed to be wrrtten inside the task's body.

Case Case insensitive Case sensitive sensitivity

Comment Starts with - Starts with II

Table 1.8 Comparison between VHDL and verilog

1.9 Summary of Operators in VHDL and Verilog ,

' . ,

Arlthmetl1' opera~o.rs , ~· . ;,

Operation Operator

VHDL Veritog

Addition .. .. Subtraction - -

Multiplication . •

Division I I

Modulus mod %

Exponent .. .. Concatenation (&) { . }

, ''"'' , ., . . ., " ·'• . , tR~l~!ion~I 9Ptra!ors •

Operation Operator

VHDL Verilog

Equality = == Inequality f; !:

Less than < <

Less than or equal <= <=

Greater than > >

Greater than or equal >: >:

Equality inclusive none ---Inequality inclusive none !=:

i..;opynghtE'd ni 1tenal


Operation Operator

VHDL Verilog

AND AND &

OR OR

NOT NOT

NANO NANO -(&)

NOR NOR - (I)

XOR XOR A

XNOR XNOR ...A

Operation Operator

VHDL Verllog

Logicai left shift sll <<

Logical right shift

Arithmetic 1et1 shift

Arithmetic right shift

Rotate left

Rotate right

Comment : Rotate two poo1tions

Table 1.9 Summary of operators in VHDL and Verilog

Copyrighted l'1 tenal


Review Questions

1. Explain the need of HDL.

2. Explain tire structure of VHDL program with the help of example.

3. Explain the structure of Vt•rilog HDL program with tire help of example.

4. Explain various data types supported by VH DL.

.S. Explain 11ario11s data types supported by Verilog.

6. If A == 1011 and B = 1101, find the value of t/1e following cxpres$iOns :

a. A AND B

b. A & B

c. A&&B

d. A AB

e. A _AB

f A» 2

g. B ror 1

7. What do you mean by modelling style ?

8. Write a VHDL and Verilog behavioral description for half-adder.

9. Write a VHDL and Verilog data flow description for lralf-subtractor.

10. Write a VHDL and Verilog structural descriptum for full subtractor.

11. Write a short note on switch-level description.

12. Explain the mixed-type description with the help of example.

13. Write a short note on mixed-langitage description.

14. Give the comparison between VHDL and Verilog.

Introduction

DOD


(1 • 42)

Data-Flow Description

2.1 High Lights of Data-Flow Description

• Data-flow is one modeling style of hardware description.

• It simulates the system by showing how the circuit signal flow from the inputs to the outputs.

• It uses concurrent statements. Thus at any simulation time, all signal assignment statements are executed concurrently.

2.2 Structure of the Data-Flow Description

The listing 2.1 shows the HDL code for the circuit shown in the Fig. 2.1. The circuit is an AND-OR circuit in which signals A, B, C, D and E are input signals, signal Y is an output signal and signals I1 and 12 are intermediate signals.

A B

C---r--.... 0 E--1.-"

Fig. 2.1 AND-OR circuit

y

.... Listing 2.1 : HDL code for AND-OR circuit - VHDL and Verilog

VHDL AND-OR Circ uit Description.

entity AND_OR is

port (A, B, C, D, E : in bit;

Y: out bit );

end;

architecture digital_ckt of AND-OR is

signal 11, 12;

begin

(2 - 1)


Fundamentals of HDL 2·2

stl : 11 < = A and B after l Ons;

st2 : 12 < = C and D and E after 10ns;

st3 : Y < = 11 or 12 after 20ns;

end digital_ckt;

Verilog AND.OR Circuit Description.

module AND_ OR (A, B, C, D, E, Y);

input A, B, C, D, E;

output Y;

wire 11, 12;

u1ign #10 11 = A & B;

assign #10 12 = C & D & E;

assign #10 Y = 11 I 12;

endmodule

2.2.1 Signal Declaration and Assignment Statement


VHDL : Here, input and output signals are declared in the entity as ports. However, the intermediate signals (11 and 12 in the listing 2.1) are declared using the predefined word signal in the architecture. A signal assignment operator <= is used in VHDL to assign a value to the left-hand side of a signal•assignment statement. The left-hand side of the statement should be declared as a signaL The right-hand side can be a signal, a variable or a constant.

Verilog : Here, input and output signals are declared in the module. However, the intermediate signals are declared using the predefined word wire. 3y default, all ports in Verilcg are assumed to be wires. The value of the wire is continuously changing with changes in the device that is deriving it.

When it is necessary to store the object's value then reg type declaration is used in Verilog. In Verilog, any object that is assigned a value in an always statement must be declared as reg. (Refer listing 2.1).

2.2.2 Execution of Assignment Statement

The execution of assignment statement is done in two phases : calculation and assignment. Consider the listing 2.1 and ' the simulation waveform shown in the Fig. 2.2.

Calculation : The value of 11 is calculated using the current values of A and B at time TO. This value is (1 and 0) = 0 in VHDL or (1 & O) = 0 in Verilog.


Fundamentals of HDL

A

B

c

2-3 Data-Flow Description

----- o I I

------~------------~--------- 0 ' I

0

D __ ....... ______ .,_ _____ _.______ 0

E ---------0

y

l l l l T0 T1 T2 T3 T4 T5

0 0 0 0 0 0 ., "'

., "'

., <ll

., "'

., <ll

., <ll

c c c c c c 0 0 0 0 0 0 0 "' 0 "' 0 "' -- "' "' M M

Fig. 2.2 Simulation waveform for listing 2.1

Assignment : The calculated value is not immediately assigned to 11; however it is assigned to 11 after a time delay of 10 ns. The delay time can be implicitly or explicitly specified. In our case, we have assumed propagation delay of each gate as 10 ns and hence we have explicitly specified time delay equal to 10 ns.

In Veri!:.1g, we have written statement as : assign #IO I1 = A & B; In Verilog, time units are not specified; the simulator assumes a delay in screen time units. Therefore, in our case the calculated value is assigned to 11 after 10 screen time units.

The change in the 11 at T = 110 ns constitute an event in signal assignment statement st3 and this causes execution of st3. For statement st3, at T = 110 ns, 12 = 0

and 11 = 0 and hence the calculated new value of Y at T = 110 ns is (11 or 12) = 0. This change in value for Y from 1 to 0 is assigned to Y after 10 ns - that is, at Tl = 110 + 10 = 120 ns.


Fundamentals of HDL 2-4 Data-Flow Description

Important points

• To assign a delay time to a signal assignment statement, we use the predefined word after (delay time) in VHDL or # (delay time) in Verilog.

• In VHDL we specify delay in time units such as nsec, msec, sec etc. In Verilog, delay time is specified in screen unit time.

2.2.3 Constant Declaration and Ass'ignment Statement

A constant in HDL is same as constant in C language; its value is constant within the segment of the program where it is visible. A constant in VHDL can be declared using predefined word constant. For example,

~-~~;~~1~u~~~~a~JIB In Yerilog, a constant can be declared by its type, such as time or integer.

In VHDL, we use the assignment operator := to assign a value to a constant. On the other hand, we use the assignment operator = in Verilog to assign value to a constant. For example,

delay :; 1 Ons; -· VHDL delay = 1 O: Ii Verilog

It is possible to assign a value to the constant in the declaration statement itself. This is shown in following examples.

constant delay : ilme := 1 Ons; ·- VHOL time. delay = 12; ' If Verilog

m• Example 2.1 : Data-Flow Description of a Half-Adder Digital computers perform various arithmetic operations. The most basic operation,

no doubt, is the addition of two binary digits. This simple addition consists of four possible elementary operations, namely,

0 + 0 = 0

O+l:ol

l+O :o l

l+l:ol02

The first three operations produce a sum whose length is one digit, but when the last operation is performed sum is two digits. The higher significant bit of this result is called a carry, and lower significant bit is called sum . The logic circuit which

Copynqhted material


performs this operation is called a half-adder. The circuit which performs addition of three bits (two significant bits and a previous carry) is a full-adder.

The half-adder operation needs two binary inputs : augend and addend bits; and two binary outputs : sum and Cout. The truth table shown in Table 2.1 gives the relation between input and output variables for half-adder operation.

Inputs

A B

0 0

0 1

1 0

Outputs

Cout Sum

0 0

0 1

0 1

A

Inputs

B

Half adder

Cout

Outputs

Sum

1 1 1 0 Fig. 2.3 Block schematic of half-adder

Table 2.1 Truth table for half-adder

K-map simplification for Cout and Sum

For Cout

B A 0

0 0 0

0

Cout =AB

For Sum

Sum=AB +AB =A(f)B

Fig. 2.4 Maps for half-adder

Fig. 2.5 Logic diagram for half-adder



~ Listing 2.2 : HDL code for half-adder-VHDL and Verilog.

VHDL Half Adder Description.

entity h aif_adde r Is

port (

A: in bit;

B : in bit;

Sum : out bit;

Gout : out bit);

end half_ adder;

architecture adder of h alf_adder ls

begin

Sum < = A xor B; -- signal assignment statement.

Gout < = A and B; -- signal assignment statement.

end adder;

Verilog Half Adder Description.

module half_ adder (A, B, Sum, Gout);

input A;

Input B;

output Sum;

output Gout;

assign Sum = a " b;

11 The d efault type of all inputs and outputs is a single bit.

II signal assignment statement.

assi!ill c = a & b ;

endmodule

II " is a b itwise xor logical operator.

11 signal a ssignment statement.

II & is a bitwise logical "and" operator.

11'* Example 2.2 : Multiplexer with Active Low Enable. The Fig. 2.6 shows 2 x 1 multiplexer. It has two 1-bit inputs : DO and Dl, a 1-bit

select line S, a 1-bit output : Y and a 1-bit enable signal : En. The input signals DO and 01 are connected to the one input of AND gates : ANDl and AND2, respectively. If enable signal (En) is low, the output is equal to one of the two inputs depending on



s Enbar or En --!:»---' 12

DO

D1

s

2x1 MUX

En-----'

y

(a) Logic diagram (b) Logic symbol

Fig. 2.6 2 x 1 multiplexer

the status of select (S) signal. If S = 0, the output is equal to DO and if S = 1 the output is equal to Dl. The Table 2.2 shows the the truth table for 2 x 1 multiplexer.

Input Output

s En bar y

x 1 0

0 0 DO

1 0 D1

Table 2.2 Truth table for a 2 x 1 multiplexer

.... Listing 2.3 : HDL code of a 2 x 1 multiplexer - VHDL and Verilog.

VHDL 2 x 1 Multiplexer Description.

library teee;

use teee.std_loglc_1164.all;

entity mux2x 1 ts

port (DO, Dl, S, Enbar: ln std_logic;

Y : out std_logic);

end mux2x1;

architecture MUX of mux2x1 is

s ignal Il, 12, 13, 14 : std _logic;

begin

-- Assume 10 nanoseconds prop a gation d e lay

-- for all and, or, and not.


Fundamentals of HDL 2 - 8 Data-Flow Description

I1 < = not S after 10 ns;

12 <= not Enbar after 10 ns;

13 < = DO and 11 and 12 after 10 ns;

14 < = D1 and S and 12 after 10 ns;

Y <= 13or14 after 10 ns;

endMUX;

Verilog Description : 2 x 1 Multiplexer. (Refer Fig. 2.7 on next page)

module mux2xl (DO, Dl, S, Enbar, Y);

Input DO, Dl, S, Enbar;

output Y;

wire 11, I2, 13, I4;

II Assume 10 time units delay for all and, or, not. In Verilog

II we cannot use specific time units, such as nanoseconds.

II The delay here is expressed in simulation screen units.

assign #10 Y = I3 I I4;

assign #10 I3 = DO & I1 & I2;

assign #10 I4 = Dl & S & I2;

assign #10 I1 = - S;

assign #10 12 = - Enbar;

endmodule

2.3 Data Type - Vectors

We have already introduced the vector data type in chapter 1. The vector data type declares an array of similar elements, rather than declaring each individual bit separately. For example,

Individual bit declaration : signal AO, Al. A2, A3 : bit ; --VHDL

wire AO, Al, A2, A3 ; II Verilog

Vector declaration : signal A: bit_ vector (3 downto 0); -· VHDL

signal A : bit_ vector (0 to 3) ; -- VHDL



DO ---.

01 _______ __.

S ---+--------'

Enbar

y

I

l l l l To T1 T2 T3 T4 Ts Te Tr

u u u u u u u u ., ., Q) ., Q) ., ., ., </) </) "' </) "' "' "' </) c:. c: c: c: c: c: c: c: 0 0 0 0 0 0 0 0 0 "' «> - (') <D Ol "' - - - "' N "' "' M

Fig. 2.7 Simulation waveform for a 2 x 1 multiplexer

wire 13 : OJ A; II Verilog

wire 10: 3) A ; II Verilog

In VHDL, downto and to are predefined operators that describe the width of the vector. Operator downto is used when zeroth element is the least significant element, and operator to is used when zeroth element is the most significant element. For example, if A has value 1100 and declaration is signal A : bit_vector (3 downto 0) then the elements of vector A are :

A(3] = 1, A(2) = 1, A(l) = 0, A(O] = 0

On the other hand, if the declaration is

signal A : bit_ vector (0 to 3) then the elements of vector A are :

A[O) = 1, A[l) = 1, A(2) = 0, A[3) = 0.

111• Example 2.3 : 4x 1 Multiplexer.

The Fig. 2.8 shows 4 x 1 multiplexer. Each of the four lines, DO to D3, is applied to one input of an AND gate. Selection lines are decoded to select a particular AND gate.


Fundamentals of HDL 2 -10 Data-flow Description

00

01

D2

D3

so S1

Enbar or EN

.. 11

... 12 .. ::. 13 ....

(a) Logic diagram

. ' . . J

. ' . ,I

. ' . ,I

. ' . ,I

14

15

16

17

-

-......

/ y

DO D1 02 D3

so ____ ~

4x1 MUX

s1 _____ __.

Enbar --------'

(b) Logic symbol


In.put Output

S1 so Enbar y

x x 1 0

0 0 0 DO

0 1 0 D1

1 0 0 02

1 1 0 03

Table 2.3 Truth table for 4 x 1 multiplexer

II> Listing 2.4 : HDL code of a 4 x 1 multiplexer - VHDL and Verilog.

VHDL 4x1 Multiplexer Description.

library leee;

use leee.std_logic_1164.all; entity mux4xl ls

port ( D : In std_logic_ vector (3 downto O);

S, Enbar: ln std_logic;

Y : out std_logic);

y


Fundamentals of HDL 2 -11

end mux4x1;

architecture MUX of mux4x1 ls

signal 11, 12, 13, 14, 15, 16, 17 : std_logic;

begin


-- Assume 10 nanoseconds propagation delay

11 < = not SO after 10 ns;

12 < = not S1 after 10 ns;

13 < = not Enbar after 10 ns;

-- for all and, or, and not.

14 < = DO and I1 and 12 and 13 after 10 ns;

15 <= Dl and SO and 12 and 13 after 10 ns;

16 < = D2 and Sl and 11 and 13 after 10 ns;

17 < = D3 and SO and S1 and 13 after 10 ns;

Y < = 14 or 15 or 16 or 17 after 10 ns;

endMUX;

Verilog Description : 4 x 1 Multiplexer.

module mux4x1 (D, S, Enbar, Y);

input (3 : 01 D;

input S, Enbar;

output Y;

wire 11, 12, 13, 14, 15, 16, 17;

II Assume 10 time units delay for all and, or, not. In

II Verilog we cannot use specific time units, such as

II nanoseconds. The delay here is expressed in simulation

11 screen units.

assign #10 Y = 14 I 15 I 16 I 17;

assign #10 14 = DO & 11 & 12 & 13;

assign #10 15 = D1 & SO & 12 & 13;

assign #10 16 = D2 & Sl & 11 & 13;

assign #10 17 = D3 & SO & Sl & 13;

assign #10 11 = - SO;

assign #10 12 = - Sl;

assign #10 13 = - Enbar;

endmodule


Fundamentals of HDL 2 -12 Data-Flow Description

u• Example 2.4 : 2 >< 2 Unsigned Combinational Array Multlpller.

Let . us generalize the multiplication process for a 2 >< 2 multiplier for two unsigned 2-bit numbers : multiplicand A = Al AO and multiplier B = Bl BO. The Fig .. 2.9 shows how the multiplication process is carried out.

A1 AO

x

B1 BO

I~,. •. '"°'"" BOA1

+

B1 A1 B1 AO I ! PMOAO

P1 = BOA1 + B1AO

P3 P2 P1 PO P2 = B1 A 1 + Carryout of P1

P3 = Carryout of P2

Fig. 2.9 Multiplication process

The multiplication process involves multiplication (product) of 2-bit number and addition of 2-bit number. The multiplication of 2-bits can be implemented using 2-input AND gate whereas addition of 2-bits can be implemented using half-adder. Such an implementation of 2 >< 2 multiplier is shown in the Fig. 2.10.

B1 A1 B1 AO BO A 1 BOAO

Half-adder

P3 P3 P1 PO

Fig. 2.10 2 >< 2 bit combinational array multiplier



Ill>- Listing 2.5 : HDL code for a 2 x 2 unsigned combinational array multiplier - VHDL and Verilog.

VHDL 2 x 2 Unsigned Combinational Array Multiplier Description.

library ieee;


entity Arr_Mul is

port (A, B: in std_logic_vector (1downto 0);

P: out std_logic_vector (3 downto O));

end Arr_Mul;

architecture MULT of Arr Mul is

begin

-- For simplicity propagation delay times are not considered in this example.

P(O) < = B(O) and A(O);

P(l) < = (B(O) and A(1)) xor (B(l) and A(O));

P(2) < = (B(1) and A(1)) xor ((B(O) and A(1)) and (B(1) and A(O)));

P(3) < = (B(1) and A(1)) and ((B(O) and A(l)) a.nd (B(1) and A(O)));

endMULT;

Verilog 2 x 2 Unsigned Combinational Array Multiplier Description.

module Arr_Mul (A, B, P);

input [1:01 A, B;

output 13:01 P;

/* For simplicity, propagation delay times are not

considered in this example.* I

assign P[OI = BIOi & AIOI;

assign P[11 = (B[OI & All)) A (B[11 & AIOJ);

assign P[21 = (Bl11 & All)) A ((BIOi & All)) & (Bill & AIOI));

assign P131 = (All i & Bil)) & ((BIOi & Al l ))& (Bill & AIOI)):

endmodule

,,,.. Example 2.5 : D latch

Fig. 2.11 shows the D latch. The NANO gates 1, 2, 3 and 4 form the basic SR latch with enable input. The fifth NANO gate is used to provide the complemented inputs.



D Q

EN

(a) D latch (b) Logic symbol

Fig. 2.11

As shown in the Fig. 2.11, D input ·goes directly to the S input, and its complement is applied to the R input, through gate 5. Therefore, only two input conditions exist, either S = 0 and R = 1 or S = 1 and R = 0. The truth table for D latch is as shown in the Table 2.4.

EN 0 Q n Qn+1 State

1 0 x 0 Reset

1 1 x 1 Set

0 x x Qn No change (NC)

Table 2.4 Truth table for D latch

As shown in the truth table, the Q output follows the D input. For this reason D latch is sometimes called transparent latch.

Looking ilt the truth table for D latch with enable input and s implifying Qn+J

functior1 by K-map we get the characteristic equation for D latch with enable input as Qn<l = EN· D +EN· Qn. This is illustrated in Fig. 2.12.

Fig. 2.12 Characteristic equation



~ Listing 2.6 : HDL code for a 0-latch-VHDL and Verilog.

VHDL D-Latch Description.

library ieee;


entity D_Latch ia

port (D, EN : in std_logic;

a. Obar: buffer std_logic);

-- a and Obar are declared as buffer because they act as

both input and output, they appear on the right and left

hand s ide of s ignal assignment statements. inout or

-- linkage could have been used instead of buffer.

end D_Latch;

architecture Latch of D Latch is

constant Delay_Nand: Time: = 10 ns:.

begin

a<=: Obar nand (D nand EN) after 2*Delay_Nand;

Obar< = a nand ((D nand D) nand EN) after 3*Delay_Nand;

end Latch;

Verilog D-Latch Description.

module D_latch (D, EN, Q, Obar);

input D, EN;

output a, Obar;

/* Verilog treats the ports as internal ports, so a and Obar are

not considered here as both input and output. U the port is

connected externally as bidirectional, then we should use

inout. */

time Delay_Nand = 10;

assign # 2*Delay_Nand Q = Obar-(&) (D -(&)EN);

assign# 3*Delay_Nand Obar = a - (&) ((D - (&) D) - (&)EN);

endmodule



11• Example 2.6 : 2-bit Magnitude Comparator

Inputs

A B

n-bit comparator

A:>B A=B A<B

Outputs

Fig. 2.13 Block diagram of n-bit comparator

Inputs

0 0 0

0

0

0

0

0

A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers. Fig. 2.13 shows the block diagram of an n-bit comparator. It receives two n-bit numbers A and B as inputs and the outputs are A > B, A = B and A < B. Depending upon the relative magnitudes of the two numbers, one of the outputs will be high.

The Table 2.5 shows the truth table for 2-bit comparator.

Outputs

A> B A= B A< B

0

0

0

0

0

0

0

0

0

0

Table 2.5 Truth table for 2-bit comparator



K-map simplification

A >B 1 0

00 01 11 10

00 0 0 0 0

01 r1· 0 0 0

-;-;;: ~t -¥--11 1 1 I 0 l; - •},-10 {.. 1 J

~r.~Cl. 0 0

A< B 1 0 1

00 01 11 10 00 01 11 10

00 Cl 0 0 0 00 0 ,...._ I 1

1~· ~ 1 ~ ' ....:..JI

•... ,, ; '

01 0 i@ 0 0 ~~ ':

01 0 0 1 1 E .. ~- _..:A;;

11 0 0 ~J 0 11 0 0 0 0

10 0 0 0 r?" .• 2) ~\

10 0 0 rn 0 ff t~

Fig. 2.14

(A = B) = A1 A0 8180 + A1A0 B1B0

+ A1A0 B1B0 + A1A0 B1B0

= A1B1 (A0B0 + AoB0)

+ A1B1 (AoBo + AoBo)

= (Ao 0 B0) ( A1 0 B1)

(A< B) A1A0 B0 + A0 B1B0 + A1B1


Fundamentals of HDL 2·18 Data-Flow Description

Logic Diagram

A,

A>B

A=B

A<B

Fig. 2.15

Copyn 1nt m 1 1

Fuhdamentals of HDL 2 -19 Data-Flow Description

... Listing 2.7 : HDL code of a 2 x 2 magnitude comparator - VHDL and Verilog.

VHDL 2x2 Magnitude Comparator Description.

library leee;


entity COMP_ 2 is

port (A, B : in std _logic_ vector(l downto 0);

AgtB, AltB, AeqB: out std_logic ;

endCOMP_2;

architecture COMP of COMP 2 is

begin

AgtB < = (A(O) and not B(l) and not B(O)) or (A(l) and not B(l))

or A(l) and A(O) and not B(O));

AltB < = (not A(l) and not A(O) and B(O)) or (not A(O) and B(l) and B(O))

or (not A(l) and B(l));

AeqB < = (A(O) xnor B(O)) and (A(l) xnor B(l));

end COMP;

Verilog 2x2 Magnitude Comparator Description.

module cornpr_2 (A, B, AgtB, AltB, AeqB);

input 11:0) A, B;

output AgtB, AltB, AeqB;

assign AgtB = IAIOJ & -Bill & - BIO)) I IA11J & - Billi

I All i & AIOI & -BIO));

assign AltB = (-Alli & - A(OJ & BIO)) I (-AIO I & Bill & BIO)) I (-All) & Bi l JI);

assign AeqB = (A(O] BIO)) & (Al l i Bil));

endmodule

»* Example 2.7 : 4-bit Ripple-Carry and Carry-Lookahead Adder. A single full-adder is capable of adding two one-bit numbers and an input carry.

In order to add binary numbers with more than one bit, additional full-adders can be employed. A 4-bit, parallel adder can be constructed using number of full adder circuits connected in parallel. Fig. 2.16 shows the block diagram of 4-bit parallel adder using number of full-adder circuits connected in cascade, i.e. the carry output of each adder is connected to the carry input of the next higher-order adder.



Cout

83 A'J

Full adder

Sum3

C3

82 A2

Full adder

Sum2

C2

81 A1

Full adder

Sum1

C1

Fig. 2.16 4-bit parallel adder

BO AO

Full adder

Sumo

Cin

It should be noted that either a half-adder can be used for the least significant position or the carry input of a full-adder is made 0 because there is no carry into the least significant bit position.

~ Listing 2.8 : 4-bit ripple-carry adder case study - VHDL and Verilog.

VHDL 4-Bit Ripple-Carry Adder Description.

library leee;


entity adder Is

port (A, B: in std_logic_vector (3 downto 0);

cin : in std_ logic;

sum : out std_logic_vector (3 downto 0);

cout : out std_logic);

end adder;

architecture RCany _adder of adder Is

--Assume 7.0-ns propagation delay for all gates.

signal cl, c2, c3 : std_logic;

constant delay _gt : time : = 7 ns;

begin

sum(O) < = (B(O) xor A(O)) xor cin after 2*delay _gt;

sum(l) < = (B(l) xor A(l)) xor cl after 2*delay _gt;

sum(2) < = (B(2) xor A(2)) xor c2 after 2*delay_gt;

sum(3) <= (B(3) xor A(3)) xor c3 after 2*delay_gt;

cl < = (A(O) and B(O)) or (A(O) and cin) or (B(O) and cin) after 2*delay_gt;

c2 <= (A(l) and B(l)) or (A(l) and cl) or (B(l) and cl) after 2*delay_gt;

c3 < = (A(2) and B(2)) or (A(2) and c2) or (B(2) and c2) after 2*delay _gt;

cout < = (A(3) and B(3)) or (A(3) and c3) or (B(3) and c3) after 2*delay _gt;

end RCany _adder;



Verilog 4-Bit Ripple-Carry Adder Description.

module RCarry_adder (A, B, cin, sum, cout);

input 13:0) A, B;

input cin;

output 13:0) sum;

output cout;

wire c l , c2,c3;

time delay _gt = 7;

II Assume 7.0 ns propagation delay for all gates.

assign #(2*delay_gt) sumlOJ = (BIO] " A(O)) " cin;

assign #(2*delay_gt) sumlll = (B(l) " A( l )) " cl;

assign #(2*delay_gt) suml2J = (Bl21 " A(2)) " c2;

assign #(2•delay_gt) suml3J = (Bl31 " A(3)) " c3;

assign #(2 ' d elay _gt) cl = (AIOI & BIO)) I (AIOI & cin) I (BIOi & cin);

assign /1(2' delay_gt) c2 = (Alli & Bil)) I (All i & cl) I (Bil l & cl);

assign 11(2*delay_gt) c3 = (A121 & Bl2)) I (A[2J & c2) I (Bl21 & c2);

assign #(2*delay_gt) Cout = (AIJJ & B[J)) I (A(JJ & cJ) I (8131 & cJ);

endmodule

Carry Lookahead Adder

The 4-bit adder discussed is implemented using full-adder. In which the carry output of each full-adder stage is connected to the carry input of the next higher-order stage. Therefore, the sum and carry outputs of any stage cannot be produced until the input carry occurs; this leads to a time delay in the addition process. This delay is known as carry propagation delay, whid1 can be best explained by considering the following addition.

0 1 0 1 + 0 0 1 1

1 0 0 0

Addition of the LSB position produces a carry into the second position. This carry, when added to the bits of the second position (stage), produces a carry into the third position. The latter carry, when added to the bits of the third position, produces a carry into the last position. The key thing to notice in this example is that the sum bit generated in the last position (MSB) depends on the carry tha t was generated by the addition in the previous positions. This means that, adder will not produce correct resul t until LSB carry has propagated through the intermediate full-adders. This represents a time delay that depends on the propagation delay produced in an each full-adder. For example, if each full-adder is considered to have a propagation delay



of 30 ns, then 53 will not reach its correct value until 90 ns after LSB carry is generated. Therefore, total time required to perform addition is 90+30 = 120 ns.

Obviously, this situation becomes much worse if we extend the adder circuit to add a greaier number of bits. If the adder were handling 16-bit numbers, the carry propagation delay could be 480 ns.

One method of speeding up this process by eliminating inter stage carry delay is called lookahead-carry addition. This method utilizes logic gates to look at the lower-order bits of the augend and addend to see if a higher-order carry is to be generated. It uses two functions: carry generate and carry propagate.

Consider the circuit of the full adder shown in Fig. 2.17. Here, we define two functions : carry generate and carry propagate.

A;-~~\\

B;- -+--1

Fig. 2.17 Full adder circuit

P; = A; EBB;

G; = A; B;

The output sum and carry can be expressed as

S; = P; E9 C1

C; +I = G; + P; C;

G; is called a carry generate and it produces on carry when both A; and B; are one, regardless of the input carry. P; is called a carry propagate because it is

associated with the propagation of the carry from C; to C;.i· Now C;.1 can be expressed as a sum of products function of the P and G outputs of all the preceding stages. For example, the carriers in a four stage carry-lookahead adder are defined as follows:

C1 = Go + Po C;n

C2 = G1 + P1 C1 = G1 + P1Go + P1 Po C;n

C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 Go + P2 P1 Po C;n

~=~+~~=~+~G2+~~G1 +~~~~+~~~~~


Fundamentals of HDL 2. 23 Data-Flow Description

Fig. 2.18 shows the 4-bit carry-lookahead adder.

Carry lookahead generator

53 P3 G3

52 P2 G2

51 P1 G1

A3 93 A2 92 A1 91 AO BO

Fig. 2.18 4·bit carry lookahead generator

We can further simplify the design by noting that the sum equation of stage i.

Si = Ai xor Bi xor Ci as Si = Pi xor Gi xor Ci

.... Listing 2.9 : 4-bit carry-lookahead adder - VHDL and Verilog.

VHDL 4-Bit Carry-Lookahead Adder Description.

library ieee;


entity adder is

port (A, B: in std_logic_vector (3 downto 0);

Cin: in std_logic;

S: out std_logic_vector (3 downto 0);

C4 : out std_logic);

end adder;

architecture Carry-LA of adder is

-- Assume 7.0-ns propagation delay for all gates

signal Cl, C2, CJ : std_logic;

signal P, G: std_logic_vector (3 downto 0);

constant delay_gt: time := 7 ns;

begin

G(O) < = A(O) and B(O) after delay _gt;

G(l) <= A(l) and B(l) after delay_gt;

G(2) < = A(2) and B(2) after delay _gt;

· G(J) < = A(J) and B(J) after delay _gt;



P(O) < = A(O) or B(O) after delay _gt;

P(1) < = A(1) or B(1) after d elay_gt;

P(2) < = A(2) o r B(2) after d elay _gt;

P(3) < = A(3) or B(3) after delay _gt;

C1 < = G(O) or (P(O) and Cin) after 2•ctelay _gt;


C2 <= G(1) or (P(1) an d G(O)) or (P(1) and P(O) and C in) aft e r 2*de lay_gt;

C3 < = G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(O)) or (P(2) and P(1)

and P(1) and Cin) afte r 2*delay_gt;

C4 < = G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1)) or (P(3) and P(£)

and P(1) and G(O)) or (P(3) and P(2) and P(1) and P(O) and Gin) after 2•ctelay _gt;

S(O) < = (P(O) xor G(O)) xor Gin after delay _gt;

S(1) < = (P(1) xor G(1)) xor C1 after d elay _gt;

S(2) < = (P(2) xor G(2)) xor C2 afte r delay _gt;

S(3) < = (P(2) xor G(2)) xor C3 after delay _gt;

end Carry-LA;

Verilog 4-Bit Carry-Lookahead Adder Description.

modu le Carry_LA (A, B, C in, S, C4);

input (3:0) A, B;

input Cin;

output (3:0) S;

output C4;

/* Assume 7.0 -ns propagation delay for all gates

including a 3-input xor. •I

wire Ct, C2, C3;

wire 13:0) P , G;

time d elay _gt = 7;

assign #delay_gt G(O) = A(O) & B(O);

assign #delay_gt G(1) = A (1) & B(1);

as sign # delay_gt G (2 ) = A(2) & B(2);

assign #delay_gt G (3) = A(3) & B(3);

assign # delay _gt P(O) = A(O) I B(O);

assign # delay_gt P(1) = A(1) I B(1);

assign # d elay_gt P(2) = A(2) I B(2);

assign # d elay_gt P(3) = A(3) I B(3);

assign #(2•ctelay_gt) C1 = G(O) I (P(OJ & Gin );

assign #(2•ctelay_gt) C2 = G(1) I (P(l) & G(O)) I (P(1) & P(O) & Cin};



assign #(2*delay_gt) CJ = G(21 I {P(21 & G(lll I (P(21 & P(ll & G(O))

I (P(21 & P il l & P(OI & Cin);

assign #(2*delay_gt) C4 = G(JI I (P(JJ & G(2)) I (P(JI & P(2] & G(lll

I (P(J I & Pi21 & Pi l l & GiOll

I (PIJ I & P121 & P(1) & P(O) & Cin);

assign #delay_gt S(OJ = (P(OI " G(O)) " Cin;

assign #delay_gt Sill =(Pill " G(1)) " Cl;

assign #delay_gt Sl21 = (P(21 " G(2)) " C2;

assign #delay_gt S(JI = (P(JI " G(J)) " CJ;

endmodule

A __ o_o_o_o _________ l.__10_1_1 ____ _

0 __ 0_0_0_0 _________ ~!0_1_1_0 ____ _

Cin

Sum 0000 0010

Cout

i- 4 x 14 = 56 ns

(a) Ripple carry adder

A 0000 ! 1011

B 0000 I 0110

Cin -------------'

s 0000 0010

- >- 4 x 7 = 28 ns

(b) Carry - lookahead adder

Fig. 2.19 Simulation waveform for 4-bit adder with a 7 ns gate delaYcopyrighted material

Fundamentals of HDL 2 . 26 Data-Flow Description

The Fig. 2.19 shows the simulation waveform for a 4-bit ripple carry and carry lookahead adders. In both the cases gate delay is considered as 7 ns. To calculate the worst delay, i.e., maximum delay, the values for the inputs A, B and Cin are taken as A = 1011, B = 0110 and Cin = 1. These values cause a change in all the carry-out signals. In Fig. 2.19 (a), the total delay is 56 ns. Since there are four one--bit adders, and each has a worst delay of 14 ns (two XOR gates). Th.is total delay equals to the number of 1-bit adders times the delay of one 1-bit adder.

In Fig. 2.19 (b), the total delay is 28 ns, which is 4 times the delay of a single gate (7 ns). On increasing the number of input bits of the lookahead adder, the total worst delay will remain same, i.e., 28 ns.

Review Questions

1. List tlte higlllights of data-flow description.

2. Explain the str11ct11re of the data-flow description with the help of example.

3. Explain the signal declarntion and assignment statements used in VHDL and Verilog.

4. Explain the steps in tlte execution of assignment statements.

5. Explain tlte constant declaration and assignment statement in VHDL and Verilog.

6. Write a VHDL and Verilog description of 4 "1 multiplexer.

7. Write a VHDL and Verilog description of 3 : 8 decoder wit/1 active low enable input.

8. Explain /row gate delays are included in the VHDL and Verilog description.

9. Compare lite worst case delays of 4-bit ripple carry adder and 4-bit carry-looka/1ead adder wit/1 tire help of simulation waveform.

DOD


Behavioral Description

3.1 Behavioral Description Highlights

• The behavioral system describes the system by showing how the outputs behave according to changes in the inputs.

• While describing in the behavioral style, it is not necessary to know the logic diagram of the system; however, it is required to know how the output behaves in response to change in the input.

• In VHDL, process is the main behavioral description statement. In Verilog, always and initial are the two main behavioral description statements.

• In VHDL, the statements inside the process are sequential. In Verilog, all statements are concurrent.

3.2 Structure of the HDL Behavioral Description

The listing 3.1 shows the behavioral description fur half-adder. Referring the VHDL description we can see that, the entity half-adder has two input ports A and B, and two output ports Cout and Sum. Here, ports are of type bit; this type is defined in VHDL and hence it is not necessary to include IEEE library in the description. If ports are of type std_Iogic then it is must to include IEEE library in the description.

We have already seen that the keyword in the behavioral description is process. Every behavioral description has to include in the process body. The process (A, B) is a concurrent statement; so its execution is initiated by the occurrence of an event. The ports A and B included in the process (A, B) statement is called sensitivity list. Any change in the state of any element of the sensitivity list is treated as an event. The process is activated (initiated) only if an event occurs; otherwise process remains inactive. If the process has no sensitivity list, the process is executed continuously.

(3 - 1)


Fundamentals of HDL 3-2 Behavioral Description

Ill- Listing 3.1 : Example of an HDL behavioral description-VHDL and Verilog.

VHDL Behavioral Description of Half Adder

entity half_adder is

port ( A : in bit;

B : in bit;

Sum : out bit;

Cout : out bit);

end half_ adder;

architecture adder of half_ adder is

begin

process (A, B)

begin

Sum < = A xor B after 10 ns;

Cout < = A and B after 10 ns;

-- signal-assignment statement 1

signal-assignment statement 2

end process;

end adder;

w ith 10 nanoseconds delays.

Verilog Behavioral Description of Half Adder

module half_adder (A, B, Sum, Cout);

input A;

input B;

output Sum;

output Cout;

reg Sum, Cout;

always @(A, B)

begin

#10 Sum = a A b ;

#10 Cout = a & b ;

end

endmodule

/* Since Sum and Cout are outputs and they are written

inside "always," they should be declared as reg *I

11 A is a bitwise xor logical operator.

11 & is a bitwise logical "and" operator

/* The above two statements are procedural

(inside always) signal-assignment statements with

10 simulation screen units delay• I



The statements included in the process body are executed sequentially : As mentioned in the chapter two, that a signal assignment statement has two phases : calculation and assignment. Here, the sequential execution means sequential calculation. This means that the calculation of a statement is done after the calculation of the previous statement; however the calculation of the statement wi ll not wait until the previous statement is assigned.

The Fig. 3.1 shows the simulation waveform for half-adder. Here at T = TO, A changes from 0 to 1, while B stays at 1. This change constitute an event on A, which in turn activates the process. The statement 1 is calculated as Sum = (A XOR B), i.e. Sum = (1 XOR 1) = 0. This value of 0 is not assigned to Sum at TO, but rather at TO+ lOns. Statement 2 is also calculated at T2 to give Cout = (A AND B) = (1 AND 1)

= 1. The value of 1 is assigned to Cout at TO + 10 ns.

A ------'

B ~--------------~

Sum ---------

Cout ~-------'

r r TO

~ "' c 0 0

T1

0

"' "' c 0 ~

~

Fig. 3.1

Referring to Verilog description of half-adder we can see tha t keyword always is used in the behavioral description. The always body includes concurrent statements, the same as in the data-flow descrip tion. It is important to note that the signal which appears in the always body must be dedared as a register (reg).


Fundamentals of HDL 3.4 Behavioral Description

3.3 The VHDL Variable Assignment Statement

We can use variables inside the processes. This is illustrated by the following statements :

process (X) variable A, B : bit ;

begin

stl: A :=X;

st2: B := not A;

st3: 01 < = A; end process ;

•· variable declaration statement

·· Variable assignment statement

·· Variable assignment statement

use < = assignment operator

Variable assignment statements, as in C language, are calculated and assigned immediately with no delay time between calculation and assignment. The assignment operator : = is used assigned values to the variables instead of assignment operator <=.

One important thing to note that we can label any statement in the VHDL such as stl, st2 and st3 in the previous description.

3.4 Sequential Statements

The various forms of sequential statements are associated with behavioral description. These statements have to appear inside process in VHDL, or inside always or initial in Verilog. These statements execute in the order in which they appear. Let us study these sequential statements.

3.4.1 IF Statement

An IF st:il~ment selects a sequence of statements for execution based on the value of a condition. The condition can be any expression that evaluates to a Boolean value.

VHDL Syntax :

if (Boolean Expression) then

statement 1;

statement 2;

else

statement x;

statement y;

end if;


Fundamentals of HDL

Example :

if (EN = '1') then

Q := St;

else

Q:=S2;

end if;

Verilog Syntax :

if (Boolean Expression)

begin

3.5 Behavioral Description

statement 1;

statement 2;

I • For only one statement, begin and end can be omitted •I

end

else

begin

statement x ;

Statement y;

end

Example:

if (EN== 1)

Q= Sl;

else

Q= S2;

!• For only one statement, begin and end can be omitted * I

In the above examples, if EN = 1 (high), then the value of Sl is assigned to Q; otherwise, the value of 52 is assigned to Q.

11* Example 3.1 : Execution of IF as a D latch

VHDL

if Clk = '1' then

Q: = D;

end if;


Fundamentals of HDL

Veri log

if (Clk == 1)

begin

O = D:

end

3-6 Behavioral Description

if Clk is J (high), then the value of D is assigned to output Q. If Clk is not high, Q retains its current value, thus simulating a latch.

m• Example 3.2 : Execution of IF as ELSE-IF

VHDL syntax :

If (Boolean Expression 1) then

statement 1 ; statement 2; ...

e lsif (Boolean Expression 2) then

statement x; statement y; ...

else

statement a ; statement b; .. .

end if;

Example:

process (a, b , en)

begin

if en ='00' then

c < = a;

elsif en='Ol' then

c <= b;

else

c < = 'O';

encl if;

enrl process;

Veri log Syntax :

if (Boolean Expression 1)

begin

statement 1; statement 2; . ..

end

else if (Boolean Expression 2)

begin

statement x: statement y; .. .


Fundamentals of HDL

end

else

begin

statement a ; statement b; .. .

end

Example

always @ (a, b , en)

begin

if (en == OJ

c = a;

else if (en = = 1}

c = b;

else

c = 0;

end


Here 'en' signal is in sensitivity list. If en = 00, signal 'a' is assigned to output 'c' . Similarly if 'en'= '01' then 'b' is assigned to 'c' else 'O' value is assigned to 'c' .

111• Example 3.3 : Behavioral description of 2 x 1 multiplexer using IF ELSE

VHDL 2x1 Multiplexer Using IF-ELSE

library ieee;

use ieee.std_logic_l 164.all;

entity mux2 x 1 is

port (DO, Dl, S, Enbar: in std_logic;

Y : out std_ logic);

end mux2 x 1;

architecture MUX of mux2 x 1 is

begin

procesa iC, DO. Dl, Enbar)

variable temp : std_logic;

.. S, DO, Dl and Enbar are the sensitivity list of the

process.

.. It is common practice in behavioral description to

use variable(s) rather than signal(s). This is done

to avoid any timing errors that may arise due to

the sequential execution of s ignal statements.


Fundamentals of HDL

begin

if Enbar = 'O' then

if S = '1' then

temp := Dl;

else

temp:= DO;

end if;

Y < = temp;

else

y <= 'Z';

end if;

end process;

endMUX;

3-8

Verilog 2x1 Multiplexer Using IF-ELSE

module mux2 x 1 {DO, D1, S, Enbar, Y);

input DO, D1, S, Enbar;

output Y;

reg Y;

always @ (S, DO, D1, Enbar)

begin

if (Enbar == 1)

Y = 1'bz;

else

begin

if {S)

y = D1;


/* This is a procedural assignment. Procedural assignments

are used to assign values to variables declared as regs

(as Y here in this module). Proc,edural statements have to

appear inside always, blocks, initial, tasks, or functions •I

else

Y = DO;

end

end

endmodule



11.. Example 3.4 : Behavioral description of a 2x1 multiplexer using ELSE IF-VHDL and Verilog

VHDL 2x1 Multiplexer Using ELSE-IF

lihmry ieee;

use leee.lltd_logic _ 1164.all;

entity mux2 x 1 is

port ( DO, D1, S, Enbar : In std_logic;

Y: out std_logic);

end mux2X1;

architecture MUX of mux2x1 hi

begin

process (S , DO, D1, Enbar)

-- S, DO, D1 and Enbar are the sensitivity list of the process.

variable temp: std_logic;

begin

If Enbar = 'O' and (S = '1' ) then

temp := D1;

elslf Enbar = 'O' and (S = 'O' ) then

temp := DO;

else

temp := 'Z';

end If;

Y <=temp ;

end process;

end MUX;

-- 'Z' represents High impedance state

Verilog 2x1 Multiplexer Using ELSE-IF

module mux2x1 (DO, D1, S, Enbar, Y);

Input DO, D1, S, Enbar;

output Y;

reg Y;

always @ (S, DO, D1, Enbar)

begin

If (Enbar ==O & S == 1)

begin

Y = DO;

end

else If (Enbar = = O & S = = 0)


Fundamentals of HDL 3 -10 Behavioral Description

y = 01;

else

Y = l'bz;

end

endrnodule

II b represents binary and z represents high impedance state

3.4.2 Signal and Variable Assignment

There is a difference betwe~n the execution of signal assignment statement and variable assignment statement. We know that signal assignment statement executes in two phases : calculation and assignment. For signal, actual assignment of new value is delayed by the propagation delay. On the other hand, when we use variable assignment statements, variables acquire their new values instantaneously. Due to this difference in two assignments, simulation result may be different if \..re use signals instead of variables. This is illustrated in the example 3.5.

n-. Example 3.5 : Behavioral description of a latch using variable and signal assignment.

The Fig. 3.2 shows the logic symbol for D latch. It has input (D), output Q and Qbar and active high enables input (En). When En is high, the output Q follows input D and Qbar is always the invert of Q.

D

En En

Fig. 3.2 D-latch

... Listing 3.2 : VHDL code for behavioral description of D-Latch using variable ·· assignment statements -

entity DLatch_ var is

port ( D, En: in bit;

Q, Obar : out bit);

end DLatch_var;

architecture DL _Var of DLatch _var is

begin

VAR : process (D, En)

variable temp1, temp2 : bit;

begin

if En = '1' then

templ := D;

temp2 :=not templ;

-- Variable assignment statement.

-- Variable assignment statement.


Fundamentals of HDL

end if;

Q <= templ;

Obar < = temp2;

end process VAR;

end DL_Var;

3 -11 Behavioral Description

-- Value of templ is assigned to Q

-- Value of temp2 is assigned to Obar

... Listing 3.3 : VHDL code for behavioral description of D-Latch using signal-assignment statements

entity DLatch_sig ls

port ( D, En : in bit;

Q : buffer bit;

Obar : out bit);

end DLatch_sig;

-- Q is declared as a buffer because it is an

input/output signal it appears on both the left and right hand sides

of assignment statements.

architecture DL_sig of DLatch_sig is

begin

process (D, En)

begin

if En = '1' then

Q <= D;

Obar < = net Q;

end if;

end process;

end DL_sig;

signal assignment

signal assignment

... Listing 3.4 : Verilog code for behavioral description of a D-Latch module D _latch (D, En, Q, Obar);

input D, En;

output a, Obar;

reg Q, Obar;

always @ (D, En)

begin

if (En == 1)

bt'gin

O = D;

Obar= - Q;

end


Fundamentals of HDL

end

endmodule

3 -12 Behavioral Description

The Table 3.1 gives the comparison between signal and variable.

Parameter Signal Variable

Assignment operator <= -Utility Represents circuit Represents local information

interconnects (wires)

Scope Can be global i.e. seen by Local, i.e. it is visible only entire code inside the corresponding

process, function or procedure.

Behavior In sequential code, the value The value is assigned is assignment after some immediately. delay.

Usage In a package, entity or Only in sequential code, i.e., architecture. In an entity, all in process, function or ports are signals by default. procedure .

Table 3.1 Comparison between signal and variable

The Fig. 3.3 shows the simulation waveform of D latch using variable assignment statement. This waveform correctly describes D-latch. The Fig. 3.4 shows the simulation waveform of D latch using signal assignment statement. As shown in the Fig. 3.4, at T = 50 ns, En changes from 0 . to 1, and D is 1 at T = 50 ns. Therefore, new value for Q is calculated as · 1; however, it is assigned at T = 50 + ti. Since at T = 50 ns, value of Q is still 0, Qbar is calculated as 1 using old value of Q.

0

En ---ii A -:-

Q

Obar

0

I

50

L

100 150 200 250 300

--- limens

Fig. 3.3 Simulation waveform of D latch using variable assignment statement


Fundamentals of HDL 3·13 Behavioral Description

D

En

Q

Obar

0 50 100 150 200 250 300

--• Tlmens

Fig. 3.4 Simulation waveform of D latch using signal assignment statement

3.4.3 Case Statement

The case statement is a special multi-way decision statement that tests whether an expression matches one of a number of other expressions, and branches accordingly. It has following syntax :

VHDL

case (control-expression) is when test value or expression 1 =>statements 1;

when test value or expression 2 => statements 2;

when others => statements n; end case;

Verilog

case (control-expression)

test value 1 : begin statements 1;

en d

test value 2 : begin statements 2;

end

default :

endcase

begin default statements;

end

The expression value may be expressed as single value, or as a range of values or as a value of specified expression. The statement when others (VHDL) or default (Verilog) can be used to guarantee that all conditions are covered. Use of multiple when others or default statements in one case statement is illegal.


Fundamentals of HDL'

Example :

VHDL

case option is

when "00''. => temp:= a + b;

when "01" => temp := a - b;

w hen ' 10" => temp:= a• b ;

when others =>temp : = a I b;

end case:

Ve rilog ., ....

case option

2' bOO : temp = a + b;

2' bOl : temp = a - b ; . .. . 2' b l O: temp = a* b;

default : temp = a I b;

endcase

3· 14 Behavioral Description

In above example, the control is option. If option = 00, then temp = a + b; if • option = 01, then temp = a - b; if option = 10, then temp = a • b; if option = 11 (others or default), then temp = a I b;

3.4.4 Comparison between CASE and IF Statement

IF statement produces priority encoded logic.

Example :

process (sel, a, b, c , d)

begin

if sel = '00' then

op <=a;

elsif sel = '01' then op < =b;

elslf sel = '10' then

op < = c; e lse op < = d;

end If; .

. ,;~md process;

· Here, .priority encoded logic means firstly the IF statement executes sequentially, so depending on the first IF condition that particular input is connected to output. Next depending on the second IF condition, the another input is passed to output.



According to this logic, for this example, three multiplexer are generated by tool. So in this case hardware is more so the delay generated by logic gates is more; so the. speed is reduced.

The case statement produces parallel logic. Here, in case statement depenping on the value of "sel" one of the four inputs is passed to the output. So a single multiplexer of 4 inputs with two select lines and one output is generate_d by a tool. So the generated hardware is less, so the delay by logic gates is less; -so the speed is high.

Example:

process (sel, a, b, c, d)

begin

case sel is

when '00' =>op<= a;

when '01' = >op < = b:

when '10' = >op < = c;

when others =>op<= d;

end case;

end process;

u• Example 3.6 : Behavioral description of a positive edge triggered JK flip-flop using the case statement

Fig. 3.5 (a) Clocked JK flip-flop

On J

0 0 J 0 0 0

0 1 0 1 CP

1 0 1 0

K ~

1 1 1 1

Fig. 3.5 (b) Logic symbol

The Fig. 3.5 shows the clocked JK flip-flop, loi:;:c symbol and truth table for clocked edge tr iggered or pulse triggered JK flip-flop.

We know that, in case of pulse or edge triggering the flip-flop changes state either at the positive ·edge (rising edge) or at the negative edge (Falling edge) of the clock pulse and is-sensitive to its inputs only at th,is trapsition of the

K On•1

0 0 J K On+1

1 0 0 1 1 1

0 0 On

0 1 0

0 1 1 0 0 1

1 0 1

1 1 . On

1 0

Fig 3.5 (c) Truth table


Fundamentals of HDL 3·16 Behavioral Description

clock. Fig. 3.6 shows the input and output waveforms for positive edge triggering JK flip-flop.

CP

J --. ..... ..

K_J

a--, ... · __ ___. Fig. 3.6 Input and output waveforms for positive edge triggered JK flip.flop

Looking at the truth table for JK flip-flop and simplifying Qn+I function by K-map we get the characteristic equation for JK flip-flop as Qn+I "' JQn + KQ n. This is

illustrated in Fig. 3.7.

Fig. 3.7 Characteristic equation for JK flip-flop

~ Listing 3.5 : HDL code for a positive edge-triggered JK flip-flop using the case :;tatement-VHDL and Verilog.

VHDL Positive Edge-Triggered JK Flip-Flop Using Case

library leee;

use leee.std_logic_1164.all;

entity JK_FF ls

port( JK : In bit_veetor (1 dow nto OJ;

elk : in std_ logie;

a. Obar : out b it);

end JK_FF;

arctiltecture Flip_Flop of JK_FF ls

begin

Pl : process (elk)


Fundamentals of HDL

variable templ, temp2: bit;

begin

if rising_edge (elk) then

case JK Is

3 -17

when ' 01" =>tempt:= 'O';

when 'tO" => templ := 't';

when ·oo· = >tempt:= tempt;

when "11' =>tempt := not tempt;

end c.ase;

Q <= tempt;

temp2 := not tempt;

Obar < = temp2;

end if;

end proc.ess Pt;

end Flip_Flop;

Verilog Positive Edge-Triggered JK Flip-Flop Using Case

module JK_FF (JK, c.lk, Q, Obar);

input (t:O( JK;

input c.lk;

output Q, Obar;

reg Q , Obar;

always @ (posedge c.lk)

begin

c.ase (JK)

2'd0: Q = Q;

2'dt: Q = 0;

2'd2: Q = 1;

2'd3: Q = - Q;

endc.ase

Obar=- Q;

end

endmodule


n'* Example 3.7 : Behavioral description of a 3·bit up counter A counter is a register capable of arriving at its clock input. For up counters, the

next state is the increment of the present state. For example, if the present state is 010, then the next state is 011. For down counters, the next state is the decrement of the present state. A 3-bit up counter counts from 0 to 7, i.e., it is a mod 8 counter.


Fundamentals of HDL 3 -1 8 Behavioral Description

The Fig. 3.8 shows the logic symbol and excitation table for 3-bit counter. It has two inputs : elk and Reset (active high). On the positive edge of the elk (Clock) input counter increments only if Reset input is 0 (Low); otherwise counter output is reset to 000.

elk

Reset

3 . bit counter

(a) Logic symbol

AO A1

A2

elk Reset Present (Clock) state

t H xxx I L 000 I L 001 I L 010 I L 011 I L 100 I L 101 I L 110 I L 111

(b) Excitation table

Fig. 3.8

Next state

000 001 010 011 100 101 110 111 000

.,.. Listing 3.6 : HDL code for a 3-bit binary counter using the case statement.

VHDL 3-Bit Binary Counter Case S~tement Description

library ieee;

use ieee.std _logic_ 1164.all;

entity CT_ Case is

port ( elk, Reset : in std _logic;

0: buffer std_logic_vector (2 downto O));

end CT_Case;

architecture Counter_3b of CT_case is

begin

counter : process(clk)

variable temp: std_logic_vector (2 downto 0) := "011";

-- 011 is the initial value, so the counter starts from 100

begin

if rising_ edge (elk) then

if Reset = 'O' then

case temp is

when "000" = >temp:= "001';

when "001" =>temp:= "010";

when "010" = >temp:= "011' ;



when '011" = > temp := ' 100";

when '100' = > temp:= ' 101";

when ' 101" =>temp := ' 110";

when '110" = >temp := '111";

when "111" =>temp:= ' 000";

when others = > temp : = ' 000';

end case;

else

temp : = "000';

end if;

end if;

0 <=temp;

end process counter;

end counter_3b;

Verilog 3-Bit Binary Counter Case Statement Description

module CT_Case (elk, Reset, Q);

input elk, Reset;

output (2:0) O;

reg (2:0) O;


initial r The initia l procedure is to force the counter to start

Q = 3'b010;

always @ (posedge elk)

begin

if (Reset = = 0)

begin

case (Q}

3'd0 : Q = 3'd1;

3'd1: Q = 3'd2;

3'd2 : Q = 3'd3;

3'd3 : Q = 3'd4;

3'd4 : 0 = 3'd5;

3'd5 : 0 = 3'd6;

3'd6 : Q = 3'd7;

3'd7 : Q = 3'd0;

endcase

end

else

from initial count q = 011 •I

11 d represents decimal value


Fundamentals of HDL

I Q = 3'b000;

end

endmodule

3.4.4.1 Verilog Casex and Casez


Verilog has another two types of case : casex and casez. Casex ignores the don't care (x) values of control expression w.hereas casez ignores the high impedance in control expression values. For example, in

casex (I)

4bOXX1 : 0 = 1'b0;

4'b1XXO : 0 = 1'b0;

default : 0 = t'bz;

endcase;

All occurrences of X are ignored. Thus, output 0 is 0 when least significant bit of I is 1 (high), the output 0 is 1 when most significant bit of I is 1 (high) and otherwiJ;e output is in high impedance state.

Let us see the example of casez : case z(l)

4'bzzz1 : 0 = 1' bl;

4'bzzz0 : 0 = 1' bO;

default : 0 = l'bz;

Here, 0 is 1 if, and only if the least significant bit of I is 1, 0 is 0 if and only if the least significant bit of I is 0 and otherwise output 0 is in high impedance state.

,,._. Example 3.8 ; Verilog description of a priority encoder using casex.

A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if two or more inputs are equal to 1 at the same time, the input hdving the highest priority will take precedence.

Table 3.2 shows truth table of 4-bit priority encoder.

Inputs Outputs

Do D1 D2 03 Y1 Yo v

0 0 0 0 x x 0

1 0 0 0 0 0 1

x 1 0 0 0 1 1

x x 1 0 1 0 1

x x x 1 1 1 1

Table 3.2 Truth table of 4-bit priority encoder


Fundamentals of HDL 3 - 21 Behavioral Description

Table 3.2 shows 0 3 input with highest priority and 0 0 input with lowest priority. When 0 3 input is high, regardless of other inputs output is 11. The 0 2 has the next priority. Thus, when 0 3 = 0 and 0 2 = 1, regardless of other two lower priority input, output is 10. The output for 0 1 is generated only if higher priority inputs are 0, and so on. The output V (a valid output indicator) indicates, one or more of the inputs are equal to 1. If all inputs are 0, V is equal to 0, and the other two outputs (Y1 and Y0) of the circuit are not used .

._ Listing 3. 7 : Verilog description for a 4-bit priority encoder. module Encoder (D. Y);

input (0:3) D;

output (1:0) Y;

reg (1:0) Y;

always @ (D)

begin

casex (D)

4'b1000 : y = 2'b00; v = l 'bl

4'bx100: Y = 2'b01; V = 1'b1

4'bxxl0 : Y = 2'b10; V = 1'b1

4'bxxxl : Y = 2'b l 1; V = l 'bl

default : Y = 2'bzz; V = l'bO

endcase

end

endmodule

3.4.5 Loop Statement

II DO-D3 = 0000

Loop is a sequential statement. It includes a sequence of statements that is to be executed repeatedly, zero or more times. The number of repetitions is controlled by the range of an index parameter. The loop statement should be written inside process in VHDL or inside always or initial in Verilog.

3.4.5.1 For-Loop Statement

VHDL for loop

The general syntax for a for-loop is : For index (iteration scheme) loop

statementl; statement2; statement3;

end loop


Fundamentals of HDL

Example;

For i in 1 to 10 loop

i_squared(i) := i • i;

end loop;

3 · 22 Behavioral Description

This for loop executes 10 times whenever execution begins. Its functior;l is to calculate the squares from 1 to 10 and insert them into the i_squared signal array. The index variable i starts at the leftmost (lower) value (1) of the range and is incremented until the rightmost (higher) value (10) of the range. In each iteration index is incremented by 1. When the value of index is greater than the higher value, the loop is terminated.

In some languages, the loop index (in this example, i) can be assigne9. a value inside the loop to change its value. VHDL does not allow any assignment to the loop index. VHDL locally declares the index; it is not necessary to declare variable i explicitly in the process, function or procedure. If another variable of the same name exists in the process, function or procedure, then these two variables are treated as separate variables.

We can use downto cause to create a descending range. Here is the example : for i in 10 downto 1 loop

i_squared (i) := 1 • 1;

end loop;

In this case, the iteration index (i) is decremented by l in each iteration.

Verilog for loop

The general syntax f9r a for-loop is : for (initial_ assignment; condition; step-assignment)

beg'.:.~

statementl; statement2; statement3; .. ....

end

Note : for single statement in the for loop we can omit begin and end.

Example:

integer i;

for (i = 1; i < = 10; i = 1 + 1)

begin

i_squared Iii = i • i;

end

In the above example, the initial_assignment (i = 1) specifies the initial value of the loop index. The condition specifies the condition when loop must be terminated. As long as the condition is true, the statements in the loop are executed. The step-assignment (i = i + 1) specifies how to modify index; it can be incremented or decremented.



3.4.5.2 While-Loop Statement

The general syntax of while-loop in VHDL and Verilog is : while (condition)

statementl; statement2; statement3; ...... .

end


This loop executes all the statement written in the while loop body as long as the condition is true. When condition is false, program exits the loop.

VHDL while-loop

Count: = O;

Result := O;

While (Count < 10) loop

Count: = Count + 1;

Result : = ·Result + Count;

end loop;

Verilog While-Loop

Count= O;

Result = O;

While (Count < 10)

begin

Count = Count + 1;

Result = Result + Count;

end

-· Executes loop till count is 9

11 Executes loop till count is 9

Note : Instead of direct value we can use variable to specify the termination condition. For example, we can write, while (Count < x). In this case, loop is executed till value of Count is less than value of x.

3.4.5.3 Verilog Repeat

In Verilog, the repeat statement executes the loop for fixed number of times. It cannot be used to loop on a general logical expression, i.e., no condition is allowed in repeat.

Example :

i = O; Result = O;

repeat (10)

begin

Result = Result + i;

end

The above loop is executed 10 times.


Fundamentals of HDL 3. 24 Behav!oral Description

3.4.5.4 Ve rilog Fonive1·

The syntax for forever-loop is:

Forever statement;

This loop statement continuosly executes the statement. It can be exited by use of the disable statement. It is commonly used to generate clock signal.

Example :

initial

begin

clock = 1 'bO;

forever # 10 clock = -clock;

end

In this example, clock first gets initialized to 0 and then toggles every 10 time units.

3.4.5.5 VHDL Next and Exit

The VHDL supports, two sequential statements next and exit associated with the loop. The exit causes program to exit the loop whereas next causes the program to jump to the end of the loop, skipping all statements written between next and end loop. The index is incremented and if its value is still within the range of the loop, the loop is repeated, otherwise the program exits the loop.

process (A, B}

constant max_limit: integer := 100;

begin

for i in 0 to max_limit loop

If (done(i) = true} then

next;

else

done(i} : = true;

end if; mul(i) < = A(i) • B(i);

end loop;

end process;

In the above example, the for loop multiplies the numbers in arrays A and B and puts the results in array mu!. This behavior continues whenever the flag is in array done is not true. If the done flag is already set for this value of index i, then ·the next statement is executed. It skips the further statements and goto next iteration. If value of i is still within the range of loop i.e. less than max_limit. The loop is repeated.



,,_. Example 3.9 : Behavioral description of ones counter This is behaviorai description of the circuit which counts the number of 'l's in a

binary vector.

VHDL ones counter description

llbrary ieee;


entity count_ ones is

port (Din : in std_logic_vector (7 downto 0);

ones : out integer range 0 to 8);

end count_ ones;

arehltecture count of count ones ls

begin

process (Din)

variable temp : integer range 0 to 8;

begin

temp:= O;

for i in O to 7 loop if(Din(i) = '1 ') then

temp: = temp+ 1;

end if;

end loop;

ones < = temp;

end process;

end count;

Verilog ones counter description

module count_ ones (Din, Ones)

input (7 : OJ Din;

output (2 : OJ ones;

reg 12 : OJ ones;

integer i;

initial

ones = 3'b000;

always @ (Din)

begin

for (i = O; i < 8; i = i + 1)

begin

if (Din [iJ = = 1)


Fundamentals of HDL

begin

ones = ones + 1;

end

end

end

endmodule

3 - 26

n1• Example 3.10 : Factorial using behavioral description A factorial of a given number is calculated as

N! = N(N - 1) (N - 2) (N - 3) .. .. . 1.

For example, 5! = 5 x 4 x 3 x 2 x 1 = 120


In this N and result of factorial are the positive integers thus we can declare them as natural.

• Listing 3.8 : HDL code for calculating the factorial of positive integers~VHDL and Veri log

VHDL : Calculating the Factorial of Positive Integers

entity factorial is

port( N : in natural;

Y : out natural);

end factorial;

archit ecture fact of factorial is

begin

process (N)

variable i, j : natural;

begin

i := 1;

j := 1;

while (j < = N) loop

i : = i • j;

j := i + 1;

end loop;

y <= i;

end proce11;

end fact;



Verilog : Calculating the Factor ial of Positive Integers

m odule factorial (N, Y);

input [5:0) N;

output [15:0) Y;

reg [15:0) Y;


/* Since Y is an output, and it will appear inside "always," then

Y has to be declared "reg" *I

integer i;

always@ (N)

begin y = l ;

II Y can be written as 16'b0000000000000001or 16'd l.

i = l;

while (i < = N)

begin

end

end

endmodule

Y = i • Y;

i = i + l;

Case study : Booth Algorithm

A powerful algorithm for signed-number multiplication is a Booth's algorithm, which generates a 2n-bit product and treats both positive and negative numbers uniformly.

This algorithm suggest that we can reduce the number of operations required for multiplication by representing multiplier as a difference between two numbers. For example, multiplier 0 0 1 1 1 0 (14) can be represented as follows.

0 1 0 0 0 0 (16)

- 0 0 0 0 1 0 (2)

0 0 1 1 1 0 (14)

Therefore, the product can be computed by adding 24 times the multiplicand to the 2's complement of 21 times the multipliGand. In simple notations, we can describe the sequence of required operations by recoding the preceding multiplier as

0+100 - 10



In general, for Booth's algorithm recoding scheme can be given as :

-1 times the shifted multiplicand is selected when moving from 0 to 1, +1 times the shifted multiplicand is selected when moving from 1 to 0, and 0 times the shifted multiplicand is selected for none of the above case, as multiplier is scanned from right to left.

We have to assume an implied 0 to right of the multiplier LSB. This is illustrated in the following examples.

Example : Recode the multiplier 1 0 1 1 0 0 for Booth's multiplication.

Solution : -

1 0 1 1 0 0 ~ltiplier - 1+1 0-1 0 0 Recoded multiplier

Solution :

Example : Recode the multiplier O 1 1 O O ·1 for Booth's multiplication. -0 0 1 .r-:ultiplier 0 1 1

+ 1 0 -1 0 +1 -1 Recoded multiplier

The Fig. 3.9 shows the Booth's multiplication. As shown in the Fig. 3.9, whenever multiplicand is multiplied by - 1, its 2's complement is taken as a partial result.

Multiplier : O O 1 1 O O Multiplicand : O 1 O O 11.

Recoded multiplier : 0 + 1 0 - 1 0 0

Multiplication :

x

0 0 0 0 0 0

0 0 0 ()' 0 0

0

0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0 0

0 0 0 0

0 0

0 +1 0

0 0 0

0 0 0

0

0 0 0

0

0 0

0

- 1

0

0

Fig. 3.9 Booth's multiplication

0 0

0 0

0

f- 2's complement of the multiplicand

0 0

The same algorithm can be ,used for negative multiplier. This is illustrated in the following example.



Example : Multiply 0 1 1 1 0 (+14) and 1 1 O 1 1(-5).

Solution :

Multiplication :

0 1

0 -1

1

0 1 0

0

0 (+14) Multiplicand

1 (- 5) Multiplier

- 1 Recoded Multiplier

x 0 -1 +1

0

0 -1

0

0

1

0

1

0

0

1

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

O 2's complement of the multiplicand

0 (-70)

The same algorithm also can be used for negative multiplier and negative multiplicand. This is illustrated in the following example.

Example : Explain the following pair of signed 2's complement numbers.

Multiplicand : 1 1 0 0 1 1 (-13)

Multiplier : 1 0 1 1 0 0 (-20)

Solution : 0 0 0

- 1 +1 0 -1 0 0

Multiplication :

0 0

x - 1 +1 0 - 1

Multiplier

Recoded Multiplier

Multiplicand

0 0 Recoded Multiplier ~~~~~~~~~~~~~~~~~~~~~~~~~-

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0 0

0

0 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

<- 2"s complement of the multiplicand

•- 2"s complement of the multiplicand

0 (260)



Hardware Implementation

The Booth's algorithm can be implemented as shown in the Fig. 3.10. The circuit is similar to circuit for positive number multiplication. It consists of n-bit adder, shift, add subtract control logic and four registers, A, B, Q and Q_1. As shown in the Fig. 3.10 multiplier and multiplicand are loaded into register Q and register B, respectively, and register A and Q _1 are initially set to 0.

--- n-bit bus n

Add I Sub Shift, Add

n-Bit Adder and subtract L ____ ....,. __ .!;E;!!n~ab~le;_J-,___-;;:ddj~;t,;;:ctl Control Logic

, , , ,

Add/subtract Enable .___....,... _ __,

Shift Right r----------------

• Initial settings : A - o and 0_1 = O

Fig. 3.10 Hardware implementation of signed binary multiplication

The n-bit adder performs addition of two inputs. One input is the A register and other input is multiplicand. In case of addition, Add/sub line is 0, therefore Cin,;. 0 and multiplicand is directly applied as a second input to the n-bit adder. In case of subtraction, Add/sub line is 1, therefore Cin =1 and multiplicand is complemented and then applied to the n-bit adder. As a result, the 2's complement of multiplicand is added in the A register.

The shift, add and subtract control logic scans bits Q 0 and Q_1 one at a time and generates the control signals as shown in the table 3.3. If the two bits are same (1 - 1 or 0 - 0), then all of the bits of the A, Q, and Q _ 1 registers are shifted to right 1 bit without addition or subtraction (Add/subtract Enable = 0). If the two bits are differ, then the multiplicand ( B-register) is added to or subtracted from the A register, depending on the status of bits. If bits are Q 0 = 0 and Q_1 = 1 then multiplicand is added and if bits are Q 0= 1 and Q . 1= 0 then multiplicand is subtracted. After addition or subtraction right shift occurs such that the leftmost bit of A ~An-I) is not


Fundamentals of HDL 3 - 31 Behavioral De~cription

only shifted into A n-l, but also remains in A n-t · This is required to pres.erve the sign of the number in A and Q. It is known as an arithmetic shift, since it preserves the sign bit.

--Qi Q.1 Add/sub Add/Subtract Enable Shift .

0 0 x 0 1

0 1 0 1 1

1 0 1 1 1

1 1 x 0 1

Table 3.3 Truth table for shift, add and subtract control logic

The sequence of events in Booth's algorithm can be explained with the help of flowchart shown in Fig. 3.11.

= 10

A -A- B

No

A - o 0 .1 - 0

B - Multiplicand Q - Multiplier Count - n

= 11 = 00

Arithmetic Shift Right: A, a. 0_1

Count - Count - 1

= 01

A -A +B

Fig. 3.11 Booth's algorithm for signed multiplication


Fundamentals of HDL 3 . 32 Behavioral Description·

Let us see the multiplication of 4-bit numbers, 5 and 4 with all possible combinations.

CASE 1 : Both Positive ( 5x 4)

Multiplicand (8) +- 0 1 0 1 (5) Multiplier (Q) +- 0 1 0 O (4)

Steps A Q Q..1 Operation

0 0 0 0 0 1 0 0 0 Initial

Step 1 : 0 0 0 0 0 0 1 0 0 Arithmetic shift right


Step 3 : 1 0 1 1 0 0 0 1 0 A +- A-8

1 1 0 1 1 0 0 0 1 Arithmetic shift right

Step 4 : 0 0 1 0 1 0 0 0 1 A +-A+ 8


Result 0 0 0 1 0 1 0 0 = + 20

CASE 2 : Negative Multlplier ( 5 x - 4 )

Multiplicand(8) ... 0 1 0 1 (5) Multiplier (Q) ... 11 0 0 (- 4)

Steps A Q Q_I Operation

0 0 0 0 1 1 0 0 0 Initial


Step 2: 0 0 0 0 0 0 1 1 0 Arithmetic shift right

Step 3: 1 0 1 1 0 0 1 1 0 A +-A - 8



Result : 1 1 1 0 1 1 0 0 = - 20 (2's complement of 20)



CASE 3 : Negative Multiplicand ( - 5 x 4 )

Multiplicand(B) +- 1 0 1 1 (- 5) Multiplier(Q) <- 0 1 0 0 (4)

Steps A Q Q.., Operation

0 0 0 0 0 1 0 0 0 Initial



Step 3: 0 1 0 1 0 0 0 1 0 A.-A-B


Step 4 : 1 1 0 1 1 0 0 0 1 A <- A+B


Result: 1 1 1 0 1 1 0 0 = - 20

CASE 4 : Both Negative ( - 5 x - 4 )

Multiplicand(B) <- 1 0 1 1 (-5) Multiplier(Q) <- 1 1 0 0 (- 4)

Steps A Q Q_, Operation

0 0 0 0 1 1 0 0 0 Initial



Step 3 : 0 1 0 1 0 0 1 1 0 A <- A-B



Result : 0 0 0 1 0 1 0 0 = + 20

.... Listing 3.9 : 4x4-bit booth algorithm-VHDL and Verilog.

VHDL 4 x 4-Bit Booth Algorithm

library leee;

use ieee.std_logic_l 164.all;

use leee.numeric_std.all;

entity Booth is


Fundamentals of HDL 3. 34 Behavioral Description

port ( B, O : in signed (3 downto O);

Result : buffer signed (7 downto 0));

end Booth; -- B : Multiplicand 0 : MUitiplier

architecture Mul Booth of Booth is

begin

process (B, 0)

variable 001 : signed (1 downto O);

variable A : signed (3 downto O);

variable 0_1 : unsigned (0 downto O);

begin

A:= "0000"; 0 _1 := "O•;

for i in 0 to 3 loop

001 := 0(0) & 0_1;

case temp is

when "10" = >A := A-B;

when "01'' =>A :=A + B;

when others = > null;

end case;

0 _1 := 0(0);

0 : = 0 srl 1; -- logical shift 0 of one position to the right

0(3) := A(O);

A := A sra 1; -- arithmetic shift A of one position to the right

end loop;

Result< = A & O;

end process;

end Mul_Booth;

Verilog 4x4-Bit Booth Algorithm

module bo'Jth (B, 0, Result);

input signed (3:0] B, O;

output signed [7:0) Result;

reg signed [7:0] Result;

reg signed (3:0) A;

reg (1:0] 001; .

reg 0_1;

integer i;

always @ (B, 0)

begin

A= 4'b0000;


Fundamentals of HDL

0 _1 = 1'b0;

for (i = O; i < 4; i = i + 1)

begin

001 "' {0(0], 0 _1};

case (001)

2'd2 : A = A - B;

2'd1 : A = A +B;

default : begin end

endcase

3 - 35 Behavioral Description

11 concatenation

0 _1 = O(OJ;

0:=0>>1;

0(3] = A(OJ;

A = A >> l ;

A [7[ = A [6];

11 log ical shift 0 of one position to the right

11 arithmetic shift A of one position to the right

/* The above two statements perform arithmetic shift

in w hich the sign of the number is preserved after

the shift. *I

end Result = {A, O}

end

endrnodule

Review Questions

11 concatenation

1. List tlte l1ighligltts of behavioral description.

2. Explain the structure of VHDL beliaviora/ description.

3. Explain tlte structure of Verilog bel1avioral description.

4. What is sensitivity list ?

5. Write a VHDL and Verilog behavioral description for full-adder.

6. Write a VHDL and Verilog bl!haviora/ description for 4 xl 11111/t iplexer using if-else.

7. Give the comparison between signal and variable assignment in VHDL.

ODO


(3 - 36)

Co y•1 Jht rn 1 I

Structural Description

4.1 Highlights of Structural Description

• When information about the hardware components of the digital system is known we can use structural description.

• It simulates the digital system by describing its logical components such as gates, registers and even processor.

• It is more design specific. For example, if we want to implement the adder, we can specify the type of adder such as ripple adder or carry look ahead adder. This is not the case with behavioral description. In which we can specify the add operation by writing the statement C. = A+ B.

• All the statements in structural description are concurrent. At any simulation time all statements that have an event are executed simultaneously. This means that execution of statements depend on events, not on the order that the statements are placed in the module.

• Basic Verilog package recognizes the gates; however basic VHDL package does not recognize gates. In VHDL, we have include one or more libraries, packages or modules that have the gate description.

4.2 Organization of the Structural Description

The listing shows the VHDL and Verilog structural description for half-adder. In the VHDL description, the entity part is same as that of behavioral description. However, architecture part has two components : declaration and instantiation.

In declaration part all different components used in the system description are declared. For example, following description declares AND gate component.

component and2

port ( 11, 12 : In std_ logic;

01 : out std_logic);

end component;

(4 - 1)


Fundamentals of HDL 4-2 Structural Description

The and2 components has two inputs : 11 and 12 and one output 01. Once the component is declared we can use the same component one or more times in the system description.

The instantiation part of the code maps the generic inputs/outputs to the actual inputs / outputs of the system. For example, the statement and2 port map (A, B, Cout); maps A to input I1 of and2, input B to input 12 pf and2, and output Cout to output 01 of and2. This mapping means that the logic relationship 'between A . B and Cout is the same as between Il, 12 and 01.

.... Listing 4.1 : HDL structural description- VHDL and Verilug

VHDL Structural Description

library ieee;

use ieee.std_logic_1164 .all;


port (A, B : in std_logic;

Sum, Cout: ou t std_logic);

end half_add;

architecture adder of half adder Is

-- Component Declaration

component xor2

port ( 11, 12 : in std_logic;

01 : ou t std_logic):

end component;

component and2

port ( 11, 12 : in s td_!ogic;


end component ;

begin

Xl : xor2 port map (A, B, Sum);

A1 : and2 port map (A, B, Cout );

end adder;

Verilog Structural Description

module system (a, b , Sum, Cout);

input a, b;

output Sum, Cout:

Statements instantiation

xor X1 (Sum, A , B );

and Al (Cout, a , b);

e ndmodule

11 X1 is an ide::itifier. It is optional it can be omitted.

11 A 1 is optional identifier; it can be omitted.



The VHDL part of listing 4.1., does not give the complete code for half_adder. It does not specify the function of the component::' and2 and xor2. To specify and2 as an AND gate or xor2 as an XOR gate, we have to link the entity having the same name as component which specifies the relationship between 11, 12 and 01 as AND gate or XOR gate, respectively. This is illustrated in Listing 4.2.

~ Listing 4.2 : HDL code of half adder-VHDL and V(·rilog

VHDL half_adder description

library ieee;


entity xor2 is

port( I1, 12 : in std_ logic;


end xor2;

architecture xor_gate of xor2 is

begin

0 1 < = 11xor12;

end xor_gate;

library ieee;


entity and2 is

port (Il, 12 : in std_logic; 01 : out std_logic);

end and2;

architecture and_gate of and2 is

begin

01 < = 11and12;

end and_gate;

library iee!!;




Sum, Cout: out std_logic);

end half_adder;

architecture adder of half_adder is

component xor2

port ( Il, 12 : in std _logic;



Fundamentals of HDL

end component;

component and2

port ( 11, 12 : ID std_logic;


end component;

begin

Xl : xor2 port map (a, b, S);

Al : and2 port map (a, b, C);

end adder;

4.4 Structural Description

As mentioned earlier, basic Verilog recognizes logic gates. The Fig. 4.1 ~hows all the gates recognized by the Verilog. Like VHDL, the statements in the structural Verilog are concurrent; they are event driven and their order of appearance in the module is irrelevant.

--t>I- =D- =D- =lD-buf or and xor

-I>- =[>-- =D- :=)~ not nor nand xnor

Fig. 4.1 Built-in gates in Verilog

4.3 Binding

Binding is nothing but the linking of entity to architecture and .coml?onent to entity in the VHDL. In Verilog, the binding means linking of one module to another module.

4.3.1 Binding between Entity and Architecture in VHDL

Refer the listing 4.3. Here the architecture archl is linked (bounded) to entity ent through the predefined word of. Similarly, architecture arch2 is also bounded to entity ent through the predefined word of. As archl and arch2 are linked with entity ent, we can use signals Il, l2 and 01 in both the architectures.

It is important to note that eventhough the architectures archl and arch2 are linked with entity ent; they are not linked (bounded) themselves. Therefore, signal (X) defined in archl is not recognized in arch2 a.nd similarly, the signal (Y) defined in arch2 is not recognized in archl.


Fundamentals of HDL 4.5

.... Listing 4.3 : Binding between entity and architecture. entity ent is

port (11, 12 : in std_logic ;

01 : out s td_logic);

end ent;

architecture arch 1 of ent la

signa l X : std_logic;

end archl;

architecture arch2 of ent 11

signal Y : std_logic;

end arch2;

4.3.2 Binding between Entity and Component in VHDL


The listing 4.4 shows the binding between entity and component. The entity and component can be bounded by their names. U the names of entity and component are same, the component is automatically bounded to the corresponding entity. Here, the component andgate is bounded to the entity andgate because their names are same. Architecture gate is bounded to entity andgate by the of.

Since component andgate is bounded to entity andgate and entity andgate is bounded to architecture gate, the r~lationship between 11, 12 and 01 defined in the architecture gate is visible to the component andgate .

..,. Listing 4.4 : Binding between entity and component. entity andgate ii

port (11, 12 : in std_logic;


end andgate;

architecture g ate of andgate ii

begin 0 1< = 11 and12;

end gate;

entity ent la


sum, cout : out std_logic);

end ent;

architecture arch of eht la

component andgate


Fundamentals of HDL

port (11, 12 : in sto_l0gic;


end component;

begin

andgate port map (A, B, Cout);

end arch;

4 . 5

4.3.3 Binding between Library and Module in VHDL


The listing 4.5 shows the binding between the library ieee to the module in VHDL. Library is a predefined word, ieee is the name of the library, use is a predefined word, and ieee.std_logic_l164.all refers to the part of the library to be bound. This part of the library provides the definition for the standard_logic type.

IJJJ> Listing 4.5 : Binding' tiJtwe'en ·Jibraty ·a'rfo moaule in VHDL. library ieee;

use ieee.std_logic_11'64 .all;

entity' ent is

port (11. 12 : 1n· std_logic; 01 : out std_logic);

en d ent; ·

architeeture arch of ent is

end arch;

The HDL simulator generates a library named work every time it compiles HDL code. We can bound this library to another module by including following statement in the module.

Here, the entity to be bound to the module is andgate; andgate has an · architecture by the name of gate, and aU information in this architecture is visible to the module in which the above use statement is written.

In listing 4.6, the statement :

*

binds the architecture xor2_7 of the entity ent to the component 'XOr.2. Because of this binding, component xor2 behaves as a two-input XOR gate with a propagative delay of 7ns. Similarly, the statement :

Lopynghtcd material

Fundamentals of HDL 4.7 Structural Description

binds the architecture and 2_4 of the entity ent of the component and2. Because of this binding, component and2 behaves as a two-input AND gate with a propagative delay of 4ns.

In listing 4.6, it is assumed that entities ent and half_adder are stored in the same directory, i.e., their path is same. In case of different paths we have to specify the path of the library work in the for all statement.

.,... Listing 4.6 : Binding between a library and component in VHDL -· code to be bound to module half adder

library leee;


entity ent is

port ( Il, 12 : in std_logic;


end ent;

architecture xor2_7 of ent is

begin

01<=11xor12;

end xor2_7;

architecture and2 4 of ent is

begin

01 < = 11 and 12 after 4 ns;

end and2_4;

·· compile the above code and store it in a known location.

··module half_adder

library leee;



port (A, B: in std_logic;

Sum, Cout : out std_logic);

end half_adder;

architecture adder of half_ adder ii

component xor2




fundamentals of HDL

end component;

component and2

port ( I1, 12 : in std_ logic;


end component;

4-8

for all : xor2 use entity work.ant (xor2 _ 7);

for all: and2 use entity work.ent (and2_4);

begin

Xl : xor2 port map (A, B, Sum);

Al : and2 port map (A, B, Cout);

end adder;

4.3.4 Binding between Two Modules in Verilog


The listing 4.7 shows the binding between two modules in Verilog. Here, the statement:

Second MO (Sum[O], Cout[O(, A[O), B(O));

Written in the first module binds secon d module to first module. Accordingly, the relationship between Sum, Cout, A and B is as follows :

• Sum[O] is the output of the two input XOR gate with A[O) and B[O] as the inputs.

• Cout[O] is the output of the two input AND gate with A[O] and B[O] as the inputs.

)Ill> Listing 4.7 : Binding between two modules in Verilog.

m odule first (Sum, Cout, A, B);

input (1:0) A;

input [1:0) B;

output [1:0) Sum, Cout;

second MO (Sum[O). Cout[O], AIOJ, B[O));

second Ml (Sum(l). Cout[1). A[l ), B(l));

endmodule

module second (S, C, Al, Bl);

input Al;

input Bl;

output S, C;

xor (S, A, B);

and (C, A, B);

endmodule



u• Example 4.1 : VHDL code for inverter, AND, OR, XOR, NOR and NANO gates.

.... Listing 4.8 : VHDL code for inverter, AND, OR, NOR, NANO XOR gates -- one input gates ------------------------- ---------------------------------------------- -------------

library ieee; use ieee.std_logic_1164.all;

entity one_ input is

port ( 11 : in std _logic;


end one_ input;

architecture inv _ 4 of one_ input is

begin

01 < = not 11 after 4ns;

end inv_4;

architecture inv _ 7 of one _input is

begin

01 < = not 11 after 7 ns;

end inv_7;

-- inverter with 4-ns delay

-- inverter with a 7-ns delay

-- two input gates ------------------------------------------------------------------------------------library ieee; use ieee.atd_logic_1164.all;

entity two_ input is



end two_input;

architecture xor2_4 of two_input is

begin 01 < = I1 xor 12 after 4ns.; -- 2-input exclusive-or with 4-ns delay

end xor2_4;

architecture and2_4 of two_input is

begin

01 < = I1 and 12 after 4ns;

end and2_4; architecture and2_7 of two_input is

begin

01 < = I1 and 12 after 7 ns;

end and2_7;

-- 2-input and gate with 4-ns delay

-- 2-input and gate with 7-ns delay.


Fundamentals of HDL 4 -10 Structural Description

architecture or2 _ 4 of two_ input la

begin

01 < = 11 or 12 after 4ns; -- 2-input or gate with 4-ns delay

end or2_4;

architecture or2 _ 7 of two_ input is

begin

01 < = 11 or 12 after 7 ns; -- 2-input or gate with 7-ns delay.

end or2_7;

architecture nor2_7 of two_input la

begin

01 < = 11 nor 12 after 7 ns; -- 2-input nor gate with 7-ns delay.

end nor2_7;

architecture nand2 _ 7 of two_ input is

begin

01 <= 11nand12 after 7 ns; -- 2-input nand gate with 7-ns delay.

end nand2_7;

-- three input gates --------------------------------------------------------------~----------------

library ieee;


entity three_input Is

port ( 11, 12, 13 : in std _logic;


end three_input;

architecture and3 _ 4 of three_ input Is

begin

01 < = 11 and 12 and 13 after 4ns; -- 3-input and gate with 4-ns delay.

end and3_4;

architecture and3 _ 7 of three_ input is

begin

01 < = 11 and 12 and 13 after 7ns; -- 3-input and gate with 7-ns delay.

end and3_7;

architecture or3 _ 4 of three_ input Is

begin

01 < = 11 or 12 or 13 after 4ns; -- 3-input or gate with 4-ns delay.

end or3_4;

architecture or3_7 of three_input la

begin


Fundamentals of HDL 4. 11 Structural Description

01 < = I1 or 12 or 13 after 7 ns; -- 3-input or gate with 7-ns delay.

end or3_7;

•• four input gates ------------------------------------------------------------- ------------- -------

library ieee;


entity four_input is

port ( 11, 12, 13, 14 : in std _logic;


emi"four _input;

architecture or4_4 of four_input is

begin

01 < = I1 or 12 or 13 or 14 after 4ns; -- 4-input and gate with 4-ns delay.

end or4_4;

lJJ.. Example 4.2 : Structural description of a 2 x 1 multiplexer with active low enable.

We have seen the behavioral description of 2x1 multiplexer in example 2.2. The same 2x 1 multiplexer is redrawn here for convenience.

s Enbar or En _ __,.. __ _... 12

s

2 x 1 MUX

En----~

y

(a) Logic diagram (b) Logic symbol


.... Listing 4.9 : HDL description of a 2x1 multiplexer with active low enable. library leee;

use ieee.std_Jogic_1164.all;

entity mux2 x 1 is

port (DO, Dl, S, Enbar: 1n st d_logic;

Y : out std_!ogic);



endmux2 x 1;

architecture MUX of mux2 x 1 is

-- Components declaration

component and3

port ( Il, 12, 13: In std_logic;


end component;


Only different types of components need be declared.

Since the multiplexer has two identical AND gates,

only one is declared.

component or2

port ( Il, 12 : in std:...logic;


end component;

component inv

port ( I1 : in std _logic;


end component;

signal 11, 12, 13, 14 : std_logic;

for all : and3 use entity work.three_input (and3_7);

for all : inv use entity work.one_input (inv_7);

for all: or2 use entity work.two_input (or2_7);

be~

Al : and3 port map (DO, 11, 12, 13);

A2 : and3 port map (Dl, S, 12, 14);

lVl : inv port map (S, Il);

lV2 : inv port map (Enbar, 12);

OR : or2 port map (13, 14, Y);

endMUX;

-- instantiation

Verilog 2 x 1 Multiplexer with Active Low Enable

module mux2 x 1 (DO, Dl, S, Enbar, Y);

Input DO, Dl, S, Enbar;

output Y;

and #7 (13, DO, 11, 12);

or #7 (Y, 13, 14);

and #7 (14, Dl, S, 12);

not #7 (Il, S);


Fundamentals of HDL

not #7 (12, Enbar);

endmodule

4 -13 Structural Desc ription

u• Example 4.3 : Structural description of a 2x 4 decoder with enable input.

n-dala inputs

Enable inputs

n n:2

Decoder

Possible n

2 outputs

Fig. 4.3 General structure of decoder

A decoder is a multiple-input, multiple-output logic circuit which converts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code. Each input code word produces a different output code word, i.e., there is one-to-one mapping from input code words into output code words. This

one-to-one mapping can be expressed in a truth table.

The Fig. 4.3 shows the general structure of the decoder circuit. As shown in the Fig. 4.3, the encoded information is presented as n inputs producing 2" possible outputs. The 2" output values are from 0 through 2" - 1. Sometimes an n-bit binary code is truncated to represent fewer output values than 2". For example, in the BCD code, the 4-bit combinations 0000 through 1001 represent the decimal digits 0-9, and combinations 1010 through 1111 are. not used. Usually, a decoder is provided with enable inputs to activate decoded output based on data inputs. When any one enable input is unasserted, all outputs of decoder are disabled.

A B

Abar Bbar

Y 0= Abar Bbar

Enable (EN)

Fig. 4.4 2-to-4 line decoder



A decoder which has an n-bit binary input code and a one activated output out-of-2" output code is called binary decoder. A binary decoder is used when it is

necessary to activate exactly one of 2° outputs based on an n-bit input value.

Fig. 4.4 shows 2 to 4 decoder. Here, 2 inputs are decoded into four outputs, each output representing one of the minterms of the 2 input variables. The two inverters provide the complement of the inputs, and each one of four AND gates generates one of the minterms.

The Table 4.1 shows the truth table for a 2-to-4 decoder. As shown in the truth table, if enable input is 1 (EN = 1), one, and only one, of the outputs Y0 to Y3, is active for a given input. The output Y0 is active, i.e. Y0 = 1 when inputs A = B = 0, the output Y1 is active when inputs A = 0 and B = l. If enable input is 0, i.e. EN = 0, then all the outputs are 0.

Inputs Outputs

EN A B Y3 Y2 Y1

0 x x 0 0 0

0 0

0

0

Table 4.1 Truth table for a 2-to-4 decoder

Listing 4.10 : HDL description of a 2x4 decoder with enable Input.

.... VHDL 2 x 4 Decoder with Enable Input library ieee; use ieee.std_logic_1164.all;

entity decoder2 x 4 is

port ( A, B, En : in std_logic;

Y : out std_logic_vector (3 downto 0));

end decoder2 x 4;

architecture decotjer of decoder2x4 hi

component inv

port ( 11 : in std_logic;


end component;

component and3



Yo

0


Fundamentals of HDL 4-15

end component;

for all : inv use entity work.one_ input (inv _ 4);

for all: and3 use entit y work.three_input (and3_4);

signal Abar, Bbar : std_logic;

begin

IVO : inv port map (A, Abar);

!Vl : inv port m ap (B, Bbar);

AO : and2 port map (Abar, Bba r, En, YO);

Al : and2 port map (Abar, B, En, Yl) ;

A2 : and2 port map (A, Bbar, En, Y2);

A3 : and2 port· map (A, B, En, Y3);

end decoder;

Verilog 2 x 4 Decoder with Enable Input

module decoder2 x 4 (A, B, En, Y);

input A, B;

input En;

output (3:0] Y;

wire Abar, Bbar;

not (Abar, A);

not (Bbar, B);

and (YO, Abar, Bbar, En);

and {Yl, Abar, B, En);

and (Y2, A, Bbar, En);

and (Y3, A, B, En);

Endmodule


-- Signal Declaration

n• Example 4.4 : Structural description of a 2 x 4 decoder with tri-state output.

The Fig. 4.5 shows the 2x 4 decoder with tri-state output. For this decoder when enable (En) input is low, the outputs are in high impedance state, i.e. tri-state.



A B

Abar Bbar

>--- Y1

>--- v2 ·

En

Fig. 4.5 2x 4 decoder with tri-state output

The Table 4.2 shows the truth table for a 2x4 decoder with tri-state output.

Inputs Outputs

En A B Y3 Y2 Y1

0 x x z z z

1 0 0 0 0 0

1 0 1 0 0 1

1 1 0 0 1 0

. 1 1 1 1 0 0

Table ~.£ i futh table for 2x 4 decoder with trl-state output

Iii> Listing 4.11 : VHDL behavioral description of a tri-state buffer. entity two_input ls

port ( 11, 12 : in std_logic:


end two_input;

architecture bufifl of two _input is

YO

z

1

0

0

0



begin

buffer : process (11, 12)

variable temp: std_Jogic;

begin

If (12 = '1') then

temp:= 11;

else

temp := 'Z';

end if;

01 <=temp;

end process buffer;

end bufifl;

.... Listing 4.12 : HDL description of a 2x4 decoder with tri-state output.

VHDL 2 " 4 Decoder with Tri-State Output

library ieee;


entity decoder2 x 4 is

port (A, B : in std_Jogic;

En: in std_logic;

Y: out std_logic_vector (3 downto 0));

end decoder2 x 4;

architecture deco9,er of decoder2 x 4 is

component bufifl

port (11, 12 : in std_logic; 01 : out std_logic);

end component;

component inv



end component;

component and2



end component;

for all : bufif1 use entity work.two_input (bufif1);

for all: inv use entity work.one_input (inv_4);


Fundamentals of HDL 4 - 18 Structural Description

for all : and2 use entity work.bind2 (and2 _ 4);

signal IO, 11, I2, I3: std_logic;

signal Abar, Bbar: std_logic;

begin

BO : bufifl port map (IO, En, Y(O));

B1 : bufif1 port map (11, En, Y(1));

B2 : bufifl port map (I2, En, Y(2));

B3 : bufifl port map (13, En, Y(3));

IVO : inv port map (A, Abar);

IVl : inv port map (B, Bbar);

AO : and2 port map (Abar, Bbar, IO);

Al: and2 port map (Abar, B, 11);

A2 : and2 port map (A, Bbar, I2);

A3 : and2 port map (A, B, I3);

end decoder;

-- Signal Declaration

In VHDL, we have to write a description of. the tri-state buffer gate. However, Verilog has built-in buffers. The Fig. 4.6 shows the buffers supported by Verilog.

in ---1>-- out buff1: _ ~

Enable

in~out notif1 :

Enable·

in --t:;.- out buffO: ~

Enable

in ---{>- out notito : . __J

Enable

Fig. 4.6 Built-in buffers in Verilog Verilog 2 x 4 Decoder with Tri-State Output

module decoder2 x 4 (A, B, En, Y);

Input A, B;

Input En;

output (3:0) Y;

wire Abar, Bbar;

buflfl (Y(O), IO, En);

buflfl (Y(l). 11, En);

buflfl (Y(2), I2, En);

buflfl (Y(3J. I3, En):


Fundamentals of HDL

not (Abar, A);

n ot (Bbar, B);

and (IO, Abar, Bbar);

and (11 , Abar, B);

and (12, A, Bb ar);

and (13, A, B);

endmodule

4 -19

n• Example 4.5 : Structural description of a full-adder.


The Fig. 4.7 the implementation of a full-adder with two half-adders and OR gate. The listing 4.13 shows the HDL code for this full-adder.

First Half-Adder

A --t,....,_,,..,"'"" B _.;.:..+;..,_.....,fl

Second Half-Adder

Fig. 4.7 Implementation of a full-adder with two half-adders and an OR gate

.,. Listing 4.13 : VHDL code for the half adder. library ieee; use ieee.ltd _logic_ 1164.all;

entity 12_02 is

port ( 11, 12 : ln std_ logic;

0 1, 02 : out std_logic);

end 12_02;

architecture HA of 12_02 is

component xor2

port ( 11, 12 : ln s td_ logic;


end component;

component and 2

port ( 11, 12 : ln std_logic ;


and compone nt;


Fundamentals of HDL 4-20 Structural Descriptli:m

for Al: and2 use entiW work.two_input (and2_4);

for Xl: xor2 use entity work.two_input (xor2_4);

begin

Xl : xor2 port map (11, 12, 01);

Al : and2 port map (11, 12, 02);

end HA;

... Listing 4.14 : HDL description of a full adder -VHDL and Verilog

VHDL Full Adder Description

library leee;


entity full_ adder is

port (A, B, Cin: in std_logic;

Sum, Cout : out std_logic:.;

end full_adder;

architecture adder of full adder is

component HA

port ( Il, 12 : in std _logic;

0 1, 02; out. std_)ogic);

end component;

component or2



end component;

for all ; HA use entity work.12_02 (HA);

for all ; or2 use entity work.two_inout (or2_4);

signal SO, CO, Cl : std_logic;

begin

HA1 ; HA port map (A, B, SO, CO);

HA2 : HA port map (Cin, SO, Sum, Cl);

OR1 : or2 port map (CO, Cl, Cout);

end adder;

Veril6g Full Adder Description

I module full_adder (A, B, Cin, Sum, Cout);

input A, B, Cin;


Fundamentals of HDL

output Sum, Cout;

wire SO, CO, Cl;

HA Hl (A, B, SO, CO);

HA H2 (SO, Cin, Sum, Cl);

or (Cout, CO, Cl);

endmodule

module HA (A, B, S, C);

Input A, B;

output S, C;

xor (S, A, B);

and (C, A, B);

endmodule

4 -21 Structural Description

II binding HA modules to module full_ adder

II Half-Adder Module

n»* Example 4.6 : Structural description of an SR-latch. The simplest type of latch is the set-reset (SR) latch. It can be constructed from

either two NANO gates or two NOR gates.

SR latch using NOR gates

S (Set)

Fig. 4.8 shows the SR latch using two NOR gates. As shown in the Fig. 4.8, the two NOR gates ar.: cross coupled so that the output of NOR gate 1 is connected to one of the inputs of NOR gate 2 and ~ice versa. The latch has two outputs Q and Q, and two

inputs, set and reset.

Fig. 4.8 SR latch using NOR gates Before going to analyse the SR latch, we

recall that a logic 1 at any input of a NOR gate forces its output to a logic 0. Let us

understand the operation of this circuit for various input/ output possibilities.

R (Reset)-~0__,

S (Set) 1

Fig. 4.9 (a)

CASE 1 : S = 1 and R = 0

In this case, S input of the_ NOR gate 2 is at logic 1, hence its output, Q is at logic 0.

Both inputs to NOR gate 1 are now at logic 0. So that its output, Q is at logic 1.


Fundamentals of HDL

R (Reset),----<

S (Set)

Fig. 4.9 (b)

S (Set)

Fig. 4.9 (c)

S (Set)

Fig. 4.9 (d)

CASE 4 : S = 1 and R = 1

4-22 Structural Description

CASE 2 : S • 0 and R ,. 1

In this case, R input of the NOR gate 1 is at logic 1, hence its output, Q is at logic 0. Both inputs to NOR gate 2 are now at logic 0. So that its output, Q is at logic 1.

CASE 3 : S = 0 and R = 0

Initially, Q = 1 and Q = 0

_ Let us a~ume that initially Q = 1 and Q = 0 . With Q = 0, both inputs to NOR gate

1 are at logic 0. So its output, Q is at logic l. With Q = l, one input of NOR gate 2 is at logic l, hence its output, Q is at logic 0. This

shows that when S and R both are low (at logic 0) the output state does not change.

Initially, Q = 0 and Q = 1

Let us make opposite assumption that Q = 0 and Q = 1. With Q = l , one input of

NOR gate 1 is at logic 1, hence its output Q is at logic 0. With Q = 0, both inputs_ to NOR gate 2 are at logic O. So its output Q is

at logic l. In this case also there is no change in the output state.

When R and S both are at logic 1, they force the outputs of both NOR gates to the low state. (Q=O and Q = O). So we call this an indeterminate or prohibited state, and

represent this condition in the truth table as an asterisk (•). This condition also violates the basic definition of a latch that requires Q to be the complement of Q. Thus in

normal operation this condition must be avoided by milking sure that l 's are not applied to both the inputs simultaneously.

Fig. 4.10 shows the symbol and truth table for SR latch. Looking at Fig. 4.10 we can summarize the operation of SR latch as follows :



• With both inputs low, the output does not change and latch remains latched in its last state. This condition is called inactive state because nothing changes.

• When R input is low and S input is high, the Q output of latch is set (at logic 1).

• When R input is high and S input is low, the Q output of latch is reset (at logic 0).

• When R and S inputs both are high, output is unpredictable. This is called indeterminate condition.

s R Qn Qn+1 State

0 0 0 0 No change(NC)

0 0 1 1

s Q 0 1 0 0 Reset

0 1 1 0

R 0 1 0 0 1 .Set

1 0 1 1

1 1 0 x Indeterminate

1 1 1 x . (a) Symbol (b) Truth table

Fig. 4.10

.,.. Listing 4.15 : HDL description of an SR latch with NOR gates.

VHDL SR Latch with NOR Gates

library ieee;


entity SR_ Latch is

port ( R, S : in std_logic;

Q, Obar: buffer std_logic);

•• Q, Obar are declared buffer because they behave as input and output.

end SR_ Latch;

architecture Latch of SR Latch is

•. Here Q and Obar signals are declared as buffer; however these signals are

-- mapped with in and out signals. Some simulators may not allow such

-- mapping. In this case, change all in and out to buffer.


Fundamentals of HDL

component nor2



end component;

4-24

for all : nor2 use entity work.two_input (nor2_7);

begin

n l : nor2 port map (S, Q, Obar);

n2 : nor2 port map (R, Obar, Q);

end Latch;

Verilog SR Latch with NOR Gates

module SR_ Latch (R, S, Q, Obar);

input R, S;

output Q, Obar;

nor (Obar, S,Q);

nor (Q, R, Obar);

endmodule

,,_. Example 4.7 : Structural description of a D latch


We have already seen the data-flow description of D latch in example 2.5. The Fig. 2.11 show the D latch.

.... Listing 4.16 : HDL description of a D latch-VHDL and Verilog

VHDL D latch Description

library leee;


entity D_Latch is

port ( D, En: in std_logic;

Q, Obar: buffer std_ logic);

end D_Latch;

architecture Latch of D Latch is

Here Q and Obar signals are declared as buffer; however these signals are



component nand2



Copyrighted material •

Fundamentals of HDL 4 ·25 Structural Description

end component;

for all: nand2 use entity work.two_input (nand2_7);

signal Sl, R, Rl : std_logic;

begin

NAl : nand2 port map {D, En, Sl);

NA2 : nand2 port map (R, En, Rl);

NA3 : nand2 port map (D, D, R); •· nand gate used as an inverter

NA4 : nand2 port map (Sl, Obar, Q);

NA5 : nand2 port map (0, Rl, Obar);

end Latch;

Verilog D latch Description

module D_latch (D, En, Q, Obar);

input D, En;

output 0, Obar;

wire Sl, Rl; ·

nand #7 gatel (Sl, D, En);

nand #7 gate2 (0, Obar, Sl);

nand #7 gate3 (Rl, R, En);

nand #7 gate4 (Obar, 0 , Rl );

nand #7 gate5 (R, D, D);

/I assume 7 ns delay for nand gate

II nand gate used as an inverter

II the names gatel, gate2 .. . given are optional

endmodule

n'* Example 4.8 : Structural description of pulse triggered SR flip-flop. The Fig. 4.11 shows the pulse triggered SR flip-flop.

s $1

a

CP

O (Q bar) R1

R 4

Fig. 4.11 Clocked SR flip-flop



CP s R a. Cn•1 Sta ta J1. 0 0 0 0

J1. No cllange(NC)

0 0 1 1

J1. 0 1 0 0 s a J1. 0 1 1 0

Reset

J1. 1 0 0 1 Set

J1. 1 0 1 1

CP R 0

J1. 1 1 0 x J1.

Indeterminate 1 , 1 x

0 x x 0 0

0 x x , , No change(NC)

(a) Logic symbol (b) Truth table for clocked SR flip-flop Fig. 4.12

The Fig. 4.12 shows the logic symbol and truth table of clocked SR flip-flop.

Listing 4.17 : HDL description of a SR-Flip-Flop-VHDL and Verilog.

IJI> VHDL SR-FF Description library iaee;


entity SR_ FF is

p ort ( S, R, CP : in std_logic;

Q , Obar : buffer std_logic);

end SR_FF;

architecture FF of SR FF is

-- Here Q and Obar signals are declared as buffer; however these signals are



component nand2



on d component;

for a ll : nand2 use e ntity work.two_input (nand2_7);

signal Sl, Rl : std_logic;

begin

NA1 : nand2 port map (Sl, Obar, Q);

NA2 : nand2 port map (Q, R1, Obar);

NA3 : nand2 port map (S, CP, S1);

NA4 : nand2 port map (R, CP, Rl);

en d Latch;


.. Fundamentals of HDL

Verllog SR-FF Description

module SR_FF (S. R. CP, Q, Obar);

input S, R. CP;

output a. Obar;

wire Sl, Rl;

nand # 7 gate1 (Q , Obar, S1);

nand #7 gate2 (Obar, Q, Rt);

nand # 7 gate3 {St , S, CP);

nand #7 gate4 (Rt , R, CP);

endmodule


11 assume 7 ns delay for nand gate

II the names gatet, gat e2 .. . given are optional

Ill• Example 4.9 : Structural description of pulse triggered D flip-flop. Like in D latch, in D flip-flop the basic SR flip-flop is used with complemented

inputs. The D flip-flop is similar to D-latch except clock pulse is used instead of enable input. Fig. 4.13 shows logic symbol and truth table for D flip-flop and Fig. 4.14 shows the input and output waveforms.

CP D Qn+1

.n. 0 0 D Q

I~ 1 1

x an

CP

(a) Logic symbol (b) Truth table of D flip-flop

Fig. 4.13

1

CP~ ! 1

D~ :

l I •

1 :

a~ L Fig. 4.14 Input and output waveforms of clocked D flip-flop



~ Listing 4.18 : HDL description of a D flip-flop-VHDL and Verilog

VHDL D_FF Description

library leee;

use ieee.std_Joglc_1164.all;

entity D _FF is

port ( D, CP : in std_logic;

Q, Obar: buffer std_logic);

end D_FF;

architecture FF of D FF is

-- Here Q and Obar signals are declared as buffer; however these signals are



component nand2



end component;

for all: nand2 use entity work.two_input (nand2_7);

signal S1, R, R1 : std_logic;

begin

NAl : nand2 port map (D, CP, Sl);

NA2 : nand2 port map (R, CP, R1);

NA3 : nand2 port map (D, D, R); -- nand gate used as an inverter

NA4 : nand2 port map (S1, Obar, Q);

NAS : nand2 port map (Q, R1, Obar);

end FF;

Verilog D_FF Description

module D_FF (D, CP, Q, Obar);

input D, CP;

output Q, Obar;

wire S1, Rl;

nand #7 gate1 (Sl, D, CP);

nand #7 gate2 (Q, Obar, Sl);

nand #7 gate3 (Rl, R, CP);

nand #7 gate4 (Obar, Q, R1);

11 assume 7 ns delay for nand gate



I nand #7 gate5 (R, D, D); 11 nand gate used as an inverter

II the names gate1, gate2 ... given are optional

endmodule

n'* Example 4.10 : Structural description of pulse triggered JK flip-flop. The Fig. 4.15 (a) shows the pulse triggered JK flip-flop, and Fig. 4.15 (b) and (c)

shows the logic symbol and truth table for JK flip-flop.

Fig. 4.15 (a) Clocked JK flip-flop

On J K

0 0 0 0 0 1 0 1 0 0 1 1 CP

J 0

1 0 0 1 0 1 1 1 0 1 1 1

Fig. 4.15 (b) Logic symbol

~ Listing 4.19 : HDL description of JK flip-flop

VHDL JK Flip-Flop

library ieee:

use leee.std_logi~_1164.all;

entity JK_FF Is

port ( J, K, CP : in std_logic;

Q, Obar : buffer std_logic);

On+1

0 J K On+1

0 1 1

0 0 On

0 1 0

1 0 1

1 0 1

1 1 On

0

Fig 4.15 (c) Truth table

-- Q , Obar are declared buffer because they behave as input and output.

end JK_FF;



architecture FF of JK FF ill

-- Here 0 and Obar signals are declared as buffer; however these signals are



component nor2


0 1 : out std_logic);

end component;

component and3


01 : out std_Jogic);

end component;



signal R, S

begin

Nl : nor2 port map (S, 0, Obar);

N2 : nor2 port map (R, Obar, 0);

Al: and3 port map (0 , K, CP, R);

A2 : and3 port map (Obar, J, CP, S);

end FF;

Verilog JK_FF

module JK_FF (J, K, CP, 0, Obar);

input J, K, CP;

output 0 , Obar;

nor (Obar, S, 0);

nor (Q, R, Obar);

and (R, 0 , K, CP);

and (S, CP, J, Obar);

endmodule

,,_. Example 4.11 : Structural description of a 3-bit magnitude comparator using a 3-bit adder.

We have seen 2-bit comparator in chapter 2. If the number of bits to be compared is more than two bits, the truth tables and hence the circuit becomes more complicated. Thus, we can implement 3-bit comparator with some different approach. In this approach 3-bit adder is used to generate AeqB, AgtB and AltB signals.



Consider, there are two numbers A and B, each of n bits. Let us assume A is greater than B. This condition can be written as

A>B=>A - B >0

=> A+B + l>O

~ A+B>-1

We represent - 1, in n bit binary numbers as

1,, l,, _1 ···1 2 11 10

·: B + 1 is 2's complement of B

The above equation says that if A is greater than B, then the sum of_ A and B should be greater than ln ln - l ••· 12 11 10 . If n adder is used to add A and B, and the

final carryout is 1 then we can say that A + B > ln 1" _ 1 · · · 12 11 10 , i.e. A > B.

If this condition is not satisfied, we can say that A ~ B. Now we can check of equality by checking the following equation.

A+ B = ln ln- l · · · 12 11 lo

If A > B and A = B, both conditions are not true then we can say that A < B.

The Fig. 4.16 shows the circuit diagram of comparator for n = 3.

AgtB

62

Bbar2

Full Adder

Sum2

AltB

A2 61

C2 Full Adder

Sum1

AeqB

A1 BO

C1 Full Adder

Sumo

Fig. 4.16 3-bit comparator using 3-bit adder

AO

0


Fundamentals of HDL 4-32 Str;uctural. Description

The listing 4.20 shows the HDL code for 3-bit comparator. The HDL code for a full-adder has already written in example 4.5 .

..,. Listing 4.20 : HDL description of a 3-bit comparator using adders.

VHDL 3-Blt Comparator Using Adders

library leee;

use leee.std_loglc_1164.all;

entity compare3_bit ls

port ( A, B : in std_logic_vector (2 downto O);

AgtB, AltB, AeqB: buffer std_logic);

end compare3_bit;

architecture compare of compare3_bit ls

component full_ adder

port ( Il, 12, 13 : in std_logic;

01, 02 : out std_logic);

end component;

component inv

port ( I1 : in std_logic;


end component;

component nor2



end cCJmponent;

component and3



end component;

for all : full_adder use entity work.full_adder (adder);

for all : inv use entity work.one_input (inv_4);


for all : and3 use entity w ork.three_input (and3_7);

signal Sum, Bbar: std_logic_vector (2 downto O);

signal C : std_logic_vector (2 downto 1);

begin

inl : inv port map (B(O), Bbar(O));

in2 : inv port map (B(l), Bbar(l));



in3 : inv port map {B(2), Bbar(2));

FO: full_adder port map (A(O), Bbar(O), 'O', Sum(O), C(l));

Fl : full_adder port map (A(l), Bbar(l), C(l), Sum(l), C(2));

F2: full_adder port map (A(2), Bbar(2), C(2), Sum(2), AgtB);

Al : and3 port map (Sum(O), Sum(l), Sum(2), AeqB);

Nl : nor2 port map (AeqB, AgtB, AltB);

end compare;

Verilog 3-Bit Comparator Using Adders.

module compare3_bit (A, B, AgtB, AltB, AeqB);

Input (2:0( A, B;


wire (2:1( C;

wire [2:0) Sum, Bbar;

not (Bbar[O), B[O();

not (Bbar(l), Bill);

not (Bbar(2(, B(2();

full_ adder MO (A(O), Bbar(O). l'bO, Sum(O). C(l();

full_ adder Ml (A(l ), Bbar(l). C(l). Sum(l). C(2();

full_adder M2 (A(2(, Bbar(2). C(2], Sum(2). AgtB);

and # 7 (AeqB, Sum(O(, Sum(l(. Sum[2();

nor (AltB, AeqB, AgtB);

endmodule

111.. Example 4.12 : Structural Description of an SRAM Cell A simple SRAM (static RAM) cell consists of a latch. It has a tri-state output. If the

Sel line of the cell is low, the output of the cell is in high, impedance state. The R/W (Read/ Write) signal controls the operation of the cell. If RI W is high, the cell performs read operation; otherwise it performs write operation. The Table 4.3 shows the excitation -table for memory cell.

Sel -

Din D En a• en Dout R/W

0 0 x Din 0 Q 0 z

0 1 x 0 0 Q 0 z

1 0 x Din 1 Din 0 z

1 1 x 0 0 Q 1 Q

Table 4.3 Excitation table of SRAM cell


Fundamentals of HDL 4 . 34 Structural Description


ForD

0

0

:. 0 = Din . R/Vll

Se I

ForCn RJW

0 1

0 0 0

1 0 Q

Cn = Sel. R/Vll

Fig. 4.17

For En

En = Sel. R/Vll

Dout

Oout = Q (for Cn = 1) Oout = Z (for Cn = 0)

The Fig. 4.17 shows the logic symbol and logic diagram of SRAM cell.

·~

SRAM Cell

R/Vll (RWb -ar)

Set

(a) Logic symbol

a Oout

(b) Logic diagram

Fig. 4.18

Dout

The listing 4.21 shows the HDL code for SRAM cell. The code is linked with the entity D-latch in example 4.7 by statement :

for all : D_Latch use entity work. D_Latch (Latch) ;

• Listing 4.21 : HDL description of SRAM memory cell.

VHDL SRAM Memory Cell Description

library leee;



Fundamentals of HDL

entity memory ls

port ( Sel, RW, Din: in std_logic;

Dout: buffer std_logic );

end memory;

architecture mem_cell of memory is

component and2

port ( 11, 12 : in std_ logic;


end component;

component inv



end component;

component bufifl



end component;

component D _Latch

port ( Il , I2 : in std_logic;

01, 02: buffer std_logic);

end component;

4-35

for all: and2 use entity work.two_input (and2_4);



for all: bufifl use entity work.two_input (bufifl);

for all : D _Latch use entity work.D _latch (Latch);

signal RWbar, D, En, Q : std_logic;

begin

INl : inv port map (RW, RWbar);

Al : and2 port map (Se!, RWbar, En);

A2: and2 port map (Sel, Din, D);

Dl: D_Latch port map (D, En, a, open);


-- open is a predefined word; it indicates that the port is left open.

A3 : and2 port map (Se!, RW, Cn);

bufl : bufifl port map (Q,Cn, Dout);

end mem_cell;


Fundamentals of HDL

Verilog SRAM Memory Csll Description

module memory (Sel, RW, Din, Dout );

input Sel, RW, Din;

output Dout;

wire RWbar, D, Q;

not (RWbar, RW);

and (En, Sel, RWbar);

and (D, RWbar, Din);

D_Latr..il ul (D, En, Q, Obar);

and (Cn, Sel, RW);

buflfl (Dout, Q, Cn);

endmodule

4.4 State Machine

4- 36 Structural Description

There are many applications in which digital outputs are required to be generated in accordance with the sequence in which the input signals are received. This requirement cannot be satisfied using a combinational logic system. These applications require outputs to be generated that are not only dependent on the present input conditions but they also depend upon the past history of these inputs. The past history is provided by feedback from the output back to the input.

Fig. 4.19 shows the block diagram of sequential circuit/finite state machine (FSM). As shown in the Fig. 4.19, memory elements are connected to the combinational circuit as a feedback path.

Combinational lnp uts circuit

Outputs (Combinational

componenl)

l Memory elements

14-Present state (Sequential Nexis tale

component)

Sequential circuit

Fig. 4.19 Block diagram of sequential circuit I FSM

j Copyrighted material

Fundamentals of HDL 4 .37 Structural Description

The information stored in the memory elements at any given time defines the present state of the sequential circuit. The present state and the external inputs determine the outputs and the next state of the sequential circuit. Thus we can specify the sequential circuit by a time sequence of external inputs, internal states (present states and next states), and outputs.

Sr. No. Comblnatlonal circuits Sequential circuits

1. In combinational circuits. the output variables In sequential circuits, the output variables are at all times dependent on the depend not only on the present input combination of input variables. variables but they also depend upon the past

history of these input variables.

2. Memory unit is not required in combinational Memory unit is required to store the past circuits. history of input variables in the sequential

circuit.

3. Combinational circuits are faster in speed Sequential circuits are slower than the because the delay between input and output combinational circuits. is due to propagation delay of gates.

4. Combinational circuits are easy to design. Sequential circuits are comparatively harder to design .

. 5. Parallel adder is a combinational circuit. Serial adder is a sequential circuit.

Table 4.4 Comparison between combinational and sequential circuits

4.4.1 Types of Sequential Circuits

In synchronous or clocked sequential networks, clocked flip-flops are used as memory elements, which change their individual states in synchronism with the periodic clock signal. Therefore, the change in states of flip-flops and change in state of the entire circuit occurs at the transition of the clock signal.

The synchronous or clocked sequential networks are represented by two models.

• Moore model : The output depends only on the present state of the flip-flops.

Mealy m1Jdel : The output depends on both the present state of the flip-flop(s) and on the input(s).

4.4.1.1 Moore Model

As mentioned earlier, when the output of the sequential circuit depends only on the present state of the flip-flop, the sequential circuit is referred to as Moore model. Let us see one example of Moore model. Fig. 4.20 shows a sequential network which consists of two JK flip-flops and AND gate. The network has one input X and one output Y.



x x JA QA Je Os

CP 0 © 1 KA QA 0 Ka QB

y

Fig. 4.20 Example of Moore model

As shown in the Fig. 4.21, input is used to determine the inputs of the flip-flops. It is not used to determine the output. The output is derived using only present states of the flip-flops or combination of it (in this case Y = QAQ9).

In general form the Moore model can be represented with its block schematic as shown in Fig. 4.21 (a) and (b).

In the Moore model, as output depends only on present state of flip-flops, it appears only after the clock pulse is applied, i.e. it varies in synchronism with the clock input.

Inputs {: Next state Memory

decoder elements

~

I Fig. 4.21 (a) Moore model

Inputs {: --Next Output

state Memory decoder . decoder elements (Combinational

~ circuit)

i---

}~-r

Fig. 4.21 (b) Moore circuit model with an output decoder



4.4.1.2 Mealy Model

When the output of the sequential network depends on both the present state of flip-flop(s) and on the input(s), the sequential circuit is referred to as Mealy model. Fig. 4.22 shows the sample Mealy model. As shown in the Fig. 4.22, the output of the circuit is derived from the combination of present state of flip-flops and input(s) of the circuit.

x x JA QA JB Os

CP 0 © KA QA 0 Ke Oe

y

Fig. 4.22 Example of Mealy model

Looking at Fig. 4.22, we can easily realise that, changes in the input within the clock pulses cannot affect the state of the flip-flop. However, they can affect the output of the circuit. Due to this, if the input variations are not synchronized with the clock, the derived output will also not be synchronized with the clock and we get false output (as it is a synchronous sequential network). The false outputs can be eliminated by allowing input to change only at the active transition of the clock (in our example HIGH-to-LOW).

In general form the Mealy model can be represented with its block schematic as shown in Fig. 4.23.

r---Output

'"'"" { decoder

Next state Memory

decoder elements

Outputs

- r--

Fig. 4.23 Mealy circuit model



4.4.1.3 Moore Vs Mealy Circuit Models

Sr. Moore Model Mealy Model No.

a) Its output is a function of present state Its output is a function of present state only. as well as present input.

b) Input changes does not affect the Input changes may affect the output of output. the circuit.

c) Moore model requires more number of It requires less number of states for states for implementing same function. implementing same function.

4.4.2 State Machine Notations

In the state machine, the Boolean variables have different names according to their generation place.

• Input variable : AU variables that originate outside the sequential machine are called input variables.

• Output variable : All variables that exit the sequential machine are called output variables.

• State variable : The output of flip-flops (memory) defines the state of a sequential machine. Therefore, the state variables are the flip-flop outputs.

• Excitation variable : Excitation variables are the inputs to the flip-flops (memory). Excitation variables are generated by the input combinational logic operating on the state variables and input variables.

For example, in the Mealy model shown in Fig. 4.22, X is an input variable, Y is an output variable, QA and Q 8 are the state variables and variable XA which excites

flip-flop B is an excitation variable.

4.4.2.1 State and State Variable

We know that state is defined by the output of flip-flops (memory). In the state machine, state variables and states are related by the expression

where

and

y

x = Number of state variables (e.g. flip-flops)

y = Maximum number of possible states

The 4 state variables can represent a maximum of 16 states.

4.4.2.2 Present State and Next State

In state machines, it is necessary to distinguish state variables before and after the clock pulse. State variable A can be represented as A before the arrival of a clock and



as A+ after the arrival of a synchronizing clock pulse. The idea of present state and next state is illustrated in Fig. 4.24.

Clock I \ I \,__--f I \ I I t - 1 ,.._ t + 1 -I I I I I I

State ==>k: A- >K A >K A+

I I I I I I I I I I I I

Fig. 4.24 Illustrating present state and next state

Present state

The status- of all state variables, at some time, t, before the next clock edge, represents condition called present state.

Next state

The status of all state variables, at some time, t + 1, represents a condition called next state.

4.4.2.3 State Transition Diagram

Fig. 4.25 State diagram for Mealy circuit

State diagram is a pictorial representation of a behaviour of a sequential circuit. Fig. 4.25 shows a state diagram. The state is represented by the circle, and the transition between sta tes is indicated by directed lines connecting the circles. A directed line connecting a circle with itself indicates that next state is same as present state. The binary number inside each circle identifies the state represented by the circle. The directed lines

are labelled with two binary numbers separated by a symbol '/'. The input value that causes the state transition is labelled first and the output value during the present state is labelled after the symbol '/'.



0

0

Fig. 4.26 State diagram for Moore circuit

4.4.2.4 State Table


In case of Moore circuit, the directed lines are labelled with only one binary number representing the state of the input that causes the state transition. The output state is indicated within the circle, below the present ·state because output state depends only on present state and not on the input. Fig. 4.26 shows the state diagram for Moore circuit.

Although the state diagram provides a description of the behaviour of a sequential circuit that is easy to understand, to proceed with the implementation of the circuit, it is convenient to translate the information contained in the state diagram into a tabular form. Table 4.S(a) shows the state table for the state diagram shown in Fig. 4.25. It represents relationship between input, output and flip-flop states. It consists of three sections labelled present state, next state, and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state is state of the flip-flop after the application of a clock pulse, and the output section gives the values of the output variables during the present state. Both the next state and output sections have two columns representing two possible input conditions: X = 0 and X=l.

Present state Next state Output

x"' 0 X=1 X=O X=1

AB AB AB y y

a a c 0 0

b b a 0 0

c d c 0 1

d b d 0 0

Table 4.5 (a)

In case of Moore circuit the output section has only one column since output does not depend on input. The Table 4.5 (b) shows the state table for Moore circuit whose state diagram is shown in Fig. 4.26.




X=O x = 1 y

AB AB AB

a a c 0

b b a 0

c d c 1

d b d 0

Table 4.5 (b)

4.4.2.5 Transition Table

A transition table takes the state table one step further. The state diagram and state table represent state using symbols or names. Jn the transition table specific state variable values are assigned to each state. Assignment of values to state variables is called State assignment. Like state table transition table also represents relationship between input, output and flip-flop states. The Fig. 4.27 shows the transition table.

· Present state Next state Output

X=O X=1 X=O x = 1

A B AB AB y y

0 0 00 1 0 0 1

0 1 1 1 00 0 0

1 0 1 0 0 1 1 0

1 1 00 1 0 1 0

Fig. 4.27 Transition table

Here, AB are the state variables. The AB = 00 represents one state, AB = 01 represents second state and so on.

4.5 Design Equations and Circuit Diagram

From the state assigned transition shown in Fig. 4.27, we can derive the logic equations for the next state and output functions. But first we have to decide on the type of flip-flops that will be used in the circuit. The most straightforward choice is to use D flip-flops, because in this case the values of next state are simply clocked into the flip-flops to become the new values of present state. For other types of flip-flops, such as JK, T and RS the relationship between the next-state variable and inputs to a flip-flop is not as straightforward as D flip-flop. For other types of flip-flops we have to refer excitation table of flip-flop to find flip-flop inputs. This is illustrated in the following example.



n• Example 4 .13 : A sequential circuit has one input and one output. The state diagram is shown in Fig. 4.28. Design the sequential circuit with a) D flip-flops b) T flip-flops c) RS flip-flops and d) JK- flip-flops.

1/1

Fig. 4.28

Solution : The transition table for the state diagram shown in Fig. 4.28 is as given in Table 4.6.


X=O X =1 X= O x .. 1

A B AB AB y y

0 0 0 0 1 0 0 1

0 1 1 1 00 0 0

1 0 1 0 0 1 1 0

1 1 00 1 0 1 0

Table 4.6

As seen from the transition table there are no equivalent states. Therefore, no reduction is the state diagram. The transition table shows that circuit goes through four states, therefore we require 2 flip-flops (number of states = 2"', where m = number of flip-flops). Since two flip-flops are required first is denoted as A and second is denoted as B.

As mentioned earlier, for D flip-flops next states are nothing but the new present states. Thus, we can directly use next states to determine the flip-flop input with the help of K-map simplification.


Fundamentals of HDL 4 .45 Structural Description

For flip - flop A For flip - flop B For output

x A B 0 1

00 0 1

0 1 0 0

11 1')] r

0

• 10 l!l 0

Fig. 4.29

K-map Simplification

DA = A BX + A B X + ABX + A B X and

D8 = AB X + AB X

Y = ABX + AX

With these flip-flop input functions and circuit output function we can draw the logic diagram as follows.

il--r-, ii >---. x--....-"' ii--r--.... B ;c--....-" A-_,..-, B x- -....-" A--r--, ii ;c--1...-"'

il--r--.... B >--~ ;c-....__..,

A-....r--.... ii x--t...-"

CP

QA A

- 9 Os

A ii x

A

x

Fig. 4.30 Logic diagram of given sequential circuit using D flip-flop



... Listing 4.22 : HDL description for given sequential circuit.

VHDL for given sequential circuit

library leee;

use ieee.std_loglc_l 164.all;

entity s _circuit Is

port ( CP, X : in std_logic;

QA, QB, OAJ:>ar, OBbar: .buffer std_logic;

Y : ou t std_logic);

end s _circuit;

architecture circuit_ D of s _circuit Is

component and2

port ( 11, 12: in std_logic;


end component;

component and3

port ( 11, 12, !3 : in std_logic;


end compone nt ;

component or2

port ( 11, 12 : in std_ logic;


end component;

component or4

port ( 11, 12, 13, 14 : in std _logic:


end component ;

component inv

port ( 11 : in std_ logic;


end component;

component D_FF


0 1, 02 : buffer std_logic);

e nd component;

for all : and2 use entity work.two_input (and2_4);







for all : or4 use entity work.four_input (or2_4);

for all : D _FF use entity work.D _FF (FF);

signal Xbar, DA, DB std_logic;

signal I: std_logic_vector (6 downto 1);

begin

INl : inv port map (X, Xbar);

Al : and3 port map (QA.bar, QBbar, X, 1(1));

A2 : and3 port map (QA.bar, QB, Xbar, 1(2));

A3 : and3 port map (QA, QB, X, 1(3));

A4 : and3 port map (QA, QBbar, Xbar, 1(4));

AS : and3 port map (QA, QBbar, X, 1(5));

A6 : and2 port map (QA, Xbar, 1(6));

01 : or4 port map (1(1), 1(2), 1(3), 1(4), DA);

02 : or2 port map (1(2), 1(5), DB);

02 : or2 port map (1(1), 1(6), Y);

Dl : D_FF port map (DA, CP, QA, QA.bar);

D2: D_FF port map (DB, CP, QB, QBbar);

end circuit_D;

II>- Verllog for given sequential circuit module circuit_D (CP, X, QA, QB, QA.bar, OBbar, Y);

input CP, X,;

output Y;

inout QA, QB, QA.bar, QBbar;

wire Xbar, DA, DB

wire (6:11 I;

not (Xbar, X);

and (1111, QA.bar, QBbar, X);

and (1(2). QAbar, OB, Xhar) ;

and (1(3), QA, QB, X );

and (1141. QA, QBbar, X):>ar);

and (1151, QA, QBbar, X);

and (1161, QA, Xbar);

or (DA, 1111, 1121. 1131. 1(4));

or (DB, 1121. 115));

or (Y, 1111. 1(6));

D _FF FFO (DA, CP, QA, QA.bar);



Fundamentals of HDL

D_FF FF1 {DB, CP, QB, OBbar);

endmodule


n• Example 4.14 : Design the sequential circuit in example 4.13 using JK flip-flop and write a structural description for the designed circuit.

Using the excitation table for JK flip-flop shown in Table 4.7 we can determine the excitation table for the given circuit as shown in Table 4.8.

Qn Qn + 1 J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

Table 4.7 Excitation table for JK flip-flop

Present state Input Next state Flip-flop Inputs Output

A B x A B JA KA Jo Ka y

0 0 0 0 0 0 x 0 x 0

0 0 1 1 0 1 x 0 x 1

0 1 0 1 1 1 x x 0 0

0 1 1 0 0 0 x x 1 0

1 'l 0 1 0 x 0 0 x 1

i I 0 1 0 1 x 1 1 x 0

1 1 0 0 0 x 1 x 1 1

1 1 1 1 0 x 0 x 1 0

Table 4.8

The first row of circuit excitation table shows that there is no change in the state for both flip-flops. The transition from 0 ~ 0 for JK filp-flop requires inputs J and K to be 0 and X, respectively. Similarly, we can determine inputs for each flip-flop for each row in the table by referring present statt:, next state and excitation table. Let us use K-map simplification to determine the flip-flop input functions and circuit output functions.


Fundamentals of HDL


(a) For J,. (b) For KA

Therefore, input function for

4 - 49

AB ..-............ 00 0 0

01 x x

11 x

(c) For J 8

Fig. 4.31

J .. = BX+ BX

KA = BX+ BX

fo = AX

KB A+X - --

Structural Descript ion

00 0 ~ 01 0 0

11 ~ ! 1 . 0

I 10 1 0

(d) For Ke (e) For output

Circuit output function = AX+ A BX

Output (Y)

Fig. 4.32 Logic diagram of given sequential circuit using JK flip-flop

.... Listing 4.23 : HDL description for given sequential circuit using - VHDL and Verilog.

VHDL for given sequential circuit

library ieee;


entity s _circuit is

port ( CP, X: in std_logic;

QA, OB. OAbar. QBbar: buffer std_logic;


Fundamentals of HDL

Y : out std_logic);

end s _circuit;

architecture circuit JK of s circuit is - -component and2



end component;

component and3



end component;

component or2

port ( 11, 12 : In std_logic;


end component;

component inv

port ( 11 : In std_logic;


end component;

component JK _FF


01, 02 : buffer std_logic);

end component;

4. 50

for al!: and2 use entity work.two_input (and2_4);


for all : inv use entity work.one input (inv 4); ' - -

for all: or2 use entity'work.two_input (or2_4);

for all : JK_FF use entity work.JK_FF (FF);

signal Xbar, JA, JB, KB std_logic;

signal l: std_logic_vector (4 downto 1);

begin

1N1 : inv port map (X, Xbar);

A1 : and2 port map (QB, Xbar, 1(1));

A2 : and2 port map (QBbar, X, 1(2));

A3 : and2 port map (QA, X, JB);

A4 : and2 port map (QA, Xbar, 1(3));

A5 : and3 port map (QAbar, QBbar, X, 1(4));



Fundamentals of HDL

01 : or2 port map (1(1), 1(2) JA);

02 : or2 port map (1(3), 1(4), Y);

02 : or2 port map (QA, X, KB);

4 - 51

JK1 : JK_FF port map (JA, JA, CP, QA, QAbar);

JK2 : JK_FF port map (JB, KB, CP, QB, OBbar);

end circuit_JK;

Verilog for given sequential circuit

module circuit_JK (CP, X, QA, OB, QAbar, OBbar, Y);

input CP, X, ;

output Y;

inout QA, OB, QAbar, OBbar;

wire Xbar, JA, JB, KB;

wire (4:1) I;

not (Xbar, X);

and (1(1). QB, Xbar);

and (1(2), OBbar, X);

and (JB , QA, X);

and (1(3), QA, Xbar);

and (1(4), QAbar, OBbar, X);

or (JA, 1(1), 1(21);

or (KB, QA, X);

or (Y, 1(3), 1(41);

JK_FF FFO (JA, JA, CP, QA, OAbar);

JK_FF FF1 (JB, KB, CP, QB, OBbar);

endmodule


,,,_. Example 4.15 : Structural description of 3-bit synchronous binary counter.

Fig. 4.33 (a) shows 3-bit synchronous binary counter and its timing diagram. The state sequence for this counter is shown in Table 4.9.

HIGH

- JO 01 J1 01 i..r>--J2 02 ..... ~ -c I> .--c >

- KO - K1 - K2

CP

Fig. 4.33 (a) A three-bit synchronous binary counter



CP

QO

01 -----'

Fig. 4.33 (b) Timing diagram for 3-bit synchronous binary counter

0 0 0 0

0 0

2 0 0

3 0

4 0 0

5 0

6 0

7

Table 4.9 State sequence for 3-bit binary counter Looking at Fig. 4.33 (b), we can see that QO changes on each clock . pulse as we

progress from its original state to its final state and then back to its original state. To produce this operation, flip-flop 0 is held in the toggle mode by connecting J and K inputs to HIGH. Now let us see what flip-flop 1 does. Flip-flop 1 toggles, when QO is 1. When QO is a 0, flip-flop 1 is in the no-change mode and remains in its present state. Looking at the Table 4.9 we can notice that flip-flop 2 has to change its state only when Q l and QO both are at logic 1. This condition is detected by AND gate and applied to the J and K inputs of flip-flop 2. Whenever both QO and QI are HIGH, the outpu.t of the AND gate makes the J and K inputs of flip-flop 2 HIGH, and flip-flop 2 toggles on the following clock pulse. At all other times, the J and K inputs of flip-flop 2 are held LOW by the AND gate output, and flip-flop does not change state.

.... Listing 4.24 : HDL description for 3-bit synchronous binary counter.

VHDL for 3-Blt Synchronous Binary Counter

library ieee;

use ie ee.std_logic_1164.all;

entity counter is

port ( CP : in std_logic;


Fundamentals of HDL 4. 53

0, Obar: buffer std_logic_vector(2 downto 0));

end counter;

architecture cnt 3Bit of counter is

component and2

port ( 11, 12: in std_logic;

01 : out std_ logic);

end component ;

compon ent JK_FF

port ( 11, 12, 13 : in std_logic;

01, 02 : buffer std_logic);

end component;

for all : and2 use entity work.two_input (and2_4);

for all : JK_FF use entity work.JK_FF (FF);

signal J2 std_logic;

begin

Al : and2 port map (0(0), 0(1), J2);

JK1 : JK_FF port map ('l', '1', CP, 0(0), Obar(O));

JK2: JK_FF port map (0(0), 0(0), CP, 0(1), Qbar(l));

JK3 : JK_FF port map (J2, J2, CP, 0(2), Obar(2));

end cnt_3Bit;

Verilog for 3-bit Synchronous Binary Counter

module circuit_JK (CP, 0 , Obar);

input CP;

in out 12:0) 0, Obar;

wire J2;

and (JC, O[OJ, 011[);

JK_FF FFO (l'bl , l'bl, CP, 0(01. ObarlOJ);

JK_FF FFl (0101. 0101. CP, 0(11, ObarllJ);

JK_FF FF2 (J2, J2 , CP, 0(21. Qbarl2J);

endmodule


4.6 Generate (HDL), Generic (VHDL), and Parameter (Verilog)

We can consider a circuit consisting of subcircuits. [n some cases, these subcircuits

are repetitive. For example, an n-bit "ripple adder" consists of n "full adders''. A generate statement in VHDL and parameter in Verilog are used to create repetitive

s tructures for such repetitive subcircuits. This concept is similar to use a FOR loop.


\ Fundamentals of HDL 4-54 Structural Description

When generate statement is used, it is not· necessary to write out all of the component instantiations individually. In VHDL, the syntax of a simple iterative generate loop is given below.

The identifier is a variable with type compatible with the range. This identifier may be used within the concurrent statement given within a FOR loop. The concurrent statement is executed for each possible value of the identifier within the range. For example, consider a circuit consisting of 8 AND gates. A generate statement can be used to create repetitive (8) structures of AND gate as shown below.

library ieee;


entity and8 is

port (A, B : in std_!ogic_ vector (1 to 8);

0: out std_logic_vector (1 to 8));

end and8;

architecture and8 _arch of and8 is

component and

port ( X, Y: in std_logic;

Z : out std_logic);

end component;

begin

G1 : for c in 1 to 8 generate

U1 : and port map (A(c), B(c), O(c));

end generate;

end and8 _arch;

An equivalent generate statement in Verilog is :

generate

genvar c;

for (c = 1; c < = 8; c =c + 1)

begin : g8 // g8 is a Label for predefined word begin and it is must

and (O[c], A[cl, B[c]);

end

endgenerate

We declare the parameters (For example : Bus width) as constants within a VHDL program. The value of a constant must be known when a VHDL program is compiled. But in many applications it is useful to design and ~ompile a VHDL program without

Copynqhted material

Fundamentals of HDL 4- 55 Structural Description

specifying the values of some parameters. VHDL provides this facility with generic statement and Verilog provides this facility with parameter statement.

Generic and Parameter Declaration

The constants whose values are not specified within a VHDL program are called generic constants. These are defined in an entity declaration with a generic declaration before the port declaration. The syntax of generic declaration is given below.

entity entity_ name is generic ( constant_names : constant_type;

constant name : constant_type;

constant name : constant type);

port signal_name : mode signal_ type;

signal_ names : mode signal_ type;

signal_names : mode signal_type);

end entity_name;

For example, consider an arbitrary_width bus inverter. The bus_width for this bus inverter is user_specifiable. The VHDL program for this bus inverter is given below.

library ieee; use leee.std_logic_1164.all;

entity businv is

generic (width: integer: = 8);

port ( A: In std_logic_vector(width-1 downto 0);

B : out std_logic_vector (width-1 downto 0));

end businv;

architecture businv arch of busin v Is

component inv port ( I: In std_logic)

end component;

begin

0 : out std_logic);

gl:

u1:

for w In width-1 downto 0 generate

inv port map (A(w), B(w));

end generate;

end businv _arch;

Multiple (in our example, 8) copies of this inverter can be instantiated in the program by taking different user-specified widths.


Fundamentals of HDL 4- 56

An equivalent generate statement in Verilog is :

module businv (A, B) parameter c = 8;

input (c:1J A;

ouput (c:ll B;

generate

genvar i;

for (i = 1; i < = c; i = i + 1)


begin : gc 11 gc is a label for predefined word begin and it is must

inv (B(i), A(il);

end

endgenerate

n• Example 4.16 : Structural description of (N + 1) - Bit magnitude comparator using Generate statement.

We have seen the structural description of 3-bit comparator in listing 4.20. Here, we will see the description of (N + 1) - bit comparator using generate statement.

Listing 4.25 : HDL description of N-bit magnitude comparator using generate statement.

VHDL N-Bit Magnitude Comparator Using Generate Statement

library ieee;

use leee.std _logic_ 1164.all;

entity comp _gen is

generic (N : integer:= 3);

port (A, B: in std_Jogic_vector (N downto 0);

AgtB, AltB. AeqB: buffer std_logic);

end comp _gen;

architecture compare of comp _gen is

component full_adder

port (11, 12, 13 : in std_logic; 01, 02 : out std_logic);

end component;

com ponent inv

port (11 : in std_logic; 01 : out std_logic);

end component;

component nor2

port (11, 12 : in std_logic; 01 : out std_Jogic);

Copyrighted material.


end component;

component and2

port (11, 12: in std_logic; 01 : out std_logic);

end component;

signal Sum, Bbar: std_logic_vector (N downto 0);

signal C, eq: std_logic_vector (N + 1downto0);

for all : full_adder use entity work.bind32 (full_add);

for all : inv use entity work.bindl (inv_O);

for all: nor2 use entity work.bind2 (nor2_7);

for all: and2 use entity work.bind2 (and2_7);

begin

C(O) < = 'O';

eq(O) < = '1';

Gl : for i in 0 to N generate

vl : inv port map (B(i), Bbar(i));

FA : full_ adder port map (A(i), Bbar(i), C(i), Sum(i), C(i+ l));

Al : and2 port map (eq(i), Sum(i), eq(i+l));

end generate Gl;

AgtB < = C(N+l);

AeqB <= eq(N+l);

nl : nor2 port map (AeqB, AgtB, AltB);

end compare;

Verilog N-Bit Magnitude Comparator Using Generate Statement

module comp_gen (A, B, AgtB, AltB, AeqB);

parameter N = 3;

input (N:OJ A, B;


wire (N:O( Sum, Bbar;

wire (N+ l : 0( C, eq;

assign C(OI = l'bO;

assign eq(OI = l 'bl;

generate

genvar i;

for (i = O; i < = N; i = i + 1)

begin : u

not (Bbar(i), B(i));


Fundamentals of HDL 4 . 58 Structural Description

full_adder FA (A(il, Bbar(i], C(il, Sum(i), C(i+ l));

and (eq(i+l], Sum(i], eq(i));

end

endgenerate

assign AgtB = C(N+l];

&•sign AeqB = eq(N+ l);

nor (AltB, AeqB, AgtB);

endmodule

,,_. Example 4. 17 : Structural description of an N-bit Asynchronous Down counter using generate.

The Fig. 4.5 shows the 4-bit asynchronous down counter using JK flip-flops. Here, the clock signal is connected to the clock input of only first flip-flop. This connection is same as asynchronous/ripple up counter. However, the clock input of the remaining flip-flop is triggered by the Q output of the previous stage.

High --.-- -----.-------..-------.· .......... --...,

QN

K 00 K 01 K 02 K 03 K QN

Fig. 4.34 Logic diagram of asynchronous n-bit counter

IJI. Listing 4.26 : HDL description of an N-bit asynchronous down counter using generate statement.

VHDL N·Bit Asynchronous Down Counter Using Generate Description

library leee;

uae ieee.std_logic_1164.all;

entity asyn_ctr is

generic (N : integer:= 4);

port ( CP : in std_logic;

-- This is a 4-bit counter.

Q, Obar : buffer std_logic_vector (N-1 downto 0));

end asyn_ctr;

archi tecture asyn_ctr_gen of asyn_ctr is



component JK _FF is

port( 11, 12, 13 : in std_logic;

01, 02 : buffer std_logic):

end component ;

for all : JK_FF use entity work.JKFF' (F'F);

signals : std_logic_vector (N downto 0);

begin

s < = (Q & CP);

-- sis the concatenation of Q and CP. Th.is concatenation is necessary to

-- specify the clock of each JK flip-flop in generic statement.

Gnlop : for i in (N-1) downto 0 generate

Gt : JK_FF port map ('1', '1 ', s(i), O(i), Obar(i));

end generate GnLop;

end asyn _ctr _gen;

Verilog N-Bit Asynchronous Down Counter Using Generate Description

module asyn_ctr (CP, Q, Obar);

parameter N = 4;

input CP;

output [N-1:0[ 0, Obar;

wire [N:O) s;

assigns = {O. CP};

II This is a 4-bit counter.

/* sis the concatenation of Q and CP. This concatenation is necessary to

specify the clock of each JK flip-tlop in generic statement. •I

generate

genvar i;

for (i = O; i < N; i = i + 1)

begin: u

JK_FF FF (1'b1, 1'b1, s[il . Q[i), Obar[iJ);

endgenerate

endmoduie

u• Example 4.18 : Structural description of an N-bit memory word using Generate.

We have seen the listing of single memory cell in example 4.12. This single memory cell can be expanded to N-bit using the generate statement. This is illustrated in listing 4.27.



..,_ Listing 4.27 : HDL description of N-bit memory word using generate

VHDL N-Bit Memory Word Using Generate

library ieee;


entity memory_ word is

generic (N : integer:= B);

port ( D_in: in std_logic_vector (N downto O);

Se!, R _ W : in std _logic;

D_out : out std_logic_vector (N downto 0));

end memory_ word;

architecture word _gen of memory_ word is

component memory_ cell

port (Se!, RW, Din: in std_logic;

01 : buffer std_logic );

end component;

for all: memory_cell use entity work.memory (mem_cell);

begin

G 1 : for i In 0 to N generate

M: memory_cell port map (sel, R_W, D_in(i), D_out(i));

end generate;

end word_gen;

Verilog N-Bit Memory Word Using Generate

module memory_word {D_in. sel, R_W, D_out);

parameter N = B;

input (N:O) D_in;

input sel, R_W;

output [N:O) D_out;

$1 generate

genvar i;

for (i = 0; i < = N; i = i + 1)

begin: u

memory Ml {sel, R_W, D_in [ii. D_outfi l);

end

endgenerate

endmodule



n'* Example 4.19 : Structural description of N-bit register. The group of flip-flops can be used to store a word, such a group is called

register. The Fig. 4.35 shows the N-bit register constructed with D flip-flops. This register is called buffer register. Each D flip-flop is triggered with a common clock pulse.

Fig. 4.35 N-bit register

~ Listing 4.28 : HDL description of N-bit register using - VHDL and Verilog.

VHDL Description of N-bit register

library ieee;


entity Regis is

generic (N : integer : = 8); -- 8-b it register

port( D: in std_logic_vector(N- 1 downto 0);

CP : in std_logic;

Q, Obar: out std_logic_vector(N-1down.to0));

end Regis;

architecture register_ nBit of Reg is is

component D_FF is

port( 11, 12 : in std_ logic;

01, 02 : buffer std_logic):

end component ;

begin

build: for i in 0 to N- 1 generate

for all : D _FF use entity work.OFF (FF );

begin

d : D_FF port map(D(i),CP , Q(i), Qbar(i));

end generate b uild;

end register_nBit ;


Fundamentals of HDL

Verilog Description of N-bit register

module Regis (D, CP, Q, Obar)

parameter N = 8;

input CP;

input (N-1 : OJ D;

output (N- 1: OJ Q, Obar;

generate

genvar i;

for (i = O; i < N; i = i + 1)

begin : u

4 - 62

D_FF FF (D(i), CP, Q(iJ, Obar(i));

end

endgenerate

end.module


111• Example 4.20 : Structural description of N-bit shift register. The binary information (data) in a register can be moved from stage to stage

within the register or into or out of the register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to a group of registers called 'shift registers'. They are very important in applications involving the storage and transfer of data in a digital system.

The Fig. 4.36 shows the N-bit left shift register. Here, the data is shifted left by one bit on receiving every clock pulse. Din is a serial input signal and Dout is a data output signal.

Din

'--~~~~~-+~~~~~~+-~~~~~-<-~cP

Fig. 4.36 N-bit left s hift register

~ Listing 4.29 : HDL description of N-bit left shift register

VHDL Description of N-bit Left Shift Register

library ieee;


entity Regis_ Ls is

generic (N : integer:= 8); -- 8-bit regist er


Fundamentals of HDL

port( Din: in std_logic;

CP : in std_logic;

Dout : out std_logic;

4. 63

Q, Obar: out std_logic_vector(N-1 downto 0));

end Regis_Ls;

architecture register_nBit of Regis_Ls is

component D _FF is

port( 11, 12 : in std _logic;

01, 02: buffer std_logic);

end component ;

begin

build: for i in 0 to N-1 generate

for all : D_FF use entity work.OFF (FF);

signal D : std_logic_vector (N downto O);

begin

D < = (Q & Din);

d: D _FF port map(D(i), CP, Q(i), Obar(i));

end generate build;

Dout < = D(N);

end register_nBit;

Verilog Description of N-bit Left Shift Register

module Regis (Din, CP, Dout, Q, Obar)

parameter N = 8;

Input Din, CP;

output Dout;

output (N-1 : OJ 0 , Obar;

wire (N:O] D;

assign D = {Q, Din};

generate

genvar i;

for (i = O; i < N; i = i + 1)

begin : u

D_FF FF (D(i]. CP, Q(i], Obar(i]);

end

endgenerate

assign Dout = D(N];

endmodule



Fundamentals of HDL 4- 64 Structural Description

Review Questions 1. List the lriglrliglrts of stmcl11ral dt'Scription.

2. Explain tire organization of tire structural description witlr tire help of exarrrple.

3. Lists tile built-in gates supported by Verilog.

4. Wlmt is binding ?

5. Explain the bi11di11g betwee11 e11tity a11d architecture in VHDL.

6. Explain tire binding betwce11 entity a11d co111po11e11t in VHDL.

7. Explain tire binding between a libran; and 111od11le in VHDL.

8. Explain the binding between a library and compo11ent in VHDL.

9. Explain the binding between two modules i11 Verilog.

JO. Write a structural descri11tio11 of 3 : 8 decoder witlr actit1e lrigh enable input.

11. Write a structural description of T flip-fl.op.

12. Design a sequential circuit of three-bit et1e11 counter and write a str11ct11ral descriptio11 for it.

13. Write a structural descriptio11 for a 4-bit synclrrono11s binary co1111ter.

14. Write a str11ct11ral description for right shift register.

ODO


fundamentals of hdl (first 4 chapters only) - godse

Engineering

summary of operators

rotate operators

unary arithmetic operators

bitwise logical operators

vhdl data types

binary arithmetic operators

types of descriptions

brief history of verilog