fundamentals on electronics part 2: a design oriented ...jose silva-martinez 3 3 pipeline cell...
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Jose Silva-Martinez 0
1st African Webinar Series on Fundamentals on Circuits, Systems, and Emerging Technologies
Jose Silva-Martinez
Department of Electrical and
Computer Engineering
Texas A&M University
Fundamentals on Electronics Part 2: A
Design Oriented Teaching Methodology
Jose Silva-Martinez 1
Outline
• Introduction
Background
• TechnologyTransistor models
• Basic Configurations
Current mirrors and diff pair
• Amplifiers for Pipeline ADCsCapacitive loaded amplifiers
• Amplifiers for Sigma-Delta ModulatorsResistive loaded amplifiers
• Conclusions
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Conventional (Nyquist) ADC
A/D
Data
Out
Vin
SQNR=6.02*n+1.76
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Pipeline Cell (sub-ADC and MDAC)
Φ1
Φ2
Φ2
Φ1
M
C1
C2
A
MUX
-VR
VR
VR/4
VIN
-VR/4
VOUT
Sub-ADC MDAC
1.5bits/stage
S/H and Gain Stage
VD
AC
INC
INC
VCq
VCqq
21,2
11,1
1
DACC
OUTC
VCq
VCqq
22,2
12,1
2
1
2
1
21C
CV
C
CVV DACINOUT
021 CC qq
Implementation of Pipeline Stages
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MDAC
Φ2
Φ1
Φ2
Φ1eC1
AVOUT
VIN
Ф2
CL
C2 x
VDAC
Ideal (C1=C2)
Ideal Transfer Function (1.5bits/stage):
Φ2
Φ1
Φ2
Φ1eC1
AVOUT
VOS
VIN
Ф2
CL
C2
CP
x
VDAC
Real (C1≠C2), finite OPAMP, non-
ideal switches
Real Transfer Function (1.5bits/stage):
Implementation of Pipeline Stages
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Design of Operational Amplifiers for High-
Performance ADCs
Part II: Basic Modeling
Jose Silva-Martinez
Department of ECE
Texas A&M University
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MOS Transistor: Basic Model
substrate
P+ P+
S G D
P-channel
N
N+
B
D
S
BG
P-type transistor
Thick oxideThin oxide
Polysilicon (heavily doped)
L
W
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OUTPUT RESISTANCE (SATURATION REGION)
Drain current
substrate
P+ P+
S G D
N+
B
Depletion region
Channel length modulation is a second (unreliable) order effect!
(Badly) Represented in SPICE by using or a more complex model.
Simulated and experimental results might be off by more than 100%
Channel Length Modulation
DSTGS
eff
OXD VVV
L
WCi
1
2
2
Leff
Lch
0
VD
S
IDS
VGS2
=0
Measure this parameter!
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Transistor Model: Capacitances
23
2
substrate
N+ N+
VS=0 VG>VTVD>0
P (NA)
P+
B
Csb Cdb
Cchb
Cgs
CgdoCgso
L*W*CjC
CjswCjbC
CjswCjbC
L*Wt
C
ChB
DB
SB
OX
OXGCh
Triode
2
L*W*CjdPd*CjswAd*CjdC
2
L*W*CjsPs*CjswAs*CjsC
CC
L*W*t2
L*W*
tC
DB
SB
GSGD
D
OX
OX
OX
OXGS
Pd*CjswAd*CjdC
L*W*Cjs*3
2Ps*CjswAs*CjsC
L*W*t
C
L*W*t
L*W*t
*3
2C
DB
SB
D
OX
OXGD
D
OX
OX
OX
OXGS
Saturation
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Small Signal Model (Saturation region)
Small signal model (saturation region)
B
gogmbvbs
gmvgs
B
D
Cdb
Cgd
Cgs
Cbs
S
S’
GD
....vv
iv
v
i
vv
iV1VV
L
W
2
Ci
2V2VV
V1VVL
W
2
Ci
bs
Qbs
Dds
Qds
D
gs
Qgs
D
Q
DS2
TGSeff
OXD
FSBF0TT
DS2
TGSeff
OXD
SBF
m
Qbs
T
Q
TGS
eff
OX
Qbs
Dmb
Q
TGS
eff
OX
Qds
D
Q
TGS
eff
OX
Qgs
Dm
V
g
v
V*VV
L
WC
v
ig
VVL
WC
v
ig
VVL
WC
v
ig
22
2
20 bsmbds0gsmDD vgvgvgIi
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Other important effects! Mobility of the carriers is voltage dependent
MOBILITY DEGRADATION: VERTICAL ELECTRIC FIELD
A bit more accurate equation:
L
V
V1
1
VVTHETA1
1
DS
MAX
0TGS0
Electric Field
VELOCITY
TGS0
VVTHETA1
1
MOBILITY DEGRADATION: LATERAL ELECTRIC FIELD
L
V
V1
1
L
V1
1
DS
MAX
00
CRIT
DS0Effect of the drain-source electric filed
THETA IS A FITTING PARAMETER ~ 0.1-0.5 V-1
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Saturation region :
As V(x) increases Qinv(x) decreases. Its minimum is at the drain
the drain is in the pinch-off condition.
If VDS > Vsat,
satDSA
VVqN
2L
DSsatDS2
AsatDS2
A
V1VVLqN
1
VVLqN
21
1
LL
L
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• Avalanche: drain current ID and a substrate current IB
• The substrate current may contribute to latch-up
• The device noise increases
• The output impedance decreases
• Carriers can be trapped on the oxide and the VTh changes (hot
electron effect)
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Saturation region :
DSsatDS2
AsatDS2
A
V1VVLqN
1
VVLqN
21
1
LL
L
More accurate expression of the output conductance : very non-linear!
(first order) (short channel) (velocity saturation) (avalanching)
DS
S
DS
D
DS
T h
mDds
V
I
V
I
V
VgIg
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Deep Submicron Technologies: first order equations
are really off from real system performance
Qgs
d
v
iGm
Linear function
Hot carriers
Quadratic function
Subthreshold region
Characterize your technology before you start you design!!
Quasi-linear Gm
Deep Submicron Technologies: Cadence
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Deep Submicron Technologies: Linearity Issues
Sweet spots are quite sensitive to PVT variations
Linearity could be good for small signals only: hard to use it in broadband
applications, but….
Large HD2 and HD3 requires huge power consumption and large parasitics
Characterize for Gm/Cgs (speed)
Measure Cgd
Measure gds and Av
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Design of High-Performance Mixed-Mode
Systems
Part III: Basic Building Blocks
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Current Mirrors
VGS
VDS
+
_
+
_
DS
2
TGS
OXn
DV1VV
L
W
2
CI
ID
TGDTGSDSTGS VVVorVVVandVV
If
DS
OXn
D
TGS
V1L
W
2
C
I2VV
or
VGS
+
_
ID
1
ID
2
1DS
2
TGS
OXn
1DV1VV
L
W
2
CI
M1=M2 =>
2DS
2
TGS
OXn
2DV1VV
L
W
2
CI
ID1 generates the voltage VGS
VGS generates ID2
M1 M2
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Current Mirrors: Accuracy limitations
VGS
+
_
ID1 ID2
M1 M2
In general (W/L)2=N(W/L)1, most probably VT1VT2, then
1D
1DS12
1TGS1P
2DS22
2TGS2P1D
1DS12
1TGS
1
OXn
2DS22
2TGS
2
OXn
2D
2DS22
TGS
2
OXn2D
NIV1VVK
V1VVKI
V1VVL
W
2
C
V1VVL
W
2
C
I
V1VVL
W
2
CI
1DS12DS2 VVError
L
1 Long devices reduce the
error; make VDS1=VDS2
1P2P KKError
Errors can be reduced (but not
eliminated) by using replicas of the
main device and good layout!
1T2T VVError
Good solution ==> use cascode structures
Effective mobility and
threshold voltages are
sensitive to VDS.and
Vdsat
Current Mirrors
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DC Current Mirrors: Second-Order Effects
VGS
+
_
ID1 ID2
M1 M2
NV1VV
V1VV
I
I
1DS1
2
1TGS1n
2DS2
2
2TGS2n
1D
2D
12Error
Error is minimized by using
replicas of the basic device
1T2TVVError
crit
dsgs
0
L
V1
1
V1
1
W
VT
VT0
1-3m
Mobility degradation
After good layout: Tolerances in N are in the range of 0.5-2 %. Usually
mismatches are inversely proportional to gate area!
Intra-die VT mismatches are
inversely proportional to
gate area!
Current Mirrors
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Small signal analysis: AC components id1-2
VGS
+
_
ID1 + id1
M1 M2
02021d
011m
2m
2dvgi
gg
gi
Notice:
•gm1vgs1 is controlled by its own terminal
==> represents an impedance (conductance =gm1)
•The output resistance is given by r02If the capacitors are considered,
g01=1/r01==> g01+sCeq
g02==> g02+sCeq2
Also, you have to consider the
overlapping capacitor CGD2
..vsCg
gg
Cs1
i
gg
gi
022eq02
011m
1eq
1d
011m
2m
2d
G1 D1,G2 D2
iD1 iD2
r01r02
gm1vgs1
gm2vgs2
ID2 + id2
Current Mirrors
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IMPEDANCE: Basic Configurations
Vd1
+
_
id1
M1
G1 D1
iD1
r01gm1vgs1
011m
1
1d011m1d
gg
1Z
vggi
VSS
vin
idG1 D1
id
r01gm1vin
vin
VB
If Vd~0
but be careful
when using this
approximation
Can you ignore gmb?
VdVd
𝑖𝑑 = 𝑔𝑚1 + 𝑔01 𝑣𝑖𝑛 − 𝑔01𝑣𝑑
𝑍𝑖𝑛 =1 +
𝑍𝐿𝑟01
𝑔𝑚1 + 𝑔01
𝑍𝑖𝑛 ≈1
𝑔𝑚1 + 𝑔01
Cascode Transistors
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Output impedance: Cascode stage
OUTPUT IMPEDANCE
D2
iD2
r02
id2
gm4vs4
v02
S4
r04
0ini02
2dout
v
iY
4s022d
4s4m044s022d
vgi
vggvvi
04024m0402outrrgrrZ
Notice that most of the AC current re-circulates within the cascode device and only id2 is extracted from r02 !!
This is the main advantage of the cascode architecture
g02 vs4
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Improved (self regulated) current source
ID
1
ID
2
M3
M4
VGS1
+
_M1 M2
+
_VDS2
+
_
VDS4
0402V4mout
rrA1gr
-AVVs4
D2
iD2
r02
iD2
gm4(1+AV)vs4
S4
r04
Similar to double cascode
Key issue: Please understand the concept!!
Signal swing Vgs increases drastically due to auxiliary amplifier
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Noise
Noise Unwanted electrical signals generated in the device
or externally and coupled to the output of the system.
Make impossible to detect, with sufficiently quality,
signals with an amplitude comparable to the noise
level.
Thermal Noise
Intrinsic Flicker Noise
Noise
Extrinsic Surrounding Circuitry
(PSRR, CMRR)
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Thermal Noise in resistors
Due to the random flow of the carriers, thermal noise
(undesired current variations) is produced due to
Collisions of carries with the crystal
Collisions between carriers
Fluctuations increase with temperature
Random fluctuations
RMS value of these variations is quasi-uniformly spread up to several GHz
Power Noise Density: Usually noise is characterized by its Spot power
noise (RMS power in bandwidth of 1 Hz) at a given frequency
vn12
R1f
vn12
1x
2
1n kTR4fv
fX
dfvvoltsv0
2
1n
22
ntotal
This integral gives infinite total noise, but
usually capacitors limit the bandwidth
leading to a finite value
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Thermal Noise in resistors
Thermal noise in resistors can be characterized in terms of voltage noise
density or current noise density
1
2
1n kTR4v
vn12
R1
in12=4kT/R1
R1
Hz/Ampsi
Hz/Voltsv
22
1n
22
1n
Units
02
2
total
2
2
n
2
2
n0
C
kT4df
RC1
kTR4v
ascomputedispowernoisetotal,and
RC1
kTR4v
sRC1
1v
+vin
-
vn Rv0
C
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Flicker Noise (1/f)
- Due to imperfections in the Si - SiO2 interface. The traps and
imperfections interfere with the charges flowing through the
channel.
- Strongly dependent of the technology
kF = fitting parameter
f = frequency
IDS = drain current
fLC
Iki
2
ox
DSF2
d
Jose Silva-Martinez 28
Typical noise spectrum
f
veq2
fc
Flicker
Thermal
f(log)
2eqv
IM3 IM3
fo1 fo2
signal power of the signal
noise + THD power noise + power THD
Corner frequency is obtained
equating the expression for
Flicker and Thermal noise and
solving for fc
Signal tones
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Differential Pair: Linear range is limited to VDSAT
id1
IB
M1 M1
v1 v2
id2
2
1DSAT
21211m2d
2
1DSAT
21211m1d
V2
vv1
2
vvg
2
IBi
V2
vv1
2
vvg
2
IBi
If both transistors are saturated and IB is ideal (rIB=)
2T2gs
OXn
2d
2
T1gs
OXn
1d
2d1d
VVL
W
2
Ci
VVL
W
2
Ci
IBii
Solving these equations => Valid for |v1-v2| < 21/2VDSAT1
IB
IB/2
-21/2VDSAT121/2VDSAT1
LINEAR
REGION
V1-V2
-VDSAT1
VDSAT1
Jose Silva-Martinez 30
Differential Pair
id1
IB
M1 M1
v1 v2
id2
The diff pair is a nonlinear circuit
If vd=v1-v2<VDSAT1 =>
IB
-VDSAT1VDSAT1
LINEAR
REGION
V1-V2
2
1DSAT
21
211m2d1dV2
vv1vvgii
Non-linear term
21BOXn2d1d
vvIL
WCii
Note:
Linear range increases for large VDSAT1
VGS is also increased (limited by supply
headroom)
Jose Silva-Martinez 31
Basic Operational Transconductance Amplifier
id1
IB
M1 M1
v1 v2
id2
DESIGN CONSIDERATIONS:
Vd=v1-v2 < VDSAT
V1,2 -VSS >VGS1+VDSATB
21mout
21BOXnout
vvgi
or
vvIL
WCi
iout
VSS
VDD
id1
For an ideal current source and ignoring the effects of gmb, and transistor mismatches, then
iout=0 for v1=v2 ==> rejection to common-mode (noise) signals present at the input!
Sensitive to differential signals
op1oout
21outmout
IIrrr
vvrgv
For small signals, ignoring the capacitors:
Jose Silva-Martinez 32
Unbalance in Frequency Response: pole-zero pair
id1
IB
M1 M1
v1
id2
iout
id1 0.5gmvd 1/gmp’CX
Vx
gmR0
1/R0C0
VX
gmpvx
CO
Vo
-0.5gmvd
Ro
d
00
0md
00
0m
'
mp
0
'
mp
mp
0 VCSR1
Rg5.0V
CSR1
Rg5.0
g
CS1
g
g
V
Vout
AV1
AV2
OPONO RRR MP’ MP
d
00
0m
'
mp
0
'
mp
mp
0 VCSR1
Rg5.0
g
CS1
g
g
1V
𝑠 = 𝑗𝜔
Differential
Single ended
Jose Silva-Martinez 33
Issue Find the best possible values for Wn, Ln, Wp, Lp, IB, Wb, Lb
id1
IB
M1 M1
v1
id2
ioutVX
M2 M2
v2
Main Specs: 7 unknowns, how many equations?
Fundamental equations: Example
Small Signal Transconductance
Av
CLoad
GBW
Phase margin
Slew-rate
Noise level
CMRR (deals with the tail current)
Minimize power
Noise due to the tail current is not very relevant in this case!
Notice that Noise and PSRR properties held until the frequency the parasitic pole is negligible
Jose Silva-Martinez 34
element 0:m1 0:m2 0:m3 0:m4
model 0:nmos 0:nmos 0:pmos 0:pmos
id 50.8791u 49.1209u -50.8791u -52.3328u
ibs -1.3599f -1.3599f 0. 0.
ibd -6.0353f -4.5000f 5.9294f 9.0000f
vgs 1.0467 1.0467 -988.2359m -988.2359m
vds 1.5585 1.0467 -988.2359m -1.5000
vbs -453.2843m -453.2843m 0. 0.
vth 935.7189m 937.3317m -796.3484m -795.0981m
vdsat 85.8964m 84.6227m -153.0961m -154.1901m
beta 10.5141m 10.4579m 3.4418m 3.4921m
gam eff 615.7505m 617.1949m 441.0793m 439.6443m
gm 917.2562u 898.5322u 530.5610u 542.4369u
gds 3.1829u 3.6270u 3.1005u 2.6071u
gmb 241.1968u 236.4976u 124.0201u 126.5817u
cdtot 168.5315f 174.6577f 190.8988f 179.7177f
cgtot 763.3385f 763.1155f 797.8187f 798.3587f
cstot 786.8845f 786.8845f 872.1273f 872.1273f
cbtot 253.8979f 261.0102f 304.0716f 292.1262f
cgs 660.5874f 660.5874f 707.1273f 707.1273f
cgd 71.8408f 71.2364f 71.2593f 71.9114f
Design Example: Check your operating point and parameters!
Jose Silva-Martinez 35
Design of Operational Amplifiers for High-
Performance ADCs
Part III: Amplifiers for Pipeline ADCs
Jose Silva-Martinez
Department of ECE
Texas A&M University
Jose Silva-Martinez 36
SR Function of an OTA Based SC Circuit
For input voltage swing is less than 𝑽𝒅𝒔,𝒔𝒂𝒕, the input transistors operate as a diff pair.
For input voltages higher than 𝑽𝒅𝒔,𝒔𝒂𝒕, the input transistors operate in slew-mode: ON or OFF.
The OTA delivers constant amount of current at its output (during slew phase) delivering a quasi-constant current.
vi+
vo+vo-
vi-
VDD
M1 M2
io+io-
vi+-vi-
io+io-
-VDS-SAT VDS-SAT
IBIB
2IB
2IB
Linear
Region
Slew
Region
Slew
Region
Jose Silva-Martinez 37
The initial Vx voltage at amplifier input would be even larger when 𝑽𝒄𝟏,𝟐 𝒕𝟎 andthe input voltage 𝑽𝒊(𝒕𝟎+) have opposite polarity. Slew effects may appear even forsmall signals
This leads to the larger slewing time.
C2
C1
vo
vi-
+
C2
C1
vo
vi
-
+
vx
IB
vx
ix
Time
Slew Region
IB /C1
t0
Linear Settling
VX
0
t1
VX (t0+)
VDS,SAT
𝑉𝑥(𝑡0+) = 𝑉𝑖(𝑡0+) − 𝑉𝑐1 𝑡0
If the capacitors are Pre-charged
Slew-Rate: OTA Based SC Circuit
Unloaded switched-capacitor circuit: Step Response
𝑉𝑥 𝑡 = 𝑉𝑥 𝑡0+ −𝐼𝐵𝐶1
. 𝑡 − 𝑡0+
Jose Silva-Martinez 38
SR is a function of the capacitor’s initial conditions as well as input signal:
Increasing bias current reduces Tslew : POWER HUNGRY SOLUTION
𝑇𝑠𝑙𝑒𝑤 = 𝑉𝑥 𝑡0+ − 𝑉𝑑𝑠_𝑠𝑎𝑡𝐶1𝐼𝐵
1 +𝐶𝑃 + 𝐶𝐿 1 +
𝐶1 + 𝐶𝑃𝐶2
𝐶1
Time
Slew Region
Ix /C1+Cp
t0
VX
0
t1
VX (t0+)
VDS,SAT
Linear Settling
Larger Initial
Voltage
Smaller (Dis)charging CurentC2
C1
vo
vi
-
+
C2
C1
vo
vi
-
+
vx
IB
vx
CP
CL CL
CP
ix
𝑉𝑥 𝑡0+ =𝐶1 𝑉𝑖 𝑡0+ − 𝑉𝑐1 𝑡0 − 𝐶𝑃𝑉𝐶𝑃 𝑡0
𝐶1 + 𝐶𝑃 +𝐶2𝐶𝐿𝐶2 +𝐶𝐿
+
𝐶2𝐶𝐿𝐶2 +𝐶𝐿
𝑉𝐶𝐿 𝑡0 − 𝑉𝑐2 𝑡0
𝐶1 + 𝐶𝑃 +𝐶2𝐶𝐿𝐶2 +𝐶𝐿
Slew-Rate: OTA Based SC Circuit
Loaded switched-capacitor circuit: Step ResponseNaderi, TCAS-I, Nov. 2018
Jose Silva-Martinez 39
SR Function of an OTA Based SC Circuit
Different slewing-time of the Class A residue amplifier based on the initial stored-voltage
on the load capacitor: a) VREF+ b) Common-mode Voltage c) VREF-
The more demand for voltage slewing swing at the output causes larger voltage step atthe input of the RA during its linear region.
The 0.25% settling time for each case is 0.8 nsecs, 1.25 nsecs and 1.75 nsecs,respectively.
The worst-case condition increases the settling time by more than a factor of 2.
Jose Silva-Martinez 40
OTAs for high speed SC circuits • Folded-Cascode OTA:
eff_L
TAIL
C
ISR
For SR, the current
efficiency is 50 %
Vin-
Vin+
VBN
VBP
Vout-
VCMFB
VBN
VBP
Vout+
VCMFB
VSS
VDD
TAILI2
TAILITAILI
M1 M1
M3VBIASM2 M2
M3
M4
M5
M3
M4
M5eff_L
m
C
gGBW
1
33
3
SBGS
mnd
CC
g
2ITAIL2ITAIL
J. Adut, et.al., TCAS-I, 2006
Potential solutions
Jose Silva-Martinez 41
Vin-
Vin+
VBN
VBP
Vout-
VCMFB
VBN
VBP
Vout+
VCMFB
VSS
VDD
M1 M1
M2 M2
M3
M4
M5
M3
M4
M5
M7 M7
N : 1 1 : N
N1
I4 TAIL
N1
NI2 TAIL
N1
NI2 TAIL
Current-mirror-cascode
OTA: 2 parasitic poles
eff_L
TAIL
C
I
N
NSR
1
2
For SR, current efficiency is >50%
(Better than folded-cascode OTA if N>1)
eff_L
m
C
NgGBW
1
3
7
1
1
GS
mnd
C
g
N
OTAs for high speed SC circuits
Potential solutions
Jose Silva-Martinez 42
OTAs for high speed SC circuits
Vin-
Vin+
VBN
VBP
Vout-
VCMFB
VBN
VBP
Vout+
VCMFB
VSS
VDD
M1P
M2 M2
M3
M4
M5
M3
M4
M5
3
I4 TAIL
3
I4 TAIL
3
I4 TAIL
VDD
M1N
3
I4 TAIL
VSS
M1N
M1P
• Double Diff pair
OTA: 2 parasitic
poles + 1 Zero
eff_L
TAIL
C
ISR
3
4
For SR, the current efficiency is 66 %
(In practice better than FC- OTA)
N
Pm
P
Nmm s
g
s
gG
11
11
44
4
CSBGS
mnd
C
g
Potential solutions
Jose Silva-Martinez 43
Multi-Path OTA
Vin-
Vin+
VBN
VBP
Vout-
VCMFB
VBN
VBP
Vout+
VCMFB
VSS
VDD
1 : N
1 : M
N : 1
M : 1
NM1
I8 TAIL
1NM
I1NM2 TAIL
1NM
I1NM2 TAIL
M1 M1 M1 M1
M6M6
M7M7
M2 M2
M3
M4
M5
M3
M4
M5
12
1
21
1
1
1
11111
PN
m
NN
m
N
mm
ss
Mg
ss
Ng
s
gG
NMC
g
GS
mnd
16
6
eff_L
TAIL
C
I
NM
NMSR
2
1
1
J. Adut and et.al., TCAS-I, 2006
Jose Silva-Martinez 44
Step Response: SR, poles and zeros
0 1 2 3 4 5 6 7 8
Time (nsecs)
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
Outp
ut
vo
ltag
e (V
)
Folded-cascode
Complementary
Current mirror
3-path
5 6 7 8
Time (nsecs)
0.485
0.490
0.495
0.500
0.505
Outp
ut
vo
ltag
e (V
) 3-path
Complementary
Folded-cascode
Current-mirror
Parameter F-Cascode Current mirror 2 diff pairs 3-path OTA
DC gain [dB] 55.9 56 60.6 60.4
Ts[0.1%] [ns] 5.3 4.9 4.7 4.2
Settling error [%] 1.15 0.75 0.95 0.42
Ideal output
Jose Silva-Martinez 4545
How to enhance efficiency? Recycle idle currents by actively using idle devices → RFC
Power Inefficiency Current sink devices conduct most current, but are idle as far as signal is concerned
Current sink devices contribute significant noise at the output
Folded Cascode Best suited single-stage amplifier for high speed and low voltage operation
Not as power efficient as the telescopic; half efficiency!
Vin-Vin+ Vout+
GND
Vbp1
Vbp2
Vbn2
VDD
M1 M2
M5 M6
M7 M8
M9 M10
M0
IT
IT/2IT/2
Vbp2
Vbn2
Vout-
VCMFB VCMFB
Vbn1 ITIT
M3 M4
Recycling Folded Cascode (RFC)
Architecture
Vin-Vin+Vout+
GND
Vbp1
Vbp2
Vbn2
VDD
M1a M2a
M5 M6
M7 M8
M9 M10
M0
IT
I T (K
-1)/
4
I T (K
-1)/
4
Vbp2
Vbn2
Vout-
VCMFB VCMFB
M3b M4bM3a
M1b M2b
M4a
1 : KK : 1
K I
T/4
K I
T/4
I T/4
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RFC Characteristics
Transconductance and Output Impedance
FC
RFC
“The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier,” R. S.
Assaad, et.al., IEEE Journal of Solid-State Circuits, pp. 2535-2542, September 2009.
Jose Silva-Martinez 4747
RFC Characteristics
Phase Margin and pulse response
GBWFC
GBWRFC
At GBWFC (K=3)
-5.5 deg, but RFC uses half power
At GBWRFC (K=3)
-9.9 deg, but FC uses twice power
FC
RFC
Jose Silva-Martinez 4848
RFC Experimental Results
Slew Rate Input
1Vpp, 5MHz
Slew Rate
FC = 42.15 V/µs
RFC1 = 77.79 V/µs
RFC2 = 48.12 V/µs
Phase Margin
Even at large step no
observable overshoot which
indicate good phase margin
The Recycling Folded Cascode shows
improved Slew Rate
FC
RFC1
RFC2
Jose Silva-Martinez 4949
RFC Experimental Results
Distortion Input
Two tones around 1MHz (100kHz separation), 1Vpp
IM3
FC = 61.7dB
RFC1 = 66.1dB
RFC2 = 61.6dB
Distortion Source
Primarily gain variations with swing, as SR results
indicate amplifiers can track up to 13, 30 and 15MHz
respectively
Results support this as difference in IM3 between
amplifiers matches their gain differences at input
frequencies
max
sinin m in in
m
Vout SRSR f A f t f
t A
2 2
2
FC
RFC1
RFC2
Jose Silva-Martinez 50
Class AB-B Circuit
• Slew-Rate Boosting Employing an Auxiliary Class-B Amplifier C2
C1
vo
vi vx-
+
Pre-ampClass-B
Class
AB
CL
CP
-
+
Technique based onthe generation of highdynamic current ondemand.
The proposed concept relies:
Monitoring the amplifier’s input stage, employing a low-power single-stage ultra-fastpreamplifier,
Preamplifier output is used to drive a class-B amplifier (almost class-C) that generatesup to three times the current delivered by the main amplifier.
“Operational Transconductance Amplifier with Class B Slew-Rate Boosting for Fast High-
Performance Switched-Capacitor Circuits,” M. Naderi, et.al., IEEE TCAS-I, pp. 3769-3779,
November 2018.
Jose Silva-Martinez 51
Proposed Core Amplifier
Main Amplifier: Pseudo Class-AB Amplifier
Class AB Output stage to provide large loading current,
The minimum transconductance requirement can be satisfied by delivering enoughcurrent at the input stage; 1.5mA and additional (2nd stage) gain when resistive loaded,
Modest dc-current would be set as the output stage current in the order to provideadditional DC-gain available by this architecture; 0.5mA,
Large output swing
M1
M7
M9
M11
VDD
Vin+
Vout+
CMFBM13
M5
M3VB1
VB2
R1
VB3
CB
RB
M2
M8
M10
M12
Vin-
Vout-
CMFBM14
M6
M4
R2
VB3
CB
RBIB1IB3
IB2
IB3
IB2
CZRZCZ RZ
Jose Silva-Martinez 52
High speed resistive loaded Pre-Amp amplify error signal by around 15dB.
The resistive load is utilized in the Pre-Amp in the order to provide the less parasitic andhigher bandwidth.
The VBP and VBN voltages are properly set.
MP1, MP2, MN1, and MN2, can provide up to five times of the main amplifier current
The input capacitance of the pre-amp is around 15 fF; 65fF due to main amplifier.
M1
MP1
MN1
CB
Vin+
Vout+
R
VBN
CB
RB
IB
VBP
RB
M2
MP2
MN2
CB
Vin-
Vout-
R
VBN
CB
RB
VBP
RB
VDD
Slew-rate booster circuit operation with 16 mVhysteresis.
20% main amp power
Proposed Auxiliary Amplifier
Auxiliary Amplifier: Class-B Amplifier
Jose Silva-Martinez 53
Simulation Results
Pulsed output current components for a switched-capacitive integrator:
The class-B amplifier takes less 300 psecs to deliver/sink more than 1.7 mA andaround 700 psecs for 1% settling;
Main amplifier delivers around 0.7 mA and settles (1%) in around 1500 psecs.
Differential output current for thestandalone amplifier and amplifier withauxiliary amplifier enabled:
The peak current of enhanced architecturesurpasses the one of the conventional one.
The slew time: 400 psecs for the proposedamplifier vs. 1050 psecs required for theconventional architecture.
Jose Silva-Martinez 54
Measurement Results
Simplified (single-ended) version of theamplifier’s characterization setup
C1 = 16Cu
R/16
C2 = Cu
R
CL
On Chip
vo
Cin_buffer
vi
Buffer Pre-Amp
Class-BBuffer
Main
Amplifier
Chip Micrograph: TSMC 40nm Technology
A fully-differential test setup used to characterize the performance of the amplifiers inthe 4.5-bit/stage pipelined stage prototype.
C1 and C2 were set to 880 fF and 55 fF, respectively, to resemble the operation of acapacitive amplifier of 16 V/V.
The capacitor values were based on the maximum total allowed input referred noiselimit to satisfy the thermal noise requirement for the first 4.5-bit residue amplifier for a12-bit pipelined ADC.
Jose Silva-Martinez 55
Measurement Results
But the results are better. The buffer masks a bit the results.
Measurement results for a large inputstep voltage:
Conventional solution (Yellow)
Proposed Solution (Blue)
A 62.5 mVpp input step voltagewas applied to generate a 1Vppoutput step variation.
The proposed architecture shows a0.8 nsecs shorter slew time (45%smaller than the amplifier withoutSR boosting)
28% smaller setting time than theconventional solution
Step Response Test:
Jose Silva-Martinez 56
Measurement Results
Under similar conditions, theproposed architecture surpasses thelinearity of the conventional amplifierby more than 10 dB for large signals
The penalty is 20% more power.
Measured spectrums for a 500 MHz tone forthe standalone amplifier.
- 8.41 dB
- 53.66 dB
- 8.53 dB
- 64.26 dB
Measured spectrums: 500 MHz tonewith SR boosting SR technique enabled.
Jose Silva-Martinez 57
Measurement Results
ADC: Measured spectra with sinusoidal input at
24.95 MHz before and after gain calibrationMeasured DNL and INL after gain
calibration
Naderi et.al., TCAS-I, Sept 2019
A 27.7 fJ/conv-step at Nyquist 500 MS/s 12-Bit Pipelined ADC with Slew Boosted Amplifiers and Sub-ADC Forecasting
Jose Silva-Martinez 58
Conventional (Nyquist) ADC
A/D
Data
Out
Vin
SQNR=6.02*n+1.76
Jose Silva-Martinez 59
)s(H
)s(HSTF
1 )s(HNTF
1
1
DAC
Vin
ss
FT
1
H(s) A/D
Data
Out
Vin
Quantization
Noise
Feedback
DAC
H(s) A/DDout
VDAC
NTF =Dout
Qn
STF =Dout
Vin
ff0
0 dB
ff0
OBG
Fundamentals of Oversampled A/D Conversion
Control Theory: Feedback and properties
Jose Silva-Martinez 60
Power distribution
Q
4b
Z -1/2Z -1/2
DoutVin
Ab
1
Ab
2
Af2
Af1
ω2
sω3
sAf3
ω1
s
g1
Power dominated by analog blocks
*Data from CTΣ∆M that appear on: B. Murmann, "ADC Performance Survey 1997-2014," [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.
Carlos Briseno-Vidrios 60
Jose Silva-Martinez 61
High Gain Broadband Amplifiers
Two Stage ‘Typical’ configuration
maximizes gain of the initial stages => Better Q control
Output pole ~ 4*GBW
Overall noise limited by input devices
Rf reduces (degenerate) noise due to NMOS current mirrors
Limitations:
• Parasitic poles result in additional loop delay/excess phase in the
filter (could be > 10 deg at 500MHz)
•Limits loop stability and affects the overall performance
Pbias
VDD
VSS
Vinp
cmbias
M1 M2
M9 M8
M6
Vinm
M3 M4
Pbias
cmbias
Voutm
M7
M5
Voutm
Rf
Cc Rc Rc Cc
Rf
Jose Silva-Martinez 62
Jose Silva-Martinez 63
Final remarks
63
• modulators are a bit different
• Resistive terminated circuits: Cascade of amplification stages
• Unfortunately we do not have time cover this topic
• Questions?