future fab international volume 43

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FUTURE FAB International | Issue 43

Welcome …

It’s now been four years since the bottom fell outof the world’s economic base and we suffered theworst economic downturn since the Great Depression.It’s hard to believe it’s been that long, but in the com-plex world of semiconductors, that time has seen theprogression of two more technology cycles; Facebookpassing 1 billion users; the rise of the tablet alongsidethe proliferation of the smartphone; and a new techwar between global technology superpowers that aresuing each other as they encroach further and furtherinto each other’s sphere of influence.

Oddly enough, all of the aforementioned was driv-en by you – yes you, reading this right now. If you area regular reader of this journal, then you are engagedor affiliated with the semiconductor industry in someform, and we just wanted to take a moment to say,“Well done; keep it up.” It’s been our honor to helpyou in whatever manner that is: to be effective, tothink and do what you do. We know we’re a small partof the ecosystem – but we’re proud of that and hopeyou are too.

Enjoy!The Future Fab Team

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2 | FUTURE FAB International | Issue 43

CONTENTS | FUTURE FAB International | Issue 43

FUTURE VISIONS & CURRENT CONCERNS

12 IntroductionPushkar P. Apte – Pravishyati Inc.

13 Optimizing an IP Portfolio Overan R&D Life CycleKathleen De Belder, Sigrid Gilis, Vincent Ryckaert – imec

18 Thought Leadership ProfileTotal Facility Solutions

20 More Than Technical InnovationRequired for CMOS ExtensionDavid Hemker – Lam Research Corp.

DESIGN IMPLEMENTATION &PROCESS INTEGRATION

25 IntroductionSteven E. Schulz – Si2

26 Designing With FDSOI vs. BulkJean-Luc Pelloie – ARM

MANUFACTURING: FAB, SYSTEMS & SOFTWARE

31 IntroductionAlan Weber – Alan Weber & Associates

32 Integrating Virtual Metrologyin a Manufacturing SystemCristina De Luca,1 Andrea Schirru2 –1Infineon Technologies Austria2University of Pavia

38 MES Migration: An Absolute Needor a Utopia?Francisco Almada-Lobo, Jeff Peabody– Critical Manufacturing

LITHOGRAPHY LANDSCAPE

44 IntroductionJanice M. Golda – Intel

45 Thought Leadership ProfileNikon

46 Reducing Defects in EUV MaskBlanks to Enable High-VolumeManufacturingVibhu Jindal, Patrick Kearney, Arun John, Frank Goodwin – SEMATECH

Next generation lithography techniques continue to evolve, but IC makers need solutions

today that will keep them on their aggressive technology roadmaps. In order to maintain

production timelines, extension of ArF lithography is vital. To meet this challenge,

Nikon developed two new 193 nm scanners—the latest evolutions of the proven

Streamlign platform, which is already adopted in leading-edge facilities worldwide.

The Nikon NSR-S621D immersion and NSR-S320F dry scanners satisfy the increasingly

demanding requirements for imaging, overlay accuracy, and ultra-high productivity that

are essential for cost-effective 22 nm half-pitch applications and beyond.

Nikon. Evolution in Action. www.nikonprecision.com

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CONTENTS | FUTURE FAB International | Issue 43

FRONT END OF LINE

51 IntroductionJiang Yan – IMECAS

52 Section SponsorHitachi

54 Monitoring Fluid Suspensions:Current Results & Perspectives ofa Novel Method Based on LightScatteringM.A.C. Potenza,1 T. Sanvito,1 A. Pullia,1

D. Di Cola,2 D. Lavalle2 G. Fazio,3

A. Filippini,3 L. Caudo,3 G. Spinolo3 –1Physics Department, University ofMilan 2Technofittings S.r.l, Rome3Micron S.p.A., Italy

60 Yield Enhancement ThroughAirborne MolecularContamination ManagementArnaud Favre,1 Julien Bounouar,1

Emmanuelle Véran,1 Astrid Gettel,2

Marco Ackermann2 – 1adixen VacuumProducts by Pfeiffer Vacuum, Annecy,France 2GLOBALFOUNDRIES,Dresden, Germany

67 Point-of-Use Chemical ReuseMark Simpson and Allen Page – Texas Instruments

METROLOGY, INSPECTION & FAILURE ANALYSIS

73 IntroductionDavid G. Seiler – NIST

74 Calculating Kill Ratios on Multi-Component DevicesGarry Tuohy – GLOBALFOUNDRIES Inc.

WAFER FAB & PACKAGING INTEGRATION

79 IntroductionChristo Bojkov – TriQuintSemiconductor

80 An Optimal Cu-to-Cu Thermo-compression Bonding ProcessWindow Compatible With 3DWafer Stacking and StabilityH.Y. Li,1 L. Peng,1,2 F.X. Che,1 C.S. Tan,2

G.Q. Lo1 – 1Institute of Microelectronics,A*STAR (Agency for Science,Technology and Research), Singapore2Nanyang Technological University,Singapore

ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

86 IntroductionSurya Shivakumar Bhattacharya –A*STAR

87 Embedded System Access:Changing the Paradigm ofElectrical TestThomas Wenzel, Heiko Ehrenberg –GÖPEL electronic GmbH

95 Advertisers Index

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EDITORIAL PANEL

Paolo A. GarginiDirector of Technology Strategy for Intel Corporation

Dr. Paolo Gargini is also responsible for worldwide research activities conducted outside Intel forthe Technology and Manufacturing Group by consortia, institutes and universities. He received doctorates in electrical engineering and physics from the Universita di Bologna, Italy.

Surya BhattacharyaDirector, Industry Development; IME

Dr. Surya Bhattacharya is director, Industry Development, for IME’s Through Si Interposer (TSI) program. He has over 18 years of experience ranging from 0.8 micron to 28 nm CMOS while work-ing in the U.S. semiconductor industry at both fabless companies and integrated device manufac-turers. Surya obtained his Bachelor of Technology degree in electrical eng. from the Indian Instituteof Technology Madras, India in 1987, and his M.S. and Ph.D. in microelectronics from the Universityof Texas at Austin in 1993.

Biographies of Future Fab's Panel MembersFor the full versions of the following biographies, please click here.

Welcome to our new Panel Member – Surya Bhattacharya

Michel BrillouëtSenior Adviser, CEA-Leti

Michel Brillouët joined CEA-Leti in 1999, where he managed the silicon R&D. Prior to joining CEA-Leti, he worked for 23 years in the Centre National des Télécommunications (France Telecom R&DCenter), where he held different positions in micro-electronics research. He graduated from ÉcolePolytechnique.

Alain E. KaloyerosSenior Vice President, CEO and Professor, College of Nanoscale Science and Engineering; University at Albany

Alain E. Kaloyeros has authored/co-authored over 150 articles and contributed to eight books onnanoscience, holds 13 U.S. patents, and has won numerous academic awards. He received his Ph.D.in experimental condensed matter physics from the University of Illinois, Urbana-Champaign, in 1987.

Gilbert J. DeclerckExecutive Officer, imec; Member of the Board of Directors, imec International

Gilbert J. Declerck received his Ph.D. in electrical engineering from the University of Leuven in1972. He has authored/co-authored over 200 papers and conference contributions. In 1993, he waselected fellow of the IEEE. Since July 1, 2009, Dr. Declerck has been executive officer imec and amember of the board of directors of imec International.

Didier LouisCorporate and International Communication Manager, CEA-Leti

Louis joined CEA-Leti (France) in 1985, where he received a Ph.D. in metallurgy/electrochemistryfrom the University of Grenoble. He has written more than 30 papers related to etching and strip-ping processing and has co-authored more than 60 scientific papers and eight patents.


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EDITORIAL PANEL | FUTURE FAB International | Issue 43

Shishpal RawatChair, Accellera Systems InitiativeDirector, Business-Enabling Programs; Intel Corp.

Shishpal Rawat holds M.S. and Ph.D. degrees in computer science from Pennsylvania StateUniversity, University Park, and a B. Tech. degree in electrical engineering from the Indian Instituteof Technology, Kanpur, India.

Jon CandelariaDirector, Interconnect and Packaging Sciences; SRC

Jon Candelaria has over 34 years’ experience in the electronics industry in a wide variety of engi-neering and managerial roles. He received his BSEE and MSEE from the University of New Mexico.

Yannick Le TiecTechnical Expert, CEA-Leti, MINATEC Campus

Yannick Le Tiec joined CEA-Leti in 1995 and received his Ph.D. in materials science and engineeringfrom the Polytechnic Institute, Grenoble, France, and his M.S. in chemistry from the National Schoolof Chemistry, Montpellier, France. He is a CEA-Leti assignee at IBM, Albany (NY), developing theadvanced 22 nm CMOS node and the FDSOI technology.

Alain C. DieboldEmpire Innovation Professor of Nanoscale Science; Executive Director,Center for Nanoscale Metrology, CNSE, University at Albany

Alain’s research focuses on the impact of nanoscale dimensions on the physical properties ofmaterials. He also works in the area of nanoelectronics metrology. Alain is an AVS Fellow and asenior member of IEEE.

Thomas SondermanVice President, Manufacturing Systems Technology; GLOBALFOUNDRIES

Thomas Sonderman obtained a B.S. in chemical engineering from the Missouri University ofScience and Technology in 1986 and an M.S. in electrical engineering from National TechnologicalUniversity in 1991. He is the author of 43 patents and has published numerous articles in the area ofautomated control and manufacturing technology.

Rohan AkolkarSenior Process Engineer, Components Research; Intel Corporation

Dr. Akolkar received the Norman Hackerman Prize of the Electrochemical Society in 2004, andnumerous Intel Logic Technology Development awards. He has authored more than 40 technicalpapers, invited talks, and U.S. patents in the area of electrodeposition.

Christo BojkovSenior Package Development Engineer, TriQuint Semiconductor

Dr. Christo Bojkov has published over 30 publications and holds 15 patents. Since receiving hisdoctorate in chemical engineering, he has worked and taught in academia for over 10 years inphysical chemistry and surface science.

Steve GreathouseGlobal Process Owner for Microelectronics, Plexus Corp.; Idaho

Steve Greathouse has published many articles on technical topics related to semiconductor pack-aging, failure analysis and lead-free packaging. He has a B.S. in electronic physics from WeberState University with advanced studies in material science and computer science.

Daniel J.C. HerrProfessor & Nanoscience Department Chair, JSNN; UNC – Greensboro

Dr. Herr is a pioneer in collaborative nanotechnology research. He is professor and chair of theNanoscience Department at the new Joint School for Nanoscience and Nanoengineering inGreensboro, North Carolina. Until recently, Dr. Herr served as the director of SemiconductorResearch Corporation’s Nanomanufacturing Sciences area. He received his B.A. with honors inchemistry from Wesleyan University in 1976 and his Ph.D. from the University of California at SantaCruz in 1984.

William T. ChenSenior Technical Advisor, ASE (U.S.) Inc.

Bill Chen is the co-chair of the ITRS Assembly and Packaging International Technical WorkingGroup. He was elected a Fellow of IEEE and a Fellow of ASME. He received his B.Sc. at Universityof London, MSc at Brown University and Ph.D. at Cornell University.

Liam MaddenCorporate VP, FPGA Development & Silicon Technology; Xilinx, Inc.

Liam Madden is responsible for foundry technology, computer aided design and advanced pack-age design. He earned a BE from the University College Dublin and an MEng from CornellUniversity. Madden holds five patents in the area of technology and circuit design.

Alan WeberPresident, Alan Weber & Associates

Alan’s consulting company specializes in semiconductor advanced process control, e-diagnosticsand other related manufacturing systems technologies. He has a bachelor’s and a master’s degreein electrical engineering from Rice University.

David G. SeilerChief, Semiconductor and Dimensional Metrology Division, NIST

David G. Seiler received his Ph.D. and M.S. degrees in physics from Purdue University and his B.S. in physics from Case Western University.

Mark McClearGlobal Director, Applications Engineering, Cree LED Components

Mark McClear is responsible for LED lighting applications development and Cree’s ApplicationEngineering Technology centers worldwide. He holds a B.S. in electrical engineering from MichiganState University and an MBA from Babson College, and has 11 issued and published U.S. patents inelectronics, LED and solid state lighting.




Giuseppe FazioAdvanced Process & Equipment Control Sr. Engineer; Micron Semiconductors Italy

With a laurea degree in applied physics from Milan University, Giuseppe has working experience inseveral sectors, from research to industry, and vast experience in industrial and scientific instru-mentation. He has authored/co-authored many articles, is an avid contributor at conferences andholds several patents in the semiconductor field.

Peter RabkinDirector of Device & Process Technology, SanDisk Corp.

Dr. Peter Rabkin focuses on development of novel 3D memory technologies and products. Heholds a master’s degree in physics from Tartu University and a Ph.D. in physics of semiconductorsfrom the St. Petersburg Institute of Physics and Technology.

Sitaram R. ArkalgudDirector of Interconnect, SEMATECH

Sitaram R. Arkalgud has over 20 years of R&D and manufacturing experience within the chip indus-try. He has a Ph.D. and a master’s degree in materials engineering from Rensselaer PolytechnicInstitute, and a B.S. in metallurgical engineering from Karnataka Regional Engineering College,Surathkal, India.

Daniel C. EdelsteinIBM Fellow; Manager, BEOL Technology Strategy, IBM T.J. Watson Research Center

Dr. Edelstein played a leadership role in IBM’s industry-first “Cu Chip” technology in 1997, in theintroduction to manufacturing of Cu/Low-k insulation in 2004. He received his B.S., M.S., and Ph.D.degrees in applied physics from Cornell University.

Christian BoitHead, Semiconductor Devices at Berlin University of Technology, Germany

The Berlin University of Technology is an institution for research and development in the areas ofdevice simulation, technology, characterization and reliability. Christian Boit received a diploma inphysics and a Ph.D. in electrical engineering on power devices, then joined Siemens AG’s ResearchLaboratories for Semiconductor Electronics in Munich and has been a pioneer on photoemission.

Pushkar P. AptePresident, Pravishyati Inc.

Dr. Pushkar P. Apte's strategy consulting firm focuses on the high-tech industry. He received hismaster’s and Ph.D. from Stanford University in materials science and electrical engineering, and hisbachelor’s degree in ceramic engineering from the Institute of Technology, Varanasi, India.

Jiang YanProfessor, IMECAS

Dr. Jiang Yan has authored and co-authored over 40 papers, holds 17 U.S. patents and 10 Chinapatents. He received his Ph.D. in electrical engineering from the University of Texas at Austin in 1999.

Klaus-Dieter RinnenDirector/Chief Analyst, Dataquest

Klaus-Dieter Rinnen is director for Dataquest’s semiconductor and electronics manufacturinggroup. He received a diploma degree in physics with minors in physical chemistry and mechanicalengineering in Germany, and a Ph.D. in applied physics from Stanford University.

John SchmitzSVP & General Manager, Intellectual Property and Licensing; NXP

John Schmitz holds a master's degree in chemistry from Radboud University of Nijmegen,Netherlands, and a doctorate in physical chemistry from Radboud University Nijmegen. He hasauthored more than 45 papers in various scientific journals and has written books on IC technolo-gy and on thermodynamics.

Lode Lauwers Director Strategic Program Partnerships for Silicon Process & Device Technology, imec

Lode Lauwers has an M.S. in electronics engineering and a Ph.D. in applied sciences. He joinedimec in 1985 as a researcher. Lode manages imec’s core partner research program on sub-32nmCMOS technologies.

Janice M. GoldaDirector, Lithography Capital Equipment Development; Intel Corp.

Janice Golda manages an organization responsible for creating strategies and working with Intel’slithography, mask and metrology suppliers and subsuppliers to deliver equipment meeting Intel’sroadmap technology, capacity and cost requirements. She is a member of the Berkeley CXROAdvisory committee, is Chairman of the Board for the EUV LLC and holds one U.S. patent.

Luigi ColomboTI Fellow

Dr. Luigi Colombo is a TI Fellow working on the Nanoelectronic Research Initiative (NRI). He is author and co-author of over 130 publications, three book chapters, and holds over 60 U.S.patents. Dr. Colombo received his Ph.D. in materials science from the University of Rochester.

Warren SavageChief Executive Officer, IPextreme

Warren Savage has spent his entire career in Silicon Valley, working with leading companies, wherehe focused on building a global scalable semiconductor IP business. In 2004, he founded, and stillleads IPextreme in the mission of unlocking and monetizing captive intellectual property held withinsemiconductor companies and making it available to customers all over the world. He holds a B.S. incomputer engineering from Santa Clara University and an MBA from Pepperdine University.

Yayi WeiPrincipal Member of Technical Staff; GLOBALFOUNDRIES

Dr. Wei investigates advanced lithography processes and materials. He has over 16 years of lithog-raphy experience, including DUV, 193 nm, 157 nm, 193 nm immersion, EUV and E-beam lithography.Dr. Wei has numerous publications and holds several patents in the field of lithography.


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Peter RammHead of Device and 3D IntegrationDepartment, Fraunhofer EMFT; Munich

Peter Ramm received his physics and Dr. rer. nat.degrees from the University of Regensburg. He hasauthored or co-authored over 100 publications, includ-ing three book chapters and 23 patents.

Davide Lodi Baseline Defectivity & MetrologyEngineering Manager; MicronSemiconductors Italy

After graduating in physics from the University ofMilan, Davide Lodi started working in 1997 forSTMicroelec-tronics as a process engineer. Afterbecoming the manager of Wet Processes andMetrology Engineer-ing at the NVM R&D Agrate site,he moved to Numonyx, which was acquired byMicron in 2010.

Stephen J. Buffat Staff Research Scientist, Lockheed Martin NanoSystems

Stephen Buffat is responsible for the startup andoperation of Lockheed Martin’s nanotechnology facili-ty and operation in Springfield, Mo. He has authoredor co-authored numerous articles on photolithogra-phy, etch and 300 mm surface preparation processtechnologies.

Ehrenfried Zschech Division Director for Nanoanalysis &Testing, Fraunhofer Institute forNondestructive Testing; Dresden,Germany

Ehrenfried Zschech received his diploma degree insolid-state physics and his Dr. rer. nat. degree fromDresden University of Technology. He has publishedthree books and over 100 papers in scientific jour-nals on solid-state physics and materials science.

Steven E. SchulzPresident and CEO, Silicon Integration Initiative, Inc.

Since 2002, Steve Schulz has served as presidentand CEO of Si2, the leading worldwide consortiumof semiconductor and software companies charteredto develop EDA standards. He has a B.S. in electricalengineering from the University of Maryland atCollege Park, and an MBA from the University ofTexas at Dallas.


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FUTURE VISIONS & CURRENT CONCERNSClick here to return to Table of Contents

13www.future-fab.com |12 | FUTURE FAB International | Issue 43

The semiconductor industry has beenan amazing source of industrial innova-tion in recent history. Starting with thediscovery of the transistor in Bell Labs in the 1940s, progressing through thedevelopment of the integrated circuit inthe 1960s, the semiconductor industryhas grown and flowered into a $300 billion juggernaut. In the process, it hasdriven incredible innovations that makethe mind boggle – such as cramming abillion or more electronic transistors on athumbnail, decoding the human genomeand enabling people to communicate verbally, in pictures, and in video almostanytime, anywhere. For the first fewdecades, the industry relied primarily ongeometric scaling – making stuff smaller.The new millennium brought a millennialshift, requiring many more innovationssuch as the shift to high-k dielectricmaterials and the move from aluminum tocopper for on-chip interconnects. But thisis just the beginning – future innovationsin materials and device structures will beeven more exotic, involving fundamentalshifts like using photons to exchangeinformation instead of electrons, and perhaps new substrates like graphene,instead of the old warhorse silicon.

Pushkar P. AptePresident, Pravishyati Inc.

While no one knows the exact natureand speed of these advances, it is abun-dantly clear that they won’t be cheap.The semiconductor industry spends moreon R&D than almost any other industry,and the spend is increasing rapidly, out-pacing revenue growth. This is simply not sustainable – as the memorable linegoes, “It’s economics, stupid.” Sustainingthis blistering pace of innovation willrequire new models of pre-competitivecollaboration across the entire supplychain in industry, and with academia,research institutes and the government.New innovation platforms and processesmust develop – they may entail anunprecedented level of trust, informa-tion exchange and “co-opetition.”

The two papers in this sectiondescribe different elements of this chal-lenge – the first describes the globalresearch institute imec’s perspective ondeveloping a rational intellectual proper-ty environment that rewards fairly butdoes not stifle the needed flow of ideas;while the second, from Lam Research,describes the breadth of innovationsneeded and exciting research programsunder way at leading research universi-ties like UC Berkeley, Stanford and MIT.

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As an independent research institute,imec performs world-leading research in nanoelectronics and nanotechnology,thereby creating new technologies andinventions all over the R&D life cycle. TheR&D work covers both fundamental as wellas late stage research, generating a diversepatent portfolio. Imec’s intellectual proper-ty (IP) business model tries to leverageand increase the value of these IP assets.

Introduction to imec and Its R&D Life Cycle

Imec was founded in 1984 as a non-profit organization with the goal ofstrengthening the microelectronics industryin Flanders. The decision of the Flemishgovernment to set up an R&D institute inthe field of nanoelectronics was inspired bythe strategic importance of microelectron-ics for the industry and by the major invest-ments required to keep up with develop-ments in this field. Nowadays, imec per-forms world-leading research in nanoelec-tronics. It leverages its scientific knowledgewith the innovative power of its globalpartnerships in ICT, health care and energy.Imec delivers industry-relevant technologysolutions. In a unique high-tech environ-ment, its international top talent is commit-ted to providing the building blocks for abetter life in a sustainable society.

As an R&D center, imec creates manynew technologies and inventions all overits R&D life cycle. The R&D work andefforts cover both early-stage research(fundamental research) as well as develop-ing designs on demands or even perform-ing low-volume manufacturing.

Figure 1 shows a global R&D platform.Early-stage technologies are typicallydeveloped in or with academia. Theseinstitutes are located on the high left ofthis platform where R&D costs are low andwhere most of the time, funding comesfrom the governmental. There is more timefor doing research, and many options areleft open. On the other hand, industrialplayers are located on the lower right side,where, typically, R&D costs are much high-er. Next to this, there is only a short timeperiod for doing development, due to thefact that the product has to enter the mar-ket within a fixed time frame.

Imec is situated in between the afore-mentioned areas, a position sometimescalled “the valley of death.” At this stage,governmental funding is exhausted, andthe industry is still reluctant to investmoney in too-immature technology.Therefore, imec has created a tunnel tobridge this gap by creating an R&D plat-form. This platform offers the opportunityto cooperate with industrial partners, but

Optimizing an IP PortfolioOver an R&D Life CycleKathleen De Belder, Sigrid Gilis, Vincent Ryckaert Imec

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to simultaneously continue the researchactivities of academia to prepare the tech-nology for an industrial framework.

In this position, imec has the opportu-nity and potential to build up an IP port-folio across all the different phases of itsR&D life cycle, covering several different IPstacks. This has resulted in a patent port-folio of about 1,025 families (translatedinto 2,850 patents and patent applicationsin Europe, the U.S., Japan, etc.). Almosthalf of the intellectual property rights (IPR)in this portfolio are co-owned by an indus-trial or academic partner. The IP stack cov-ers materials, equipment, process steps,process results, devices, circuitry, systemsand software.

Similar to its R&D activities, imec triesto gain value out of the IP portfolio inevery stage of the R&D life cycle.

Imec’s Business ModelBefore going into detail in the moneti-

zation process, imec’s business modelneeds some introduction.

Imec’s business model is an open, col-laborative model primarily based on non-exclusive licenses. The key features of thebusiness model are: 1) avoiding IP blockingfor our partners; 2) securing IP rights forour partners; and 3) enabling publications.The tools to facilitate this model consist ofa selective patenting model and a carefullydesigned IP model. In every stage of theR&D life cycle, an open multi-partnermodel is promoted wherein the costs and IP are shared among the partners.

Figure 2 lists the R&D life cycle, goingfrom funded research (early stage), toapplied research projects, bilateral agree-ments toward development on demand,

Figure 1. Representation of R&D Life Cycle: Time Frame for Doing Research vs. the R&D Cost

Optimizing an IP Portfolio Over an R&D Life Cycle FUTURE VISIONS & CURRENT CONCERNS

low-volume manufacturing, IP licensing andeven selling IP. Arrows A and B illustratethe possible routes for handling the IP.

When early-stage IP has been created,typically, two routes are to be consideredin the handling of IP. Route A is selected touse early-stage IP as background for (fol-low-up) projects, in bilateral collaborations(where new IP can be generated based onthis background) and later on as back-ground (with or without IP created halfwayin the life cycle) in late life-cycle activities.Typically, imec grants non-exclusive useand exploitation rights to make, sell andoffer to sell semiconductor products. Inother words, a technology transfer is car-ried out via the residents of the partnerswho are collaborating jointly in the

research programs. There is the possibilitycreating joint IP that will be on a without-accounting basis (i.e., IP can be used byeach contributing party without financialaccounting to another involved party orwithout asking consent).

The benefits of this model are twofold:The cost of R&D is being shared (costs forinfrastructure, people, experience); and theavailable funding mechanism can be usedfor long- or midterm research (not stop-ping after academic R&D, no end in the val-ley of death). Furthermore, there is a wellbuilt-up IP portfolio when a product entersthe market. There might be some argu-ments against this ecosystem, being: theneed to have an agreement on the prose-cution of IP; some loss of value due to the

Figure 2. Possible Routes for Handling of IP Over the R&D Life Cycle



non-exclusivity of the system; and/or norights to sue via a licensing system.

Imec manages its IP via one-to-onecontracts (it is not a joint venture). The useof co-ownership without accounting avoidsco-management. By following this path,the IP is fully exploited.

In some cases, it might be preferable to reserve the early-stage IP in order to beable to license or transfer it on an exclusivebasis later. This is illustrated by route B inFigure 2.

Selecting this path also has its conse-quences; namely, a) financial means andcritical mass are low; b) the entry into themarket of the technology is risky; c) IP hasto be reserved; d) the upturn for exclusivepost-research exploitation is higher; and e) mutual expectations are to be matchedby avoiding sitting on IP, by evaluating thesituation frequently and by being preparedto switch to route A.

Academia should not only look fordirect valorization of its IPR (via transfersor exclusive licenses), but should considersetting up a business framework whereinIP that is being created or acquired maybe supported by licenses from other aca-demia. This model of participation and collaboration between academia and/orother interested parties might be a way tounlock value for early life-cycle IP.

In both cases or routes, selling the IP to the secondary market should be the lastoption/resort for valorizing IP. However,before doing this, some aspects must betaken into consideration:• Can the ecosystem be secured? Which

parties can be approached? What arethe possible risks or liabilities?

• Regarding business policy: Is thisapproach fair toward current partners?Can a submarine approach be avoided?Should the IP be offered to partners first?

Creating and OptimizingAdditional IP Value ThroughoutMonetization

Besides taking one of the above-men-tioned routes, why not jump on the train ofIP monetization? As current success storiesshow, monetization of IP is a booming andupcoming market. It involves the transac-tion of a (granted) patent or patent family,without know-how, especially to non-prac-ticing entities, hence for use of the IP rightembedded in the patent as such. This ris-ing trend of gaining additional revenuesand more value out of IP through moneti-zation is due to the failure of the early-stage IP market. In Europe, this markethardly exists. Besides that, this market failure is also caused by the lack of trustbetween the different R&D players andacademia and/or by a mismatch of theirbusiness models.

The first experiment with IP moneti-zation for imec was with an older patentfamily. A first choice was made by work-ing with a defensive patent aggregator.This is a party that tries to keep thepatents out of the hands of non-practic-ing entities (NPEs) that would assertthem against companies that are likely to infringe these patents. Instead of fos-tering patent litigation, defensive patentaggregators operate as clearinghousesand try to set up a licensing deal withthird companies.

Imec learned the following from this IPmonetization experiment. Firstly, an effi-cient internal preparation is needed and aselection needs to be made of patent fami-lies that are without or have only minorencumbrances, e.g., having all assignmentsin place in case of co-owned patents.

A second important issue is to find outhow one can evidence product infringe-ment.

Optimizing an IP Portfolio Over an R&D Life Cycle FUTURE VISIONS & CURRENT CONCERNS

Thirdly, one needs to value the patent.This is a difficult exercise for early-stage IP,because there is no existing market yet.However, looking at the following para-meters might help: • Does the patent include know-how?• Does the patent exist independently

of the know-how? • Is there a market yet? • What is the stage/status of the patent?

Of the know-how?• Is the patent part of a patent cluster? • What is the scope of the patent and is

it technology independent?• Is the patent linked to a standard? • Is the patent blocking other technologies? • Should one simply go for a cost-based

approach (plus overhead)?• Is there a time-to-market advantage?

Furthermore, prepare an offeringaccording to your own business or salesmodel. The buyer will also perform a duediligence of the offered patent, so expect alot of questions. Finally, there is the closingof the deal. All documents need to be inplace (patent purchase agreement, assign-ments, documents, translations, etc.).

Currently, the imec IP model is moredynamic than ever before:1. imec is recognizing and starting to use

the IP market evolutions.2. imec believes it is time to discuss IP

in- and out-licensing with other EUresearch institutes.a. To overcome failure of early-stage IP

marketb. To overcome adverse effects of IP

monetizationc. To create true EU collaboration

3. imec is willing to bring its experiencewith academia to the table to achieveconcrete solutions.

About the Authors

Kathleen De Belder After some years of research at the Vrije

Universiteit Brussel, Kathleen De Belderjoined imec’s patent group in October 2006as a patent portfolio officer. She has fol-lowed several courses in European patentlaw, due diligence and licensing technology.In 2011, Kathleen moved to the IP Businessgroup. Her work is directed toward giving IPadvice in business concepts and contracts,and developing IP models.

Sigrid Gilis After having obtained her master’s

degree in law at the Catholic University of Leuven (KUL), Sigrid Gilis became a registered member at the bar of Hasselt inSeptember 2009. She specializes in IP, TMTand ICT law, but is also active in the sectorof commercial and economic law and con-tract law. In June 2012, she completed acomplementary post-graduate study in ICT,IP and media law at the KUL, organized by the ICRI. Currently, Sigrid is doing aninternship with imec’s IP Business group as an independent legal consultant.

Vincent Ryckaert Vincent Ryckaert is a qualified Euro-

pean patent attorney, receiving furtherqualification on litigation of Europeanpatents. He has also undergone training inU.S. patent, licensing law and patent opin-ions and has an in-depth expertise in thefield of software-enabled patents. Vincentleads imec’s IP Business team. His effortsare directed toward IP business and intel-ligence work. �


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Future Visions & Current Concerns


Thought Leadership Profile

450 mm is slowly but surely movingaway from the “maybe” column toward the “inevitable” due to the largest four chip manufacturers building a roadmapthrough the much-publicized Global 450Consortium (G450C) and other announce-ments such as the imec 450 clean room inBelgium. All are aiming to assist the rolloutof what could be the final wafer transitionbefore CMOS architecture finally runs outof ways to cheat physics and the industrymust find new platforms to continue thenever-ending consumer thirst for techno-logy-related products.

Many of the throughput issues that chal-lenged 300 mm high-volume fabs will beexacerbated by the switch to the 450 mmwafer size; however, there is a plus side tosuch disruption. Many ideas that had beenproposed as solutions in 300 mm havebeen rejected or remain in limbo due tonumerous factors including risk, lack ofsupport, and pushback from a conserva-

tive-leaning industry. 450 mm has theopportunity to breathe new life into num-erous conceptual technologies due to itsnear-complete clean-sheet, and thereforehave a far greater chance for adoption than they did in the 300 mm space. This is mainly due to issues such as economicscale and complexity, which will force fabdesigners, OEMs and process integrators to investigate all open avenues in thesearch for solutions to the huge challenges450 mm entails.

Many ideas from the last five years –such as platform standardization, where-by traditional single-vendor cluster tools(Figure 1) evolve into standardized/modu-lar multi-purpose cluster tools (Figure 2) –offer solutions to the complexities involvedwith scaling up the wafer size and toolfootprint while maintaining throughput andefficiency. This approach morphs a processline into a single tool or a few tools capableof an entire single layer. Instead of process

lines, the process steps become layer clusters featuring multi-process tools withnumerous chambers able to completeentire levels of the device.

This is no easy switch. The transitionfaces numerous challenges due to thenature of the business: Competing vendorswill no longer be working with solely themanufacturer, but with each other to settleon a standard platform – an approachmany consider unworkable. There are sim-ilar examples common in fabs already; thelitho cell is just one example. Obviously,there are differences. The litho cell general-ly doesn’t have competing vendors inte-grated onto a common platform, but theconcept is sound, even if the political andinfrastructure challenges faced will not beeasy.

Total Facility Solutions’ vision is to bethe preferred, single-source providerof process-critical infrastructure forcustomers in the semiconductor, lifescience, photovoltaic and data centerindustries.

Joe CestariPresident

Mike Anderson Executive Vice President/Chief Operating Officer

Chris Walton Vice President, East Region

Robert Hill Vice President, West Region

Joe MinerVice President, Electrical

Total Facility Solutions 1001 Klein Road Suite 400Plano, Texas 75074Phone [email protected]

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20/20VISIONSFUTURE VISIONS & CURRENT CONCERNS20/20VISIONS


Complementary metal oxide semicon-ductor (CMOS) process technology hasbeen the standard in the semiconductormanufacturing industry for more than 40years. CMOS has advanced at a rapid paceguided by Moore’s Law. Approximatelyevery two years, circuit line widths aredriven smaller, device performance isimproved and cost is reduced, puttingmore processing power into a handheldsmartphone than all of the Apollo spacemissions combined.

But some are predicting that CMOS will soon reach the proverbial “brick wall”of the laws of physics, where conventionalscaling becomes impossible (or at leastimpractical). If this does happen, theresults will not only be felt in the fab, but will also negatively impact globaleconomies that are influenced by demandfor the latest and greatest technologies.

So what can be done?First, consider that the end of CMOS

has been predicted many times over the

past two decades. People used to thinkthat optical lithography was going to bethe end of CMOS scaling – that you couldn’tproduce patterns smaller than the wave-length of the source illumination. Addi-tionally, there were skeptics who didn’tbelieve it was possible to reliably use deepUV sources in production, let alone 193 nmimmersion lithography, double patterning,quadruple patterning or even EUV litho-graphy. But innovation has proven themwrong. Indeed, the industry has continuedto invent technology “extenders” that havekept CMOS alive and well.

When device speed improvements couldno longer be achieved with traditionalmethods, the industry invented materialswith higher dielectric constants to continuegate oxide scaling, metal gates to reduceresistance, and hybrid materials like SiGeand strain engineering to enhance mobility.To achieve voltage scaling, reduced volt-age operation and lower leakage in logicdevices, we now have 3D FinFET structures

More Than TechnicalInnovation Required for CMOS Extension

replacing planar structures. In memorydevices, planar NAND is being replaced by3D NAND to improve device densities, andDRAMs are migrating to buried bit linesand buried word lines. To emphasize theamount of change that is taking place inthe industry, consider this point: Before2000, there were 19 periodic table ele-ments being used in semiconductor man-ufacturing. Today more than 60 materialsare either in use or under evaluation.

Based on our customers’ roadmaps, virtually all semiconductor manufactur-ing will still use CMOS at the end of thisdecade. But this does not mean that CMOSwill be around forever. Despite the indus-try’s inventiveness, there are things that

could ultimately spell the end of the roadfor CMOS. The first of these is the tran-sistor itself. Preventing transistor leakage on ever-smaller devices is a significantchallenge that will need to be addressed.Failing to do so will result in larger end-products or shorter battery life. Anotherpossible disruptor to CMOS is the cop-per interconnect. Shrinking interconnectsincreases the electrical resistance in cop-per wiring, which in turn reduces perform-ance. The industry is looking at alternativemetals, new deposition processes, andgraphene and carbon nanotubes as pos-sible solutions to this issue. Perhaps themost likely factor to drive CMOS to an endis cost. Even if technology challenges areovercome, the process may be too expen-sive for scaling to remain economicallyfeasible.

So, what might a successor to today’sCMOS technology look like? Academia and

David Hemker Lam Research Corp.

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Figure 1. Nanoelectronics tunnels electric currentthrough a barrier.[1]

Figure 2. Nanomechanics replaces transistors with tiny switches.[1]




industry around the world are exploringseveral options. The first is nanoelectronics(Figure 1). This approach proposes replac-ing transistors with a new switching mech-anism that tunnels electric current througha barrier. It would significantly reducedevice power consumption, but faces sig-nificant challenges around band-edgesharpness and alignment.

The second approach is nanomechanics(Figure 2). This replaces transistors withtiny switches that open and close mechan-ically and have no “off-state” current. Thisis great for power consumption, but it alsohas significant challenges related to relia-bility, manufacturability and device design.

A third approach is nanophotonics(Figure 3) – a process that uses light,rather than electrons, to function. Thegood news about nanophotonics is that ituses very little energy and has significant

room for growth before reaching its theo-retical limits. Challenges to this methodinclude processing hybrid materials (III-V)that require highly toxic raw materials, aswell as processing silicon and III-V materi-als on the same substrate.

The fourth approach is nanomagnetics(Figure 4). This energy-efficient methodleverages the natural spinning movementof electrons, rather than their charge, to store and process data. IBM recentlydemonstrated that it is possible to controland manipulate the spin of electrons usingnanomagnetics (e.g., spintronics). Keychallenges to this approach include pro-cessing mostly nonvolatile novel com-pounds, reliability and compatibility withsilicon wafer fab processes.

While significant innovation is requiredto overcome the challenges with each ofthese technologies, the good news is that

academia and industry are already workingtogether well in advance of when they maybe commercialized. The Center for EnergyEfficient Electronics Science (E3S) at theUniversity of California at Berkeley is anexample of a public-private consortiumthat is focused on evaluating each of theseapproaches. The group, funded by theNational Science Foundation, is collaborat-ing with other academic institutionsincluding the Massachusetts Institute ofTechnology, Stanford University and oth-ers, as well as corporations, including LamResearch.

While it is not clear which technology, if any of these, will win out, five of theworld’s leading semiconductor industryassociations have jointly outlined eight criteria they consider essential to a CMOSsuccessor. Published in the “InternationalTechnology Roadmap for Semiconductors”(ITRS) in 2009, these criteria include scal-ability, incremental performance improve-ments, energy efficiency, an OFF/ON ratiofor memory devices to minimize powerdissipation, gain (for logic devices), oper-ational reliability, room-temperature oper-ation with tolerance for higher internal-device temperatures, and, perhaps mostimportantly, both technological and archi-tectural compatibility with CMOS.[2]

Between now and the end of CMOS –whenever that is – we can expect that theindustry will continue on its rapid pace of innovation. By the end of this decade,chipmakers will be manufacturing at leastsome capacity in volume on 450 mmwafers. The leading-edge manufacturing

node will be 7 nm, and 10 nm will be in full production. Extreme ultraviolet (EUV)lithography will be in play, and double- and quad-patterning of EUV-treatedwafers will follow. New processes will beexplored, including directed self-assembly,which uses phase separation of polymersto create patterned wafers as a potentialalternative to lithography, or more likely to augment optical lithography.

Wafer fabrication equipment will con-tinue to evolve and become even moresophisticated in 2020, with more sensorsand “intelligence.” Some tools may even be self-diagnosing and able to restocktheir own consumables. New approachesto deposit and remove many of the newmaterials may be required, and even newways of building structures may emerge.

No matter how we get there, one thingis certain: The extension of CMOS is get-ting harder and more expensive. Innovation– not just in technology, but in how wepartner and collaborate – is essential toovercome the financial burden of develop-ing next-generation technologies. Earlycollaboration with semiconductor manu-facturers, fabless companies, peers, suppli-ers, research consortia and universities isessential not only to reducing risk but alsoto efficiently achieving the level of techni-cal innovation that is required in the future.Lam Research is actively pursuing newinnovation models to help our customersextend CMOS for as long as possible, andwe are investigating the successors toCMOS so these technologies are readywhen our customers need them.

20/20VISIONS 20/20VISIONSFUTURE VISIONS & CURRENT CONCERNS

Figure 3. Nanophotonics uses light rather thanelectrons to power devices.[1]

Figure 4. Nanomagnetics uses the natural spinningmovement of electrons to store and processdata.[1]


DESIGN IMPLEMENTATION & PROCESS INTEGRATIONClick here to return to Table of Contents

It seems that nearly the entire semi-conductor landscape is becoming limitedby power and energy management, wherethis topic has overtaken timing perform-ance to satisfy battery life, thermal con-straints, reliability or global "green"resource management.

At one time, a majority focus was placedon the main culprit, dynamic (sometimescalled switching) power. However, at smallerprocess nodes, leakage competes withdynamic power and can even dominatetotal power consumption. While every new process node brought with it relativeincreases in leakage, it could be ignored asa small portion of total power consumption,so emphasis was placed on design tech-niques to provide large dynamic power sav-ings. Now, however, leakage has emerged as a serious limiter to continued semicon-ductor device integration.

In the following paper from ARM FellowJean-Luc Pelloie, the author makes the mod-ern-day case for fully depleted SOI (FDSOI)devices. Mr. Pelloie takes a designer's per-spective, assessing the "pros and cons" of

Steven E. SchulzPresident and CEO; Silicon Integration Initiative, Inc.

FDSOI along with bulk CMOS and otheralternatives such as FinFETs. The authormakes several excellent points regarding thedependence upon supporting design flowinfrastructure necessary to take advantageof FinFETs and FDSOI. As appealing as anew transistor device may seem as a solu-tion to the leakage problem, it becomesclear that it may require much more workand cost in infrastructure changes before it can be effectively inserted and used innew designs.

Novice designers who see their role primarily in terms of “programming andverifying” RTL code to deliver digital functionality into silicon might be initiallytempted to consider the details of FDSOIand FinFET outside their immediate scope.That would be a huge mistake. The abilityto design in the future will increasinglydepend upon optimizing all aspects of an interconnected technology chain (and supply chain). For almost every category of IC in the years ahead, managing power – specifically leakage power – will be a critical success factor.

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Endnotes1. K. Ganapathi et al. “Center for Energy

Efficient Electronics Science” website,University of California at Berkeley,http://www.e3s-center.org/research/index.htm#theme1-sec, Aug. 2012.

2. “Emerging Research Devices,”International Technology Roadmap forSemiconductors, http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_ERD.pdf, 2009.

References• Kartik Ganapathi et al. “Recent

Simulation Results on TFET Structures:Transport, Limitations on ON Current,Ballistic Leakage, and StructuralOptimization,” Talk or presentation,Center for Energy Efficient ElectronicsScience, Jan. 27, 2011.

• Youngki Yoon et al. “Scaling Study ofGraphene Transistors,” 2011 11th IEEEInternational Conference on Nanotech-nology, August 2011.

• Giovanni De Micheli, “Are We Reachingthe End of CMOS Scaling Limits?” EE Times, May 22, 2000.

• Matt Grimshaw, “Chip Watch: The Endof CMOS and Its Effect on the World,”Silicon Valley Watcher, Aug. 28, 2009.

• “IBM Scientists Waltz Closer to UsingSpintronics in Computing,” IBMResearch and the Solid State PhysicsLaboratory at ETH Zurich, http://www-03.ibm.com/press/us/en/pressre-lease/38566.wss, Aug. 12, 2012.

• Tsu-Jae King Liu et al. “The RelayReborn,” IEEE Spectrum, April 2012.

• A. Barman et al. “Size DependentDamping in Picosecond Dynamics ofSingle Nanomagnets,” Applied PhysicsLetters, vol. 90, Issue 20, May 17, 2007.

About the Author

David Hemker Dr. David Hemker is chief technology

officer at Lam Research Corp., in Fremont,Calif., where he focuses on corporate technology development. He joined LamResearch in 1998 and was named CTO in2012. Previously, Dr. Hemker served as vicepresident of New Product Development.Prior to joining Lam, he was vice presidentof technology for PMT/Trikon, where hewas responsible for research and devel-opment, technology and engineering. Dr. Hemker also spent five years in varioustechnology roles at Applied Materials. He received his doctorate and master’sdegrees in chemical engineering fromStanford University, and his bachelor’sdegree in chemical engineering from theUniversity of Wisconsin. Dr. Hemker holdsover 35 patents and has authored numer-ous technical publications in the areas ofsemiconductor processing and thin filmapplications. �


20/20VISIONS 20/20VISIONSFUTURE VISIONS & CURRENT CONCERNS





DESIGN IMPLEMENTATION & PROCESS INTEGRATION DESIGN IMPLEMENTATION & PROCESS INTEGRATION

With gate length scaling down to followMoore’s Law, it is more and more difficultto achieve a good leakage current compat-ible with low-power applications require-ments. This is due to the loss of control ofthe vertical electric field through the chan-nel of the MOS transistor, which triggersthe short channel effects. Until now, in bulk CMOS, the control was maintained byshrinking the gate insulator thickness (gateoxide has now been replaced by high-kinsulator) and increasing the doping in thechannel region close to the source drainjunctions (halo or pocket implants). Thismethodology is reaching its limits, asincreasing the channel doping results in an increase of junction leakage and gate-induced drain leakage (GIDL) currents.

Fully depleted SOI (FDSOI) transistor isnot a new device, as it started to be usedmore than 20 years ago. At that time, itwas considered to be the ideal MOS tran-sistor, being able to switch with a 60mV/decade subthreshold swing at roomtemperature. FDSOI has not been popularon the manufacturing side in the past, andwas mainly used by OKI for production at0.25 µm and 0.15 µm nodes for ultra-low-power circuits used in watches.[1] People

were wrongly afraid of the possible var-iability of the devices because of thethreshold voltage dependence on the sili-con film thickness, and were not inclinedto move from bulk to SOI, as they did notmeet major issues using bulk. That situa-tion has changed with the coming 20 nmnode and beyond.

The probability is low that bulk will beable to maintain the leakage current as low as it was for the previous generations.Many companies have started to work onalternative solutions, and FDSOI is emerg-ing as the best short-term solution from amanufacturing point of view. Other solu-tions are based on 3D devices (FinFET,multi-gate, nanoribbons … ) which willdemand more development time to reachthe manufacturing maturity. Note that allthese 3D devices are fully depleted devicesand can be implemented on either SOI orBULK substrates.

Coming back to the physics, FDSOI hasthe advantage that the vertical electric fieldin the channel can be controlled by adjust-ing the film thickness. The smaller the gatelength, the thinner the silicon film must beto achieve a low leakage current. A generalrule of thumb is that the silicon film thick-

Designing With FDSOI vs. Bulk

ness must be less than one-fourth of thegate length; for instance, a 5 nm silicon filmmust be used for a 20 nm gate length. Thethreshold voltage then becomes fixed bythe silicon thickness and the metal gatework function; there is no need for dopingin the channel region. This is a tremendousadvantage, as one can immediately deter-mine that the variability due to randomdopant fluctuation no longer exists.

The use of an ultra-thin silicon film maybecome a manufacturing obstacle at small-er nodes, being difficult to deal with a few nm of silicon. This constraint may bereleased by depleting the device from several gates controlling the silicon filmbetween them. The next step will be to use the FinFET: a vertical dual-gate fullydepleted device, where the required silicon

thickness may roughly be multiplied by 2 with respect to planar FDSOI. The nextquestion is, What are the implications onthe design side?

For planar FDSOI, a simple and directanswer is: There is no change from bulk; allthe electronic design automation (EDA)views used for circuit design are identical.Most of SOI circuit designs in the last 20years have used partially depleted SOI(PDSOI), and designers had to deal withthe history effect of the devices[2] toachieve a reliable timing closure of the cir-cuit paths. This effect does not exist inFDSOI, and timing analysis is run exactlythe same way than bulk.

The differences between planar FDSOIand bulk are only related to the deviceelectrical features. In particular, the SPICE

Jean-Luc PelloieARM

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SOI FinFET BULK FinFET

BURIED OXIDE

FIN

GATE

SILICON

HEIGHT

STI

FIN

GATE

STI

SILICONLOCAL IMPLANT

HEIGHT

Figure 1. SOI and BULK FinFET Cross-section Comparison




model must be dedicated to FDSOI, a bulkSPICE model will not accurately simulatethe FDSOI electrical features (current andcharge models). Several SPICE models are already available, such as BSIM-IMG(University of California at Berkeley), HiSIM(Hiroshima University) or PSP-SOI (ArizonaState University). It is also worth mention-ing that all interconnect metal layers abovethe transistors are identical for SOI andbulk, and the corresponding wire loads areequivalent. A direct migration of existingbulk EDA views may be applied to FDSOI.

Though not necessary, slight changesmay be achieved to get a better optimiza-tion due to the different FDSOI electricalfeatures: The transistors used in the logicstandard cells (optimum ratio betweenNMOS and PMOS is different betweenFDSOI and bulk), memory periphery andinput/output (IO) may be resized for opti-mal performance. The SRAM bit cell maybe identical or also slightly modified tobetter balance the pull-up, pull-down andpass-gate transistors. A much better mar-gin is expected due to the reduced vari-

ability, and low-voltage memory operationwill be easier to achieve,[3] which is a sig-nificant advantage for low-power applica-tions. When moving from bulk to FDSOI,the only EDA views that need to be modi-fied are those containing the electricalinformation: timing, power and noise,obtained from SPICE simulations (datacontained in liberty or .lib files). This isidentical to the recharacterization requiredwhen a bulk process modification results in a change of the SPICE models.

When implemented on a thin buriedoxide layer (typically 10 nm thick for 20nm node), planar FDSOI offers anotherstrong advantage: The threshold voltage of the transistors can be modulated by theback-gate bias applied to the substrateunderneath the buried oxide.[3] The mod-ulation is much more efficient than bulk;typically, 70 mV/V can be achieved, whichtranslates in a 10x reduction of the leakagefor a 1V change of the back-gate bias. Thewell bias has been extensively used in bulkdesigns to reduce the leakage (back bias)or improve the performance (forwardbias), but has become fairly inefficient atadvanced technology nodes because ofthe reduced threshold voltage modulation.FDSOI enables the continuation of imple-menting the reverse/forward biasing tomitigate power and performance.

FinFET may be seen as a 90° rotatedplanar FDSOI with the front and backgates connected together. It becomes avertical device, and the silicon thicknessbetween the gates is controlled throughlithography and etching process steps. The bulk version adds more process com-plexity: The bottom part of the fin is notisolated from the silicon substrate, requir-ing an additional local doping to avoiddrain-source punch-through leakage, andthe fin height results from a combination

of silicon etch and insulator planarizationand etch-back.

In the SOI version, the fin height corre-sponds to the silicon film thickness afteretching (Figure 1). The electrical features ofthe bulk and SOI versions are identical, andthere is no difference when designing witheither version. Contrary to planar FDSOI,FinFET has a significant impact on thedesign because of its discrete width. Thewidth of the transistor is no longer thelength of the drain-source diffusion; it nowresults from the fin height (roughly twice).The total width and then the delivered cur-rent of an active device correspond to thesum of fins connected together. It was usualin the past to compare the current per unitwidth between two technologies to indicatetheir performance. That no longer makessense when comparing FinFET to planar.What is important is the current per unitarea, which relates to the number of activefins that may fit in a given area. A real com-parison may only be achieved at circuit level.Cells using FinFET have a similar layout toplanar with the addition of the fins (Figure2). A direct porting of a planar design (bulkor FDSOI) to a FinFET-based design mayprove challenging because of the width mis-match. In addition to the EDA views modi-fied because of different SPICE models men-tioned for FDSOI, the layout views are alsodifferent. The FinFET discrete width is not an obstacle to analog design as long as asignificant total device width is required sothat many fins are used in parallel.

For both planar FDSOI and SOI FinFET,the protection against electrostatic dis-charge may be more area-consuming thanits bulk counterpart. This is due to the limited silicon volume used by the activedevices. This area increase is generallycompensated by the additional arearequired for latch-up protection in bulk.

Designing With FDSOI vs. Bulk DESIGN IMPLEMENTATION & PROCESS INTEGRATION

Active fins

Active fins

Figure 2. FinFET-based NAND2 Cell

MANUFACTURING: FABS, SYSTEMS & SOFTWAREClick here to return to Table of Contents

The latter part of 2012 finds most indus-try veterans older yet wiser after the les-sons of 2009, while still bracing for a roughcouple of quarters. Nevertheless, these arethe times when well-prepared companiesfocus on technology improvements thatwill better position themselves for theinevitable market improvements down theroad, and the two papers in this sectiondiscuss such technologies in depth. Inter-estingly, both papers deal with complexsystem integration issues at the factorylevel, but at two very different ends of theapplication spectrum.

The first paper in this section providesan excellent overview of the connectionpoints between a virtual metrology systemand the various applications that must sup-port it or are affected by its results. This is a refreshing departure from most of the literature that has been published on virtualmetrology (VM) to date, which tends tofocus on the analysis, modeling and algo-rithmic aspects of the technology (whichare often very process- or solution-specific)rather than the practical issues that must be dealt with to realize VM in a productionenvironment. In particular, the authors pointout the multiple data sources that must be integrated beyond the trace data from the process tools; namely, the wafer or lotstart/stop events, the logistic/context infor-

Alan WeberPresident, Alan Weber & Associates

mation (which may come from the MES),and the metrology results from prior runs.Moreover, they identify the related applica-tions that must comprehend the insertion of VM into the application suite; namely,(dynamic) lot sampling, R2R control, andequipment health monitoring, among oth-ers. All in all, this article is a “must read”treatment of the topic for people consider-ing a virtual metrology implementation.

The second paper deals with migrationof an entire manufacturing execution sys-tem (MES) from a legacy level of capabilityto a new set of production functionalityover some period of time. Migration of thisscale can be thought of as a combinationof integration and “dis-integration” pro-cesses of multiple types, including datasources and repositories, applications, userinterfaces and especially the underlyingbusiness processes … a daunting prospectfor any company. The authors rightly pointout that undertaking an MES migrationrequires clear justification, thoroughrequirements gathering, careful technol-ogy selection and planning, and above all,an experienced team that has done thisbefore. Even though the audience for thispaper may at first glance appear to be lim-ited, the insights offered apply to a broadrange of manufacturing system develop-ment/support organizations.

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Endnotes1. J.L. Pelloie, “FDSOI Design Portability

from BULK at 20nm Node,” IEEE SOIconference proceedings, 2011

2. J.L. Pelloie et al. “Timing Verification of a 45nm SOI Standard Cell Library,”IEEE SOI conference proceedings, 2010

3. T. Skotnicki, “Competitive SOC withUTBB SOI,” IEEE SOI conference pro-ceedings, 2011

About the Author

Jean-Luc Pelloie Jean-Luc Pelloie, ARM Fellow and direc-

tor of SOI Technology, is an SOI expert. Heco-founded SOISIC in April 2001, the firstindependent company offering SOI physicalIP blocks, after having spent more than 10years at LETI (Grenoble, France) on SOItechnology development, including colla-borations with IBM and TI. Jean-Luc joinedARM at the end of 2006 as a result ofSOISIC’s acquisition. Since then, he has driv-en the development of three SOI physical IP generations at 45 nm, 32 nm and 22 nm,and is currently working on 14 nm FinFET-based physical IP development. �


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Designing With FDSOI vs. Bulk


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MANUFACTURING: FABS, SYSTEMS & SOFTWARE MANUFACTURING: FABS, SYSTEMS & SOFTWARE

AbstractIn semiconductor manufacturing, metrol-

ogy operations are expensive and time-con-suming; for this reason, only a small sampleof produced wafers are evaluated. Virtualsensors are used to estimate the result of anoperation measurement relying on process-ing data parameters. This article describeshow virtual metrology should be integratedin a manufacturing system.

IntroductionManufacturing science is a primary

enabler for semiconductor companies toremain competitive for the next 10 years of technology evolution. Competitivenessmeans to be able to produce high-qualitynanoscale devices at a reasonable cost,quickly and effectively integrating rapidchanges in process technologies. Managecomplexity, enable flexibility and agility,rapidly adapt to technology changes arekey phrases used to describe most of thesemiconductor challenges of the future.

During the last 20 years, semiconductormanufacturers have focused on advancedprocess control (APC) topics, includingfault detection and classification (FDC)and run-to-run (R2R) controllers. Afterearly deployments on specific processessuch as chemical vapor deposition (CVD),

lithography, etch, epitaxy, etc., the effortswere concentrated in the realization of afab-wide solution (Moyne, 2004). The driv-ing factor, especially in the last 10 years,has been the need to improve yield (Tobinand Neiberg, 2001) and quality withoutimpacting productive throughput; suchtopics are even more important for theindustries facing high product mix andrapid product development phases.

Some research has focused on samp-ling techniques. While on one side, thiswould allow for reducing costs by avoid-ing unnecessary measurement operations,this posed sensitive problems for R2R con-trollers, which need a constant flow of real measurements to work. Constant challenges include the costs and reliabilityof equipment integration for data collec-tion and interaction with existing software(such as R2R controllers, FDC, in-situ sen-sors, yield management systems). The the-ory of a fab-wide solution that goes fromAPC to yield and integrates componentssuch as scheduling and dispatching repre-sents the next step in the semiconductorindustrial roadmaps.

Actually, the need (ITRS 2011, FactoryIntegration) is to move factory operationsfrom a reactive mode to a predictivemode: “Reactive practices such as FDC

Integrating Virtual Metrologyin a Manufacturing System

(fault detection and classification), preven-tive and unscheduled maintenance andreal-time scheduling and dispatching havebeen used in the past and also today butunfortunately they cannot eliminate wasteon product, downtime, cycle time, yieldloss etc. … this is due to the fact that thereis a reaction to an incoming problem.”

This means to migrate from fault detec-tion to fault prediction and in this way toreduce control events and fault occurrences,better scheduling maintenance events inorder to reduce unscheduled downtime and improve efficiency in daily maintenancework. On the other side, one of the impor-tant components is virtual metrology, whichwill ably provide metrology values in realtime at different product levels (lot, wafer,sites) at different equipment levels (equip-ment type, chamber, sub-chamber). Datasuch as sensors or APC key values, recipes,logistic data of lots – wafers and equipment,and also, if possible, maintenance informa-tion – are merged in a sequential data flowavailable for a virtual metrology algorithmor software.

A key challenge to reach the “predic-tion” goal is the development of robust,

configurable and real-time models andalgorithms. After data filtering and qualitydata check, the virtual metrology data areavailable for all the “customers” that needto use this information. One customer isthe R2R controller that will benefit fromthe good wafer/site information, solvingthe conflict between having no measure-ment for costs and having measurementfor better control. Another example is the“skip lot sampling,” which, based on a so-called wafer at risk, could decide when andwhat to skip. An equipment/process healthfactor system that can trigger maintenanceor other events can be also a customer ofVM information.

These are the main “systems” that couldbenefit from virtual metrology and the reli-ability of the calculations (see Figure 1). Agreat challenge in doing this is certainlythe high-mix factory environment and thecomplex process control (reaction to fre-quent recipes and process tools changes).The expectation’s target is the improve-ment of efficiency: productivity wastereduction, better product quality, higherprocess monitoring and controllability,yield and cycle time improvement, and last

Cristina De Luca,1 Andrea Schirru2

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Sensors Data

Logistic Data

Recipe Data

Maintenance

Data

Lot

Sampling

R2R

Controller

Equipment/

Process

Health

Factor

Trigger

Scheduling

Dispatching

Sequential

Data Flow

Virtual

Metrology

Calculation

Figure 1. General Virtual Metrology Data Flow: Input Data & Output & Possible Software Customers




but not least, reduction in utilities andpower consumption. Following is a view on how to integrate virtual metrology in amanufacturing system.

Data CollectionTo implement an automated virtual

metrology system, it is necessary to devel-op a robust online data import library thatwill be responsible for merging informationfrom heterogeneous sources to a commonformat. Specifically, the following sourcesof information should be available:• Raw equipment data dispatcher: This

interface sends, on a fixed-time basis,the sensor information coming from apiece of equipment, as well as the setparameters for the recipe currentlybeing processed.

• Synchronization component: This serv-ice, which can be either independent orincluded in the previous point, has thetask of sending synchronization tokensabout processed wafers (e.g., when theprocessing of a certain wafer begins orends), along with minimal logistic infor-mation.

• Logistic data provider: This componentis able to provide the full logistic scopeof a certain wafer on a request-replymode, receiving the minimal logisticinformation discussed above as input.

• Metrology data provider: This allows theintegration of the full process data (col-lected by means of merging the infor-mation of the first three components)with metrology information, wheneveravailable.

Using a wafer-specific key related to theabove systems (e.g., an RFID-based identityof the silicon slice, combined with minimalprocess-related key to identify the correctstep), enables building a homogeneouslearning dataset (Figure 2) with the following:• Unique wafer identifier (UWI): an internal

key that uniquely represents a silicon sliceundergoing a specific process step in aspecific piece of equipment

• Complete logistic infomation: all the logis-tic data (e.g., chamber position, recipename, etc.) associated to the UWI

• Complete process data: all the sensorreadings collected during processing, as well as equipment set points

• Metrology data: complete measurementtype (categorization) and (possibly multi-variate) measurement results

Following such dataset structure, it ispossible to configure a dataset extractionsystem for a specific logistic configuration(e.g., a certain recipe or process type) and associate it to a specific measurement(e.g., a thickness measurement). After thisstep, the dataset is ready to be processed bya mathematical algorithm.

Model Creation and PredictionWhenever it is possible to update a VM

model (that is, every time a complete waferis available – including metrology informa-tion), the above described dataset is elabo-rated by a mathematical procedure in orderto provide a VM model.

While the literature in terms of VM mod-els is quite wide, including hierarchicalapproaches,[3] kernel-based methodolo-

Integrating Virtual Metrology in a Manufacturing System MANUFACTURING: FABS, SYSTEMS & SOFTWARE

Figure 3. Logical Flow for Model Computation

Virtual Metrology Actual Metrology

Sensor DataProvider

CustomerApplications

LogisticData

Provider

MetrologyRoutingSystem

VirtualMetrology

System

MetrologyStation

SynchronizationComponent

Figure 2. Architecture and Dependencies of the Virtual Metrology System



gies[4] as well as models profoundlyimpacted by process expertise,[5] the mainfocus from the software architecture point of view must be set on the generic interfacebetween historical dataset and mathematicallibrary. Specifically, a system of interfacesmust be set in a way that any algorithm canbe implemented as a black-box procedure,where only the structures of input (historicaldataset) and output (the model) are prede-termined. From the point of view of architec-tural development, this allows for the decou-pling of the system from the employed algo-rithms, ensuring forward compatibility fornew breakthroughs in the VM learning field.

Special emphasis must be set on theparameter selection for the involved algo-rithm; in fact, it is well-known that mostlearning algorithms depend on an additionalset of parameters (called “hyperparame-ters”) that must be tuned to obtain optimal

predictive power. Given that the procedureused for such tuning operations is usuallythe same for very different algorithms, it isadvisable to implement a wrapper procedureto deal with them (e.g., by means of a gridsearch-based approach). In this way, a signi-ficant overhead in algorithm programmingwill be avoided, and suboptimal models willbe ruled out by a centralized procedure(Figure 3).

As soon as a model is calculated, it ispossible to use it to make predictions fornew wafers; specifically, every time a waferthat matches the model configuration isavailable (even without metrology data), a virtual measurement will result from theinput-output structure of the most recentlycalculated model. Depending on the capa-bilities of the model, additional indicatorsmight be available, such as confidence inter-vals or virtual goodness-of-fit (GOF).

An example of the results of a VM algo-rithm is given in Figure 4, comparing in4(a) real average thickness productive dataand virtual ones for 42 wafers (differenttechnologies, same target) and in f(b) thenine virtual sites as well as real measure-ment for one wafer. Upper and lower con-trol limits are not included in the figure asthey are well outside the considered win-dow. In the best case, such as this, all themeasurements are well inside the specifiedcontrol limits. If some of them are outsidethe 95 percent confidence limit, or theupper/lower control limits, the VM valuesfor that wafer are discarded.

ConclusionsThis article has briefly explained how

to implement a virtual metrology system in a real semiconductor manufacturingenvironment. Among the main challengesthat such an endeavor presents is having a robust data collection system for onlineVM calculation and wafer/equipment moni-toring purposes. The example shows theresults of a VM-algorithm application withreal online data. Furthermore, it is a keyaspect to provide a flexible interface formodel calculation in order to lower theimplementation effort for new method-ologies.

References1. Moyne, J., “Making the Move to Fab-

wide APC,” in Solid State Technology,vol. 47, No. 9: pp. 47-52 (2004)

2. Tobin Jr., K. and Neiberg, L., “MetrologyData Management and InformationSystems,” in Handbook of SiliconSemiconductor Metrology, SEMATECH

3. Schirru, A. et al. “Multilevel Kernel meth-ods for virtual metrology in semiconduc-tor manufacturing,” IFAC WorldCongress 2011, 11614-11621

4. Schirru, A. et al. “Virtual Sensors forSemiconductor Manufacturing: ANonparametric Approach - ExploitingInformation Theoretic Learning andKernel Machines,” Informatics in Control,Automation and Robotics, (2013) 175-193

5. Purwins, H. et al. “Regression Methods forPrediction of PECVD Silicon Nitride LayerThickness,” Automation Science andEngineering (CASE), 2011 IEEEConference, 387-392

About the Authors

Cristina De LucaCristina De Luca received her laurea

degree in statistical and economical science,University of Padova (Italy) and her Ph.D.degree in mathematics, University of Kla-genfurt (Austria). She joined Infineon Tech-nologies Austria in 2002, where she is cur-rently innovation project manager and staffengineer on the Innovation Managementteam. Dr. De Luca has worked on a widerange of R2R control applications and hassignificant experience in advanced processcontrol. She was project manager of the“IMPROVE” ENIAC Project for Work Package“Predictive Equipment Behavior.”

Andrea SchirruAndrea Schirru received his master’s

degree in computer science engineering and his Ph.D. degree in model identificationfrom University of Pavia (Italy). He partici-pated in the EU-ENIAC project IMPROVE. Dr. Schirru’s main research interests includevirtual metrology, fault detection and classi-fication, and machine learning models. �


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Figure 4. Comparison of real and wafer-level virtual measurements with 95% confidence interval forCVD thickness average (42 wafers from different technologies, same target) and site-level thickness (9 points) for 1 wafer. All the real and virtual measurements are between the control limits not includedin the pictures.




MANUFACTURING: FABS, SYSTEMS & SOFTWARE MANUFACTURING: FABS, SYSTEMS & SOFTWARE

AbstractSemiconductor manufacturers are

among the earlier adopters of MES sys-tems. Once vital to maintain the competi-tiveness of their operations, these applica-tions are becoming obsolete, and the needto circumvent their limitations causes sig-nificant cost, time and risk and will sooneror later impact these companies’ business.This article describes the limitations oflegacy MES and the main aspects to consider in a migration project.

The Need to MigrateIntroduction

Manufacturers operating in high-techsectors such as the semiconductor indus-try must continuously embrace change orfind themselves overtaken by more agilecompetitors. Forward-looking companiescan point to a history of innovation andcontinuous improvement – and know thatfurther change will be required to remainsuccessful. These changes encompasseverything from product conception,design and manufacturing to the sale, support and retirement processes.

Manufacturing execution systems (MES)play a vital role in this perpetual evolution.Almost no change can be done withoutthe appropriate enforcement, recording

and process automation that MES systemsprovide.

The MES is often considered a verymature market. However, many of thesesystems have evolved from homegrownapplications, and many commercial sys-tems have been developed to meet thenarrow requirements of certain industries.

Given the effort to build a new MES andthe need for a return on such investments,the majority of existing solutions weredeveloped 10, 20 or even more years ago,prior to the major technology advance-ments in recent years. Early suppliersaccumulated a significant customer basethat could not be abandoned or disruptedeven when new technologies becameavailable. Thus, improvements in legacysystems tended to be small and incremen-tal. However, these systems needed to bemaintained because, as we’ll see later,manufacturers were also reluctant tochange, providing a unique environmentfor extending the life of sometimesextremely obsolete technologies.

Without fast-evolving MES products,the burden of enabling the manufacturingprocess evolution was passed on to manu-facturers. Bigger semiconductor corpora-tions had dozens or even hundreds of per-sons building extensions and work-arounds

MES Migration: An AbsoluteNeed or a Utopia?

to overcome system limitations. Very-low-level technical framework features had tobe used due to the legacy technologiesinvolved. Every new feature had to bepatched in a complex network of function-al blocks that had not been designed forthat purpose, requiring considerable time,effort and risk, and an exponential futuremaintenance cost (see Figure 1).

Is this history? Not quite, as a majorityof the market remains in this state.

Main System LimitationsGiven the obsolescence of the tech-

nologies involved, many aspects limit theevolution and scope of the manufacturingprocesses. However, we will focus on fac-tors causing the greatest constraints.

ModelingThe modeling capability is perhaps

the most important, because it is one of the most difficult to be circumvented.Semiconductor processes are complex.There are cascading flows, processloops, optional steps, rework paths,alternate flows and non-sequentialsteps.

Material flows are frequently not dis-crete in nature, forcing the use of hierar-chical logical material structures. Materialsneed to be associated with position-controlled container models, and tracked to sublevels of clustered equipment. Dis-patching or sorting rules need to be dyn-amic and consider both cell and line opti-mization criteria.

Francisco Almada-Lobo, Jeff PeabodyCritical Manufacturing

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Figure 1. Most Common Legacy System Enhancement Strategies




Engineering data collections need to be recorded in real time, some manuallycollected, while others are collected auto-matically from measurement or productionequipment. These often need complex calculations, dynamic sampling and to bechecked against limits.

Without realistic modeling of the opera-tions, the result is inevitably a compromisein visibility, traceability and control. Thatcan be fatal.

Rule EnforcementRule enforcement is the second catego-

ry. It includes all aspects of misprocess prevention or of immediate reaction uponanomaly situations. Prevention includes ver-ification of limits, measurements, elapsedtimes, checklists, operations performed and other preconditions. Reaction includesautomatic material dispatching, equipmentactions, remeasurements, triggering excep-tion protocols and other possibilities.

A system that lacks rule enforcementcompromises product quality, yield andcycle time, and ultimately profitability.

Functional Coverage, Integration and Usability

While all MES systems deal with materi-al and resource tracking, the full scope of the manufacturing operations is muchbroader. Beyond tracking, a fully integratedsystem comprises monitoring, controlling,dispatching, quality and recipe manage-ment, equipment integration and automa-tion, documentation management, mainte-nance management, data analysis andbusiness intelligence.

Can’t this functionality be provided byother systems? It can, and depending onthe specialization requirements, sometimesit should. However, there must be a bal-ance between what’s in scope of the MES,

considering that external systems maymean a duplication of master data and a significant increase of integration andmaintenance effort. This becomes over-whelming with legacy systems and, everysubsequent addition is likely to exponen-tially worsen the problem.

The user interface plays an importantrole in terms of efficiency and usability. Itmust be ergonomic, integrated, oriented tothe operator flow and easily adaptable tochanging scenarios. Some traditional sys-tems still rely on character-based termi-nals, while others come with Visual Basicor Web-based interfaces that provide aless-than-ideal user experience and provecumbersome to extend and maintain.

So Why Don’t CompaniesChange Their MES Systems?

They certainly can, and it is inevitablethat they will do it sooner or later. Para-doxically, as companies are afraid of doingit, they make the situation worse by invest-ing more effort and cost in adding work-arounds and patches to keep up with theirdynamic environments.

Because of the dependency productionhas on the MES, fab managers have beenheard comparing MES migration to a hearttransplant. Getting a newer and leaner system is an appealing concept, but in theanalogy of the heart transplant, the newheart must be fully compatible with allother organs and the surgery must becarefully planned and executed.

Given the risks involved (in the MESmigration), the obvious question is, Whatare the benefits?

There are four primary drivers:• End-of-life support• High maintenance and operational cost• Effort to modify, extend and integrate• High turnaround times

Perhaps the only lethal argument to animmediate change would be the end-of-lifesupport, but legacy system suppliers con-tribute to the postponement of the deci-sion by continuously announcing supportextensions.

So, the justification must allow for amidterm gain, considering risk, cost andmissed revenue (opportunity costs) argu-ments. The short-term argument may bedifficult to see, but the long-term peril is simple and easily understood: Coping

with the required process agility willslowly become prohibitively expensiveuntil it becomes impossible. Every timethe decision is postponed, it makes thefuture migration more expensive andriskier.

The MigrationThree aspects must be considered

when planning the migration: the selectionof the MES; the migration scenario; and theproject team.

MES Migration: An Absolute Need or a Utopia? MANUFACTURING: FABS, SYSTEMS & SOFTWARE

Figure 2. Assessment of MES Migration Strategies



Selection of the Right MESThe selection of the right MES system is

key for the success of the migration proj-ect and the achievement of its objectives.

First, the new MES needs to address themajority, if not all, of the shortcomings ofthe legacy system. Vendor guides fromanalyst companies like Gartner[1] orLogica[2] are excellent starting points. The system must have full modeling pos-sibilities for materials, equipment, contain-ers, product structures, flows, steps, datacollections, but with high flexibility. Re-member that it will support the currentand future business needs. It must allowthe enforcement of rules and processesboth preventively and reactively. And itmust contain all necessary functionality tocover as completely as possible the manu-facturing system’s domain in a modular,yet service-oriented fashion. This facilitatesminimal integration effort within the mod-ules, but still provides room for specializedfunctionality to be performed by externalsystems with low integration efforts.

Second, it must eliminate the need foranother migration for many years. It makeslittle sense to replace a 15-year-old systemwith a 10-year-old system. The goal is touse the new system for 10 or more years.Beyond the model flexibility and functionalmodular coverage, it should allow an easyevolution in terms of configurability, exten-sibility and interoperability.

Third, and often ignored, the new sys-tem should be migration compatible. Thisrefers to the ability of the new MES to“mimic” the legacy MES to allow migration.This is ultimately related to the migrationstrategies described later, which includethe “big bang” approach, parallel systemsor phased introduction. The “big bang”approach is limited to master data migra-tion, but the need for compatibility is con-

siderably higher in the phased introductionand extremely high in a parallel systemapproach.

The Migration StrategyExploring the different migration strate-

gies would provide sufficient content for a much longer article. A migration projectis complex and needs to include: • Migration of master data• Migration of manufacturing software

processes• Reporting systems• Historical information• Integration with other applications• Deployment plans and procedures,

including software, hardware and people

• Risk mitigation and fallback solutions• Hand-over to operations & support

Figure 2 summarizes the most commonoptions. There are, of course, possible var-iations within each scenario.

The main point is that there’s no rightor wrong strategy, but one may better fityour needs. To determine the best strate-gy, the company must answer the follow-ing questions:• What is the level of risk the company

can cope with?• What is the amount of effort (cost and

time) that can be invested in the project?The migration strategy can now be

part of the MES selection criteria. With MES capabilities and strategy

determined, thorough planning withinvolvement from representative stake-holders is essential. Answering the follow-ing additional questions helps to betterdetermine the project complexity:• How much production downtime is

acceptable (from zero to n days)?

• What historical data needs to be usedwithin the new system (versus only in analytical or business intelligencedatabases)?

• How complex are the interfaces toapplications that require MES inter-facing?

The TeamWhile there are many MES professionals

with significant manufacturing and MESknowledge, resources specifically withmigration experience are few. Even if acompany decides to use a supplier with a history of successful deployments, it isessential for the team to include someonewith migration experience. Although eachmigration is unique and highly dependenton the environment and selected applica-tions, as well as on the strategy, personswho have been exposed to migration proj-ects know what needs to be consideredand how to react to specific migrationchallenges. Leveraging this experience isinvaluable and can often determine thesuccess of such a challenging project.

ConclusionsIn a Nutshell

Production and site managers constant-ly face a difficult balancing act. On onehand, they are challenged to excel on day-to-day operations, improving quality andthroughput, while at the same time reduc-ing cost. On the other hand, they need toensure the future long-term viability andcompetitiveness of their company.

Migrating an obsolete MES is anabsolute must. If not done, it will sooner orlater have a negative impact on the com-pany’s business. The longer it takes, thehigher the risk and the higher the effort.

It is definitely not a utopia. It has beensuccessfully done in very complex and

high-volume manufacturing environments.It requires the right migration strategy, theright MES, proper planning and of course,experienced people who have done itbefore.

Endnotes1. Vendor Guide for Manufacturing

Execution Systems, 2012, Gartner2. MES Product Survey, 2012, Logica

About the Authors

Francisco Almada-LoboFrancisco Almada-Lobo worked for

12 years in semiconductor IT for Siemens,Infineon and Qimonda. In 2004, he ledInfineon’s first migration of an MES systemin a running high-volume facility, and managed until 2009 a development centerimplementing MES projects worldwide.Francisco co-founded Critical Manufactu-ring in 2009, where he has been the CEOsince 2010.

Jeff Peabody Jeff Peabody served as director of

Sales and Marketing at itemic Corp. and as product sales manager for KLA-Tencor’sProcess Control group. From 2006 till2009, he held a senior sales executiveposition in the Global Services group ofApplied Materials. Jeff has been CriticalManufacturing’s VP for Sales and BusinessDevelopment since 2010. �


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LITHOGRAPHY LANDSCAPEClick here to return to Table of Contents

Building the Perfect MaskIn this section, Vibhu Jindal and his

colleagues at SEMATECH describe theircomprehensive search-and-destroy missionto find defects on EUV mask blanks, era-dicate their sources and help enable EUVmask equipment and materials suppliers to do the same. The targets of this missionare to meet the memory requirement ofzero defects larger than 100 nm, and lessthan 22 defects larger than 35 nm perblank, and to meet the logic requirement of zero defects larger than 75 nm and lessthan three defects larger than 25 nm perblank. The numbers are daunting.

This mission has required seeking outand destroying defect sources in mask substrate preparation as well as in the subsequent multilayer deposition process,leaving no rogue defect source to survive.Substrate preparation involves removal ofmaterial via various polishing techniques

Janice M. Golda Director, Lithography Capital Equipment Development; Intel Corp.

to deliver an extremely flat surface, fol-lowed by cleaning to remove defects gen-erated during polishing. Multilayer depo-sition requires depositing more than 80, yes 80, layers of film to build the EUVreflective film stack without adding de-fects. Destroying defect sources in themultilayer deposition process has requiredSEMATECH to seek out the defect sourcesin the deposition equipment and addressthem by working with the supply chain toimprove equipment design and materialsspecifications.

As a result of current progress, SEMA-TECH has demonstrated production of EUVblanks that can meet defect density asrequired for memory applications; however,further improvements are required to meetthe logic requirements, as well as to enablethe supply chain to deliver consistent yieldto enable high-volume manufacturing. Themission will continue …

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Nikon Corporation has been one of the world’s leading optical companies formore than 90 years. Nikon developed the world’s first production-worthy step- and-repeat photolithography tool in 1980.Since then, over half of all integrated circuits printed have been manufacturedon Nikon steppers and scanners.

Nikon has a long-established prece-dent of leading the industry throughinnovation and the continuous evolutionof our proven lithography solutions, providing photolithography systemsspanning the range of resolutionsrequired by today’s IC manufacturers.From high-throughput i-line steppers toadvanced immersion ArF scanners for 22nm half-pitch applications and beyond,Nikon delivers exceptional performancewith the lowest cost of ownership, andthe most comprehensive customer support of any manufacturer.

In 2007, Nikon shipped the industry’sfirst 1.30 NA immersion scanner, theNSR-S610C, for 45 nm half-pitch prod-uction. Later that year, Nikon also intro-duced the NSR-S310F and NSR-S210Dnon-immersion scanners. These systemswere evolutions of the S610C immersionplatform that incorporated Tandem

Stage technology to provide optimalperformance and cost of ownership fordry lithography applications.

Then, in 2009, to meet the stringentrequirements for 32 nm double patterningand provide extendibility to next genera-tion applications, Nikon introduced theNSR-S620D immersion scanner, which is based on the innovative Streamlignplatform. This was followed in 2011 by theNSR-S320F, an evolutionary Streamlignplatform-based system designed to deliver exceptional performance and productivity for the most critical dry ArFapplications. The most recent releasefrom Nikon is the NSR-S621D immersionscanner. This latest evolution of theproven Streamlign platform fully satisfiesthe aggressive overlay and throughputrequirements of high-volume immersiondouble patterning applications at 22 nmhalf-pitch and beyond.

Next generation lithography techniquescontinue to evolve, but IC makers needsolutions today that will keep them ontheir aggressive technology roadmaps.With a history of innovation and evolu-tionary lithography solutions, Nikon willbe there to ensure you maintain yourproduction timelines.

Proven Solutions Through Evolution

This Future Fab section is sponsored by Nikon

Nikon. Evolution in Action. | www.nikonprecision.com

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LITHOGRAPHY LANDSCAPE LITHOGRAPHY LANDSCAPE

Extreme ultraviolet (EUV) lithography isthe leading next-generation technology tosucceed optical lithography beyond the 22nm node,[1] and the availability of defect-free masks is one of the top two most criti-cal technology gaps hindering its commer-cialization.[2,3] The masks for EUV lithog-raphy are reflective, composed of a multi-layer structure consisting of molybdenumand silicon bilayer film, a capping layer, anda patterned absorber layer formed on a 6-inch glass substrate made of low thermalexpansion material. EUV mask blanks aredefined as multilayer structures with a cap-ping layer but without an absorber maskpattern. Defects can be incorporated at dif-ferent locations in the blanks depending ontheir various sources. Figure 1 shows all thepossible defect locations. Substrate pitsand embedded particles on the substrate,due to chemical mechanical polishing(CMP) or the cleaning process, are majorconcerns, as they are small and often diffi-cult to detect. Particle residues left on thesubstrate due to cleaning, storage or han-dling are another major contributor of maskblank defects. Other significant sources aredeposition particles within or on top of themultilayer due to material handing within

the deposition tool and from the depositionprocess and pits or particles added post-deposition from storage, cleaning or han-dling. The insufficient progress across theindustry in reducing mask blank defectshas prompted SEMATECH to concentrateefforts on identifying their major sources,implementing mitigation techniques, anddemonstrating a yielding EUV mask blankmultilayer deposition process with lowdefect density. Ongoing research atSEMATECH has provided opportunities for blank suppliers to acquire early learningon the deposition, cleaning and inspectiontools, providing the impetus to improveEUV mask blank quality for the industry.This work has enabled mask blank and toolsuppliers to improve processes for multi-layer deposition,[2,3] develop novel clean-ing techniques for EUV substrates andblanks,[4] and evaluate the metrologyinfrastructure for mask blank defects tomatch the industry’s needs.[5]

The current industry requirement formemory applications specifies that EUVblanks contain 0 defects >100 nm, consid-ered killer defects and less than 22 defects>35 nm in the quality area. The defectrequirements for logic applications are

Reducing Defects in EUVMask Blanks to Enable High-Volume Manufacturing

more stringent, requiring 0 defects >75 nmand less than 3 defects >25 nm. SEMATECHhas been able to determine the criticalcomponents and sources of defects thatare impeding progress in mitigating EUVmask blank defectivity. Defects from theshields and targets are large killer defectsthat must be completely eliminated. Char-acterization of the target surface aftersputtering shows a tendency for noduleformation and roughness near the edges,primarily due to divergence in the ionbeam. Based on the analysis of mask blankdefects and the tool, the two main contrib-utors to target defects were determined tobe from scattered ion-beam sputtering onthe edges of the target and the materialproperties (dopant properties, void density,surface finish, etc.) of the bulk target mate-rials. A number of defects can also origi-nate in the shield areas when (a) installed

shields are not cleaned properly; (b) heavydepositions cause cracking or flaking onshield surface; and (c) the shield surface isetched by the scattered ion beam. The col-lective improvements to tool componentsand processes were able to significantlydrive down the number of large defects.The recent improvements in cleaningprocesses at SEMATECH were also able toreduce total defectivity and improve theyield of high-quality mask blanks. With theimplementation of these improvements,SEMATECH was able to report a new cham-pion mask blank three times in the last fourquarters. A champion mask blank of 28defects >45 nm was reported in 2011,[6]with a further reduction to 19 defects >45nm by the end of Q1 2012. The latest cham-pion mask blank at the end of Q2 2012shows 12 defects >45 nm, with only 8defects >50 nm within the quality area (132

Vibhu Jindal, Patrick Kearney, Arun John, Frank Goodwin SEMATECH

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Figure 1. EUV masks blank defects categorized based on location and possible defect sources.



mm by 132 mm) as measured by theLasertec M7360 (Figure 2) in a dense scan mode.

As a result of our current progress,SEMATECH has demonstrated productionof EUV blanks that can meet defect densityas required for memory applications; how-ever, further improvements are required to meet logic requirements. The yield of the mask blank deposition tool, whichhas been an increasing concern, was alsoimproved in the last year. The yield of high-quality mask blanks (less than 20 defects>45 nm) in the clean phase was found to be just over 20 percent (Figure 3(a)).SEMATECH has a clear path to drive furtherimprovement of EUV mask blank championdefectivity and to address the lack of cor-responding yield through the design ofnext-generation deposition tools equip-ped with improved handling capability.Improvements in some of the critical com-ponents within the ion beam depositionsystems – such as the ion beam source,substrate fixture and substrate chuckingmethod – are also required. The next-gen-eration deposition tool should have ionsources in which divergence will be tightlycontrolled and scattered high-energy ionsand neutrals minimized. As defect data

have shown, the dual-pod reticle carrier hassuperior defect protection when comparedwith a standard reticle standard pod. Thenext-generation tool should be configuredto support and integrate the dual-podfront-end handler. Furthermore, tool sup-pliers should proactively be involved inthese advancements and improvements.

The demands for EUV mask blanks willincrease over the next few years; however,the industry is currently not equipped tomeet these demands. The need for high-quality EUV mask blanks is expected toreach up to 5,500 per year in 2015. Thehigh demand will generate capacity issuesfor ion beam deposition systems andunavailability issues for high-quality sub-strate yields. The supply of high-qualityEUV substrates has often been overlooked.The current yield on such quartz sub-

strates (less than 5 defects >45 nm), asprocured by SEMATECH, is insufficient,(Figure 3(b)). The yield on low thermalexpansion material substrates is even lesswith the current technology. As can beseen in Figure 4, more than 18,000 high-quality substrates are needed to yield5,500 high-quality mask blanks per year at a 30 percent yield in the ion beam dep-osition system. Meeting such demandsinvolves addressing numerous substraterequirements, especially considering thecurrent issues with substrate quality andcleaning. Achieving these targets willrequire a new multilayer deposition tool to improve the deposition yield on high-quality blanks, extensive innovations to improve substrate quality and cleaningto enable high-volume manufacturing oflow-defect density blanks.

Reducing Defects in EUV Mask Blanks to Enable High-Volume Manufacturing LITHOGRAPHY LANDSCAPE

Figure 2. Champion EUV Mask Blank With 12Defects >45 nm and 8 Defects >50 nm as Inspectedby the Lasertec 7360 in Dense Scan Mode

Figure 3. (a) Yield of EUV mask blanks with under 20, 20-30 and over 30 defects >45 nm after EUVmask blank deposition; (b) yield of EUV substrates under 5, 5-15 and over 15 defects >45 nm aftersubstrate preparation and cleaning

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FRONT END OF LINEClick here to return to Table of Contents

In the semiconductor industry, highyield and low cost are two very importantissues that are closely related to the manu-facturing profit. There are many factors andissues that could impact the performanceof the yield and the cost. In this section,there are three excellent papers that dis-cuss ways to enhance yield and to reducethe process cost.

The paper from the University of Milanand Technofittings S.r.l. introduces a noveloptical method to measure the particles infabs. The measurements at different situa-tions and the reliability of the method arepresented in the paper.

In terms of yield enhancement, manage-ment improvement for airborne molecular

Jiang YanProfessor, IMECAS

contamination (AMC) is proposed in thepaper from Pfeiffer Vacuum and GLOBAL-FOUNDRIES. As AMC is a key contributorto yield loss, control of AMCs is very impor-tant to yield enhancement. The concepts of DOSE and DOSElim and evaluation of the various solutions are discussed in thepaper.

In the paper from Texas Instruments,several effective ways to reduce processcosts by chemical savings are introduced –a key topic, as usage of chemical materialsin semiconductor manufacturing fabs ishuge and costly. Good methods for chem-ical saving include chemical reuse,increased bath lifetime and equipmentreconfigurations.

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References1. S. Wurm et al. “SEMATECH’s EUV pro-

gram: a key enabler for EUVL intro-duction,” Proc. SPIE 6517, EmergingLithographic Technologies XI, 651705(March 23, 2007)

2. V. Jindal et al. “Ion beam depositionsystem for depositing low defect den-sity extreme ultraviolet mask blanks,”Proc. SPIE 8322, Extreme Ultraviolet(EUV) Lithography III, 83221W (March29, 2012)

3. V. Jindal et al. “Modeling the EUV multilayer deposition process on EUVblanks,” Proc. SPIE 7969, ExtremeUltraviolet (EUV) Lithography II, 79691A(April 6, 2011)

4. Abbas Rastegar and Vibhu Jindal, “EUVmask defects and their removal,” Proc.SPIE 8352, 28th European Mask andLithography Conference, 83520W (April16, 2012)

5. V. Jindal et al. “SEMATECH's infrastruc-ture for defect metrology and failureanalysis to support its EUV mask defectreduction program,” Proc. SPIE 7969,Extreme Ultraviolet (EUV) LithographyII, 79690I (March 29, 2011)

6. V. Jindal and F. Goodwin, “Roadmap forDefect-Free Extreme Ultraviolet MaskBlanks,” Future Fab International, Issue39 (October 2011)

About the Authors

Vibhu JindalVibhu Jindal is the group leader in

SEMATECH’s EUV Mask Blank DefectReduction program. He received his B.S. in material science from the Indian Instituteof Technology, Bombay, and his Ph.D. innanoscale science and engineering fromSUNY-Albany.

Patrick KearneyPatrick A. Kearney earned B.S. degrees

in physics and mathematics with minors in optics and electronics from the Rose-Hulman Institute of Technology in 1987, and a Ph.D. in optical sciences from theUniversity of Arizona in 1994. From therehe moved to Lawrence Livermore NationalLaboratory until 2004, developing andrefining several techniques for deposit-ing multilayer mirrors. In 2004, Patrick moved to SEMATECH’s EUVL Mask BlankDevelopment Center to aid in the develop-ment of EUVL mask blank infrastructure.

Arun JohnArun John Kadaksham has been a proj-

ect engineer at SEMATECH for six years.His primary focus is reducing nanoparticledefects on substrates for EUV lithography.Dr. Kadaksham previously held positions as a post-doctoral research associate atClarkson University, where his research wasmainly focused on nanoparticle adhesionand removal.

Francis Goodwin Francis Goodwin is the program man-

ager for SEMATECH's EUV Mask BlankDefect Reduction program and MaskBlank Development Center. He has morethan 20 years of experience in lithography,has held management and engineeringpositions throughout his career, and hassupported ASIC, logic and advancedDRAM operations. �


Reducing Defects in EUV Mask Blanks to Enable High-Volume Manufacturing

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Thought Leadership Profile

Hitachi High Technologies, Inc. (HHT) is proud to introduce the semiconductorindustry’s highest-volume production etchtool for critical and non-critical etch layers.

The HHT M-9000XT Lynx is a linear pro-duction platform that offers best-in-classthroughput per footprint of any etch clus-ter available to the market. The Lynx plat-form offers a significant advancement inextendibility by integrating from one tonine process chambers, thus allowing theM-9000XT to be configured to meet theexact needs of SC manufacturers. The abi-lity to add process chambers allows the M-9000XT to grow with production capac-ity requirements. Manufacturers can takeadvantage of a small R&D investment byinstalling a single-transport unit module to support one to three process chambers. As the development moves toward prod-uction, the SC manufacturer can add up to two additional transport unit modules,allowing a maximum of nine process cham-bers to support high-volume manufactur-ing (HVM). Flexibility and extendibility arethe advantages to the new Hitachi HighTechnologies M-9000XT.

The HHT M-9000XT is capable of integ-rating different chamber types but the HHTMicrowave ECR or M-XT chamber is the pri-mary chamber for today’s state-of-the-artetch processes. The M-XT plasma etch cham-ber delivers the best etch uniformity, tightestprocess control and highest productivity ofany etch system available to the SC market.

Etch uniformity is the key design concept for the M-XT. HHT retained theMicrowave ECR plasma source and all itsadvantages while redesigning the gasdelivery and evacuation of the chamber to provide superior uniformity of reactivegases reaching the wafer surface andbyproducts being removed from theprocess chamber.

Combining the highest-capability etchchamber with the new ultra-high-through-put platform allows HHT to offer the mostsignificant new etch tool to the SC market.When your fab is ready to shift into highgear, contact Hitachi High Technologies,Inc. to learn more about the possibilities to improve your process and increase yourproductivity with the HHT M-9000XT.

Hitachi High Technololgies suppliesplasma etch systems to the world’sleading SC and HDD manufacturers.HHT customers rely on Hitachi’s tech-nology, innovation and reliability tohelp them succeed in creating today’smost advanced microprocessors, DSPs,memory devices and HDDs. Hitachietch systems are renowned for theirsuperior technology and production-proven reliability in the most demand-ing SC and HDD manufacturing envi-ronments.

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AbstractWe present the results of a feasibility

study for the exploitation of a novel light-scattering method for monitoring watersuspensions of submicron particles ofinterest for nanoelectronics fabs. In a col-laboration between the University of Milanand Techno Fittings S.r.l., we realized aprototype of a device based upon a recentoptical method for single particle sizingthat is calibration free and provides resultswithout any free parameter. We showresults obtained with calibrated, monodis-persed spherical particles, as well as sam-ples with broad size distributions of grainsmade of different materials. The suitabilityof the method for specific nanoelectronicsapplications is discussed.

We recently proposed[1] a novel light-scattering method for measuring the size ofsingle submicron particles, claiming a poten-tial interest for performing measurements ofinterest for nanoelectronics fab processes.This method relies on the illumination of asingle particle brought into the scattering

volume and the consequential interferenceof the scattered wave front with the trans-mitted beam. Exploiting the fundamentals of optics, more information than the basiccross-section measurement can be recov-ered from the time-dependent intensity dis-tributions at a given distance from the scat-tering volume. This method is capable ofovercoming the limitations of the currentoptical methods measuring single particles,typically due to the presence of stray light,fake events, multiple events, determinationof the traversing position of the particlewithin the light beam, calibration problemsand rejection of air bubbles. For a completeoverview of the traditional methods, one canrefer to Terrell, and Mitchell and Bast.[2,3]On the basis of some typical issues at thenanoelectronics fab processes – such as, e.g.,the quality of the slurries used for chemicalmechanical polishing (CMP) processes – wedesigned and realized a prototype especiallydedicated to the aim.

The method is the result of the activityperformed during the last few years at the

Monitoring Fluid Suspensions:Current Results & Perspectivesof a Novel Method Based onLight Scattering

University of Milan, and the recent partici-pation of all the authors to the Europeanproject IMPROVE, within the ENIAC plat-form. During the last 10 years, several opti-cal methods have been conceived andrealized based on the measure of thetransmitted light just downstream a sam-ple.[4-6] These schemes are as simple aspossible, with almost no instrumentationneeded and free from any complex align-ment procedure. The measure of the trans-mitted light provides determination of the overall power reduction of the beam,which is ultimately a perfect measure ofthe particle cross section. At the sametime, this geometry also promotes a self-reference condition, where the intensitydistribution at a distance from the scatter-ing volume is given by the interference ofthe scattered wave front and the transmit-ted beam. The self-reference conditionnaturally gives an intrinsic calibration ofthe signals, and allows the development of a model describing the instrument with-out any free parameter.

Particle suspension is brought into thedevice after a very high dilution, such thata single particle at a time is statisticallypresent within the scattering volume. Theflux is forced along a given, known direc-tion at a definite speed (0.1 m/s, in ourcase), and passes through a focused laserbeam. The intensity distribution due to theinterference between the wave front scat-tered by the particle and the main trans-mitted beam changes with space and timedepending on: 1) the size of the particle; 2) the refractive index of the particle; 3)the position of the particle across the lightbeam. Once the velocity (direction andspeed) is known, one can cope with justtwo parameters the particle is endowedwith (see below for further details). There-

fore, the fast acquisition of intensity signalsis a crucial point here, and resulted in thedevelopment of a dedicated front-endelectronics (FE). Indeed, the ultimate limitof this method is ideally represented bythe capability to tell apart the true signalsgenerated by particles passing through thelight beam from the very intense transmit-ted beam. This is an issue here, since thesignals to be detected are as small as sev-eral 10-4, corresponding to the limitationsimposed by the current laser sources’ sta-bility (relatively cheap sources are consid-ered here, as imposed by the fab environ-ments). The developed FE is an innovativepreamplifier capable of an automatic, real-time rejection of the DC signal, based on adouble-ring negative feedback architecturewith good stability and linearity. It physi-cally separates the DC and the AC signals,bringing the small fluctuations to zeroaverage.[7]

Under these conditions, a sensibilityclose to the limits of current optical deviceshas been achieved. Depending on the parti-cle refractive index, the current sensibility isapproximately 150-200 nm in diameter.Notice that this is not the ultimate sensibili-ty for the present method, which can becapable of detecting and measuring thesize of much smaller par-ticles if a moretightly focused beam is used. On the otherhand, a decrease of the scattering volumewill appreciably reduce the counting rate.The current sensibility represents a trade-off that permits one to obtain relatively fastmeasurements of a suspension, with a reso-lution down to approximately 20 nm in thelower size range and an accuracy of severalpercent for each bin of the distribution. Wecare-fully analyzed the laser stability issue,and compared several sources as detailedin Sanvito.[8]

M.A.C. Potenza,1 T. Sanvito,1 A. Pullia,1 D. Di Cola,2

D. Lavalle2 G. Fazio,3 A. Filippini,3 L. Caudo,3 G. Spinolo3

1Physics Department, University of Milan, 2Technofittings S.r.l., Rome, 3Micron S.p.A., Italy

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After the acquisition of intensity signalswith the FE, the data reduction schemeactually represents a fundamental featureof the method. A procedure of pulse shapeanalysis (PSA) permits: 1) a strict classifi-cation of the measured signals, telling theposition of the particles within the scat-tering volume; 2) access to informationbeyond the sole cross section on the basisof the peculiar signatures that are presentin the intensity distributions. Briefly, thePSA operates as follows: 1) the time seriesanalysis of two parameters, a(t) and b(t),are determined; 2) any fake, multiple orbubble event can be eliminated; 3) the

position of the particle passing though thelight beam, and the corresponding intensi-ty profile of the illuminating beam at thatposition are determined; 3) two physicalparameters, A and B, are determined fromthe time series a(t) and b(t). Parameter Ais related to the particle cross section (thatslightly depends on the particle’s refractiveindex); parameter B depends on the opti-cal thickness of the particle; i.e., the prod-uct of the diameter and the refractiveindex. Note that just due to the self-refer-encing conditions, each time series can benormalized so that a(t), b(t), A, B are purenumbers.

In Figure 1, we show the resultsobtained with water suspensions of cal-ibrated, monodispersed polystyrenespheres (200, 240, 290, 430 nm in dia-meter). The size distributions are shown,recovered on the basis of accurate Miecomputations for the optical cross sec-tions. As can be seen, a very high resolu-tion is obtained. While the sensibility ofthe device is given by the laser stability asdiscussed above, the resolution is mainlygiven by the PSA used to obtain the inten-sity profile encountered by the particlewhen traversing the beam. This dependson different experimental parameters, such

as the beam shape quality and the lasernoise. Note that although decreasing theparticle diameter, the raw signals are morespread out due to unavoidable noise; theactual size resolution is higher just for thesmallest particles, thanks to the strongerdependence of the signal amplitudes onthe size itself.

Figure 2 shows the size resolutionobtained for a suspension of ground pow-der. These tests have been performed tocheck for the reliability of the method withmore realistic, non-ideal samples (as thepolystyrene spherical particles are). In thiscase, the results show that the method

Monitoring Fluid Suspensions: Current Results & Perspectives of a Novel Method Based on Light Scattering FRONT END OF LINE

Figure 2. The Size Distribution Obtained With a Suspension of a Ground Powder Endowed With a Large Polydispersity and Nonspherical Shape of the Particles

Figure 1. Results obtained with water suspensions of calibrated, monodispersed polystyrene spheres(200, 240, 290, 430 nm in diameter). Histograms indicate the fractional content of each bin.



maintains the performances. The onlysmall limitations are: 1) the knowledge ofthe refractive index; and 2) the effect ofthe nonspherical shape of the particles.Both slightly reduce the resolution, as agiven refractive index and the sphericalapproximation are assumed (as is usuallydone) for recovering the particle diameter.

In Figure 3, we show the size distribu-tion obtained from a measurement per-formed with a suspension of ceria particlescommonly used to polish optical surfaces.In this case, the refractive index is well-known (2.1), and can be used to determinethe cross sections (under the spherical

approximation). The binning is compatibleto the size resolution, while the error barsare obtained from the Poisson statistics foreach bin. As can be seen, the method cangive insight into the details of a size distri-bution, thanks to the superior resolutionand reliability of assigning the size. Thisrepresents a feature that suggests poten-tial applications in measuring sizes of sub-micron particles. This collaboration aims to assess the feasibility of such measure-ments for in-line monitoring and analysisof liquids for nanoelectronics fabs such asCMP slurries (similar to the ceria samplesshown in Figure 3). A possible integration

of the device within the advanced processcontrol could result in a continuous moni-toring of the slurry, with the possibility ofautomatic feedback on the process.

AcknowledgmentsThe authors gratefully acknowledge

the following: The apparatus has been realized by D. Viganò (Workshop of theDepartment of Physics, University ofMilan). This work has been developedwithin the framework of the Europeanproject IMPROVE, with financial supportfrom University of Milan and TechnoFittings S.r.l.

Endnotes1. M.A.C. Potenza et al., “A Novel Method

for Monitoring Fluid Suspensions:Current Results and Perspectives,”Future Fab International, vol. 39 (2011)

2. E. Terrell, et al. “Understanding LiquidParticle Counters,” PMS Inc. Boulder,Colorado (2006)

3. J. Mitchell and B. Bast, “ComparingParticle Counter PerformanceCharacteristics for Analyzing High-Purity Water,” Ultrapure Water, 48(2000)

4. M.D. Alaimo et al. “Probing theTransverse Coherence of an UndulatorX-Ray Beam Using Brownian Particles,”Phys. Rev. Lett. vol. 103 194805 (2009)

5. M.A.C. Potenza et al. “Confocal zero-angle dynamic depolarized light scat-tering,” Eur. Phys. J. E 31 69-72 (2010)

6. M.A.C. Potenza et al. “How to Measurethe Optical Thickness of Scattering

Particles from the Phase Delay ofScattered Waves: Application to TurbidSamples,” Phys. Rev. Lett. 105 193901(2010)

7. A. Pullia et al. “A Low-Noise LargeDynamic-Range Readout Suitable forLaser Spectroscopy with PIN Diodes,” in press, in Rev. Sci. Instrum.

8. T. Sanvito, et al. “A method for charac-terizing the stability of light sources,” in preparation.

About the Authors

University of Milan, Physics DepartmentM.A.C. Potenza – Assistant professorTiziano Sanvito – Ph.D. student in physicsA. Pullia – Associate professor

Technofittings S.r.l.Domenico Di Cola – General managerDaniele Lavalle – R&D manager

Micron S.p.A., ItalyGiuseppe Fazio – Senior Engineer,APC/AECA. Filippini – Senior Engineer,Contamination Control LeadLeonardo Caudo – Senior Engineer, CMPLeadGiulia Spinolo – Manager, CMP �


Monitoring Fluid Suspensions: Current Results & Perspectives of a Novel Method Based on Light Scattering

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Figure 3. The Size Distribution Obtained From a Measurement Performed With a Suspension of Cerium Oxide, Obtained by Strongly Diluting a Slurry Commonly Used to Polish Optical Surfaces

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Introduction With chip dimension shrinking, airborne

molecular contamination (AMC) is well-known as a key contributor in avoidingyield loss and quality degradation.[1-2]And as for everything related to yield, sig-nificant investments to fight against thisinvisible enemy are made. As a conse-quence, there are as many strategies asthere are semiconductor fabrication plants;bay and EFEM filtration; wafer and reticulestocker with AMC filtration or purge cap-abilities; new substrate carrier materials;stand-alone, EFEM or stocker purge; Qtimemanagement – it is quite the mixed bag.

To solve this problem in a cost-effectivemanner, we need to fully understand thecauses and their effects, and finally manage a global solution addressing each cause. Inthis paper, the importance of AMC-behaviorunderstanding will be highlighted and thelinks between AMC and yield will be exposed.Finally, current solutions will be describedand evaluated. An example of AMC manage-ment results in a 300 mm advanced fabrica-tion plant will be then discussed.

AMCsSpecies to Be Controlled

One of the Yield Enhancement ITRSgroup’s topics is Wafer EnvironmentContamination Control (WECC). This sub-group is involved in defining the type andthresholds of AMCs that may lead to waferdefects. In 2011, a restructuration of the YE WECC table was published; one of thegoals was to set the difference betweencleanroom and FOUP contaminationspecies and thresholds. Please refer to theYE3 table in the Yield Enhancement chap-ter: (http://www.itrs.net/Links/2011ITRS/Home2011.htm).[3]

From this YE3 table, we can extract thelist of AMCs that can lead to wafer defects,in order to define the species that needs to be controlled inside FOUPs:• Total inorganic acids• HCl• HF• HBr• HNOx

• Total organic acids• Total bases

Yield Enhancement Through Airborne MolecularContamination Management

• Total other corrosive species• H2S• Total sulphur compounds• Volatile organics (with GCMS retention

times ≥ benzene, calibrated to hexade-cane)

AMC Sources Inside FOUPThere are three AMC sources in FOUP

environment (Figure 1).[4-5]• Cleanroom contamination, through the

FOUP leakage or filters – As cleanroomsare well-controlled, this contaminationcan be considered “under control” incomparison with the two other sourcesof contamination.

• Wafer outgassing – After each processstep, wafers are stored inside FOUPs,waiting for the next process step.Wafers will then outgas a significantamount of last process byproduct.

• FOUP outgassing, coming either fromthe polymer material itself, or from theoutgassing of previously adsorbed mol-ecules on the polymer (memory effect).

Mechanism of Wafer DegradationFrom the two AMC main sources inside

FOUPs, mechanisms of wafer defects due to AMC are illustrated in Figure 2.

Shrinking dimensions, together withprocess gas quantities, which increase intandem with throughput ramp-up (lesspurging time/wafer), are the root causesfor wafer AMC outgassing. As a conse-quence, and as FOUP is a closed environ-ment, these wafers will outgas during thestorage between two process steps in theFOUP environment, and will lead to anincrease in AMC concentration. Chemicalreaction may occur as well as defectgrowth, leading to yield loss (Figure 3).

Moreover, the ability of polymer FOUPto absorb molecules can be relativelyhigh[6] and degassing of absorbed mole-cules could last for days or even weeks.FOUP wet cleaning is not efficient enoughto remove AMC from the FOUP. As a con-sequence, cross-contamination can occurwith new wafer batches.

The Concept of DoseAs explained above, we can summarize

wafer damage due to AMC with theschematic found in Figure 4.

Interaction of AMC, substrate materialsand moisture during wait time betweentwo process steps may lead to particlegrowth and yield decrease. AMC concen-tration [AMC] and storage time (St) arekey parameters to control; that is the reason we introduce the “DOSE” concept:

DOSE = [AMC]*St

Moisture cannot be considered com-pletely as a contaminant by itself, but itcan act as a catalyst that increases theimpact of some AMCs. As an example, a

Arnaud Favre,1 Julien Bounouar,1 Emmanuelle Véran,1

Astrid Gettel,2 Marco Ackermann2

1adixen Vacuum Products by Pfeiffer Vacuum, Annecy, France2GLOBALFOUNDRIES, Dresden, Germany

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Cleanroom contamination

Wafer outgassing

FOUP

outgassing

Figure 1. AMC Contamination Sources in FOUP




higher moisture level can increase the corrosion effect of acids.

DOSE is thus a “quantity of contamina-tion,” and defects will appear when DOSE> DOSElim, where DOSElim is a function ofmaterial surface and contaminant type.The current trend is a decrease of DOSElim,as new materials such as ultra-low-K areintroduced in production. This is the rea-son AMC-related issues are more and morecritical to FOUP-related contamination.

AMC Concentration During StorageThere are different concentration

behaviors inside FOUPs, and it is importantto understand that they are related to thelast wafer process step (Figure 5).• Right after a process, the FOUP will be

first open on the EFEM, and AMC con-centration can be considered almostzero (depending on EFEM filtration or,without EFEM filtration, on cleanroomquality).

• Then, wafer (and/or FOUP) outgassingtakes place. We observe a competitionbetween two phenomena. Wafer out-gassing leads to an increase of AMCconcentration inside the FOUP, whileFOUP leakage and AMC adsorption onFOUP inner surfaces lead to a decreaseof concentration. This competition isrepresented by a second-order function.

• The maximum in AMC concentrationcan occur right after the FOUP closure,after the last wafer has been inserted,or later during the storage time.

As a conclusion, DOSE can be expressedas the integration of these curves, i.e., inte-gration of concentration with time. As DOSEis a quantity, its unit is [mol] (Figure 6).

In this example, DOSElim cannot beexceeded after process 1. Storage after this process is not critical. However, afterprocesses 2 and 3, defects will appearrespectively after tmax2 and tmax3. Actionsneed to be undertaken for these two criti-cal processes.

Control of AMCsFOUP Measurement

To control AMCs, it is crucial to monitortheir concentration [AMC] inside FOUPs.There are two general methods: offline andonline measurements. As the concentrationof AMC is time dependent, AMC measure-ment must be carried out in the produc-tion environment to be able to evaluatethe AMC concentration behavior, and toset up quickly the containment actions.

adixen Vacuum Products, by PfeifferVacuum, has developed and patented aninnovative equipment. This equipmentmeasures [AMC] (total acids, total amines,total volatile organic compounds andmoisture) at ppbv level inside FOUPs (withor without wafers inside) within two min-utes, and can be integrated into the pro-duction flow. This equipment – APA302 –is widely used in semiconductor fabrica-tion plants for advanced nodes, such as at GLOBALFOUNDRIES, and enables rapididentification of AMC issues and solutionqualification.

Current SolutionsVarious industrial solutions are available,

currently installed in semiconductor fabs.However, before listing and evaluatingthem, it is necessary to identify the para-meters they are dealing with.

Coming back to DOSE expressions:

DOSE = [AMC]*St with apparition ofdefects when DOSE exceeds DOSElim

DOSElim cannot be modified, as itdepends on wafer materials and processgas. As a consequence, AMC concentration[AMC] and storage time St are the only twoparameters to consider lowering the DOSE.

Many industrial solutions address thesetwo parameters.

Yield Enhancement Through Airborne Molecular Contamination Management FRONT END OF LINE

Wafers are processed

with chemical gases

Byproducts are

outgassed from wafers in

FOUP

Chemical reactions in

FOUP will lead to defects

on wafers

Process chamber

Figure 2. Defects Due to Wafer Outgassing

Gas coming from

previous wafer or FOUP

material

Outgassing from FOUP

to wafers

Chemical reactions in

FOUP will lead to defects

on wafers

Figure 3. Defects Due to FOUP Outgassing

AMC

H20 Storage time

DEFECTS

Figure 4. Schematics of Defect Apparition



Queue time (Qtime): setup of maximumduration between two process steps. Withdimension shrinking, maximum duration is decreasing drastically (sometimes <2h)and it is more and more difficult to handlein a production environment without hugeinvestment. If the Qtime is exceeded,wafers are either scrapped or reworked.

FOUP Change: After the critical step,wafers are removed from the initial FOUPand introduced in a clean FOUP throughthe wafer sorter.

FOUP N2 purge: Specific FOUPs have theability to be purged with clean N2 either ona specific load port, or in a specific stocker.

EFEM N2 Purge: During the wafer process-ing, the FOUP is purged with N2 on a specific N2 EFEM.

Lot Split: Before the critical step, 25 waferlots are divided in different lots (fewerwafers in the FOUP, less outgassing).

Vacuum Purge: This innovative solution hasbeen introduced and patented by adixen

Vacuum Products, by Pfeiffer Vacuum, and has demonstrated yield enhancement.After loading the chamber with a FOUPcontaining wafers, the pressure in thechamber is reduced to < 0.1 mbar. Then thedecontamination process is applied andcontamination is removed. After this, thechamber is purged with clean nitrogen and returned to atmospheric pressure. Thewafers and FOUP are now protected fromcontamination and Qtime can be extendedto one day.

Table 1, based on various experiments,[7-10] describes impact on [AMC] and Stfor each solution:

Currently, almost all advanced fabs areusing at least one of these solutions, andmost of them are using several, dependingon the process steps. GLOBALFOUNDRIESis one of the leaders in AMC managementin the semiconductor industry.

ConclusionThe control of AMCs in FOUPs has

become a major stake to ensure an opti-mum yield. ITRS and end-users are lookingfor better AMC control inside FOUP. Thispaper has shown the importance of con-

Yield Enhancement Through Airborne Molecular Contamination Management

Solutions [AMC] St Solutions Global Evaluation

Qtime 0 + • Need process tool investments

• Increase production complexity

FOUP change during process + 0 • No action on wafer outgassing

FOUP N2 purge + 0 • Need continuous N2 purging to be efficient

EFEM N2 purge + - 0 • Need to be coupled with N2 purge during storage to be efficent

Lot split + Qtime + - + • Need process tool investments

• Increase production complexity

{FOUP + wafer} Vacuum purge + + 0 • One action to suppress both FOUP & wafer outgassing issues • Yield enhancement

Table 1. Evaluation of Solutions

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0

5

10

15

20

25

30

0 50 100 150 200 250 300

Ac

idic

co

nc

en

tra

tio

n p

pb

v

minutes

after process 1

after process 2

after process 3

Figure 5. Example of Acidic Concentration Evolution During Storage After 3 Different Process Steps

0

500

1000

1500

2000

2500

3000

0 50 100 150 200 250 300

Do

se

minutes

after process 1

after process 2

after process 3

DOSE lim

tmax3 tmax2

Figure 6. DOSE Accumulation After 3 Different Processes


67www.future-fab.com |66 | FUTURE FAB International | Issue 43 67

cepts like DOSE and DOSElim to define the right solution to AMC yield issues.Evaluation of the various solutions hasbeen presented.

Moreover, as new materials will be usedin production for the next-generationnodes, DOSElim should become so restric-tive that alternatives to atmospheric-pres-sure transport between critical processeswould need to be investigated.

Endnotes1. T.Q. Nguyen et al. “Identification and

quantification of FOUP molecular con-taminants inducing defects in integrat-ed circuits manufactuing,” Microelec-tronic Engineering (2012)

2. H. Fontaine et al. “Impact of the volatileacid contaminants on Cu interconnectselectrical performances,” ECS Trans-actions, vol. 25 (5), pp. 79-86 (2009)

3. International Technology Roadmap forSemiconductors (ITRS), Yield Enhance-ment, 2011, www.itrs.net

4. H. Fontaine et al. “Study of the volatileorganic contaminants absorption andtheir reversible outgassing by FOUPs,”Solid State Phenomena, vols. 145-146,pp. 143-146 (2009)

5. H. Fontaine and M. Veillerot, “Plasticcontainers contamination by volatileacids: accumulation, release and trans-fer to Cu-surfaces during wafers stor-age,” Solid State Phenomena, vol. 134,pp. 251-254 (2008)

6. P. Gonzáles et al. “FOUPs PolymersAgainst AMCs: The HF Case,” FutureFab international, issue 42

7. T. Kamoshima et al. “Ambient GasControl in Slot-to-Slot Space insideFOUP to Suppress Cu-Loss after DualDamascene Patterning,” ISSM 2007

8. A. Favre et al. “Yield enhancementthrough new solutions for queue timecontainment,” ISSM 2008

9. S. André et al. “Yield EnhancementUsing New Solutions for Queue TimeContainment,” ARCSIS 2008

10. C. Martin et al. “Metal corrosion, what isthe solution?,” ARCSIS 2007

About the Authors

Arnaud Favre – Head of the R&D depart-ment of Advanced Systems, adixenVacuum Products

Julien Bounouar – Process Manager, adixen Vacuum Products

Emmanuelle Véran – SemiconductorMarket Manager, adixen Vacuum Products

Astrid Gettel – Project Leader, FactoryAutomation Tech Development depart-ment, GLOBALFOUNDRIES

Marco Ackermann – Principal ETCHProcess Engineer, GLOBALFOUNDRIES �


Yield Enhancement Through Airborne Molecular Contamination Management

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Wafers susceptible to particle andresidue contamination necessitate special-ized chemical mixtures to clean and etchthem during the manufacturing process.Organic amine-based solvent strippers arerequired for removal of etch residue, oftenfollowed by chemicals such as isopropylalcohol (IPA) and/or deionized water toclean off the original chemical. “Wet” pro-cessing equipment contains multiple tanksin sequence filled with these chemicals.They must be frequently dumped to wasteand replenished to keep contaminates frombeing redeposited onto wafers. Chemicaluse is therefore one of the higher costs inwafer production due to the quantity usedand a stringent need for cleanliness.

This article reviews several methods forchemical cost savings in post-metal waferprocessing from bath life extension tochemical point-of-use reuse with emphasison qualifying process change throughinline controls and monitoring. Even withhigh customer requirements to producewafers, reduced costs can be achievedthrough creative and effective techniques.

High Cost of Chemicals in a FabSemiconductor manufacturing com-

mands many processing steps that useselective chemicals as part of its cleaningor etching phases. Aqueous and solvent-

based strippers formulated to removeorganic residues, such as photoresist orpost-dry etch material, are usually foundunder the supplier’s specialty chemicalsection. These solvents are often difficultand expensive to produce and a challengeto dispose of in an environmentally con-scious way without amplifying significantwafer costs. In addition, wafers that gothrough a specialty solvent immersion orspray are regularly followed up with a rinsein IPA. Although not as expensive as thesolvent strippers in terms of liters-for-liters,chipmakers must use higher quantities ofsemiconductor-grade IPA and pay a premi-um for its high purity and cleanliness. Andunlike ethanol or methanol, IPA is generat-ed from fossil fuel, which adds to the envi-ronmental concerns.

The demand for state-of-the-art integrat-ed circuits fuels the need for an increasinglycomplex set of manufacturing rules. How dofabs provide top-quality chips to customerswithout compromising performance orcost? The solution may be as simple asextending a chemical bath life or sending a waste stream somewhere for reuse. This“low hanging fruit” gives the lowest returnon investment (ROI); however, it is a greatsegue into higher-ROI projects.

Keep in mind that even simple andequally effective process changes require

Point-of-Use Chemical ReuseMark Simpson and Allen Page Texas Instruments

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review by a change approval committee.This will be discussed in detail later.

Extending Chemical Bath LifeThe most efficient way to reduce chem-

ical usage is to simply extend the bath life.Imagine it as reprogramming a dishwasherat home to prolong the water used in thewash cycle by reusing it for the rinse cycle.Water usage would be cut in half, but thedishes may not be as effectively cleaned.By the same token, it is easy to calculatethat for every x time added to a bath, yamount of chemicals will be saved, butminimum specifications of removabilityand cleanliness may be affected. Figure 1shows a typical process sequence usingrecirculated tanks. Pumps move solventfrom outer to inner weir of each tankthrough a filter. Solvents are frequentlydumped to drain and then refreshed tocontinue in its strength and to keep the filter from overloading with contaminates.

Bath life is determined by many factors:how quickly loaded the filter becomes witheach run, concentration changes over timeand/or loss of chemical integrity in effec-

tive cleaning and particle removal. Bathsare automatically dumped as programmedby the engineer at either time-based or-run based intervals. Extending the initialIPA rinse and doubling the amount ofwafers processed is one low-cost solutionto stretch the amount of runs betweenchemical changes. No associated hardwaremodifications or re-plumbing and reroutingof piping are necessary. Only a recipe orparameter change is needed.

Waste Stream RecycleDiverting spent water or chemicals

for reuse elsewhere is not a new concept.Manufacturers routinely plumb drain waterfrom wet hoods to the industrial waste-water system to aid in dilution of acidwaste. Reuse of water is utilized in non-critical applications like HVAC cooling tow-ers. Using the dishwasher analogy, imaginererouting its drain to water the grass out-side. Solvent waste comprised mostly IPAis usually collected and periodically emp-tied into a tanker truck for disposal. Ifwater content is low enough, the wastecan be recycled as fuel or for other appli-

Figure 1. Typical Post-Metal Process Sequence Using Recirculated Tanks

Point-of-Use Chemical Reuse FRONT END OF LINE

cations by extracting the specific com-pounds needed for reuse. In certain cases,the waste solvent is actually purchasedand the company avoids disposal costs.Special internal equipment programming is needed to divert drains to different out-puts based on liquid type, cleanliness orconcentration. Re-plumbing of drain linesoutside the tool is necessary, but thechange is downstream and has no effecton the process itself.

Concentration ReplenishmentThere are numerous chemistries that

lose concentration over time due to evapo-ration, process drag-out, tank level replen-ishment or chemical reaction. Often, equip-ment is set up to bypass this problem byreplenishing extra chemicals at a certainrate in order to extend bath life. It is com-mon practice to add hydrogen peroxideinto a hot sulfuric-peroxide mixture prior

to wafer entry in a post-ash clean bath.Similarly, water-based solvent chemicalsused in post-metal processes, which alsooperate in heated tanks, can have waterreplenished to remove polymers fromwafers effectively. Concentration of waterwithin the solvent is critical, and the evap-oration rate of the water due to elevatedtemperatures limits its useful life. One solu-tion is to determine water evaporation rateof a solvent over time. Then, deploy anintegrated flow controller-metering valveto add de-ionized water back into the bathat the same rate of evaporation. An in-linechemical analyzer, like the WetSpec 200TM

(manufactured by CI-Semi Inc.), measureswater concentration every two to threeminutes and can provide feedback to themetering valve.[1] This method allows for a 600 percent increase in the life of thebath, which transformed into an enor-mous reduction in cost and solvent supply

Figure 2. Bath Life Extension, Stripper Replenishment, Drain Reclaim and IPA Reuse



reduction.[2] Chemical concentration con-trol can be challenging. There are risksassociated with building a replenishmentsystem into a process where solvent-to-water ratio is key: Too much water cancause corrosion of metal, and too little cancause ineffective polymer removal. In-linecontrols are crucial to ensure reliability andrepeatability.

Point-of-Use Chemical ReuseEach of the chemical cost-saving meth-

ods discussed thus far is relatively low riskand industry proven. In spite of extendingbath life, much IPA is still consumed inpost-metal processes. Because thesequence of carry-over from the solventstripper bath makes the second in-line IPAbath cleaner than the first, connecting pip-ing from the second bath to the first allowsreuse of IPA at the point-of-use. By attach-ing I/O signals from the process tool to aprogrammable logic controller (PLC), engi-neers can control valves and pumps sothat the IPA transfers from the secondbath to the first at the start of its fill cycle.

Revisiting the dishwasher example, cleanerwater used in the rinse cycle can be savedfor reuse in the wash cycle of the next loadof dishes. This passive system only per-forms the transfer when the signal of themain tool starts to drain the first bath. Thiswould reduce the amount of IPA chemicalchanges by half for a two- tank process –only one tank changes out. Even more savings can be yielded than the extendedbath life scenario where eventually bothtanks still dump. Reusing IPA at its point-of-use eliminates the need for any specialstorage system. Figure 2 shows the over-all modifications that can be utilized forchemical cost savings on a single piece of equipment and the sequence of eventsduring IPA transfers. The PLC utilizes atouch screen that features different areasto look at, such as overall piping and valvestatus, I/O signals and alarm conditions(Figure 3).

Qualifying the Process ChangeEven simple process changes, such as

chemical reduction methods, require qual-ification. Knowing the five steps to pro-posing change is essential: 1. Proof of Concept – Prove the concept

will work for any process changethrough initial testing. This can includeanalysis of liquid samples for process of record (POR) versus new processes.Take Texas Instruments’ life extension/replenishment project (Figure 4). Com-position of the bath remains stable after12 hours and up to 78 hours. Particlechecks may also be utilized to prove the new process is as clean as POR.

2. Initial Presentation for Change – Presentdata outlining the concept to a changereview board for initial approval. Includethe number and variation of split waferlots.

Point-of-Use Chemical Reuse FRONT END OF LINE

Figure 3. Engineers monitor piping and valve status, I/O signals and alarm conditions throughtouch screens.

3. Split Lot Results – Present the resultsfor the new process versus baseline, orPOR. This often includes in-line defect,parametric and probe data. These testsneed to be statistically equivalent andin specification. A limited release maythen be granted.

4. Limited Release – Run a predeterminednumber of lots using the new process.Once these are completed, the confi-guration is returned to POR, awaitingresults. Compile in-line defect, paramet-ric and probe data again, and comparethe limited release lots to POR lots forverification of sameness.

5. Full Final Release – Show all data to thefinal change review board. If the changeis considered equivalent or improved

over POR, then it will be granted fullfinal release, and equipment may thenbe modified for the change. Specifi-cations may have to be updated andpersonnel trained. Once the change is fully implemented, it is tracked for cost savings, improved probe data and improved throughput.

SummaryFabs are conscious of the need to pro-

vide top-quality chips to customers whoimpose rigorous standards of performancewhile holding down costs in order to turn a profit. The ongoing price increase fordepleting raw materials demands thatengineers change the way they think. Fromsimple changes in chemical bath life to

Figure 4. Initial Data Collection for a Change in Process Proposal


METROLOGY, INSPECTION & FAILURE ANALYSIS


Cost-effective manufacturing is criti-cally dependent upon the development of defect detection, defect review and classification technologies. The 2011 ITRSRoadmap Yield Enhancement chapterpoints out that it is a challenge to detectmultiple killer defects and to differentiatethem simultaneously at high capture rates,low cost of ownership and high throughput.Multi-component architectures such as inhigh-end microprocessors and graphic

processors are becoming more common,and their corresponding kill ratios thusbecome more difficult to estimate.

Garry Tuohy of GLOBALFOUNDRIES has put together an elegant method of calculating kill ratios and loss estimates for manufacturing defects that utilizes thediscrete component results. The methodsshould generally be applicable when quan-tifying the defect-generated yield loss perwafer inspection step.

David G. SeilerChief, Semiconductor and Dimensional Metrology Division, NIST

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more involved equipment reconfigurationsto recycle its resources at its point-of-use,manufacturers must take a discerning look at its processes and develop creativemethods for cost reduction while main-taining process integrity.

References1. M. Simpson et al. “Monitoring recircu-

lated baths using NIR inline chemicalanalysis,” Solid State Technology, pp. 44-46, October 2007

2. M. Simpson et al. “Achieving closed-loop process control of DI-Waterreplenishment,” pp. 77-84, MicroMagazine, July 2004

About the Authors

Mark SimpsonMark Simpson, TMG member of theTechnical Staff, joined Texas Instruments in 2000 and currently holds a position assenior engineer in the Plasma Etch groupat DMOS5 in Dallas. He received his B.S. in EET from Texas A&M University in 1987.

Allen PageAllen Page joined Texas Instruments in 2007and currently holds a position as SeniorEngineer in the Plasma Etch group in DMOS5in Dallas. He received his B.S. in math andphysics from East Central University in 1977and his M.S. in instrumentation from theUniversity of Arkansas in 1981. �


Point-of-Use Chemical Reuse

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METROLOGY, INSPECTION & FAILURE ANALYSIS METROLOGY, INSPECTION & FAILURE ANALYSIS

AbstractThe advent of multi-component devices

has served to slow the reduction in diesize. Relying on die-level contingencyanalysis to determine kill ratios for ever-shrinking design rules is no longer ade-quate. A means of utilizing the data fromdie components is necessary in order topreserve kill ratio accuracy. The applicationof a yield model is presented as a meansof utilizing component-level data for killratio calculation.

IntroductionThe progress to multi-component archi-

tectures in high-end microprocessors andgraphic processors has been well underway for the past decade. Leading-edgemicroprocessors are now very heteroge-neous in nature, containing a wide range of discrete component types (e.g.,NorthBridge, PCIe, Display Port).

More recently, this trend has alsoappeared in general purpose microproces-sors and even microcontrollers. This indi-cates that a method of calculating killratios and loss estimates for manufacturingdefects that utilizes the discrete compo-nent results should now be more generallyapplicable when attempting to quantifythe defect-generated yield loss per waferinspection step.

The ChallengeThe primary difficulty with utilizing

component-level SORT data when calcu-lating kill ratios are those die affected by a gross defect or a peripheral defect, bothof which can result in the loss of compo-nent-level data.

In the case of the examples shown inFigure 1, the components of the middle die cannot be treated independently, butrather need to be considered as a singledie-level failure.

To illustrate the issues associated withdie-level fails, consider the synthesizedwafer maps in Figure 2. The yield differ-ence between the defective die (Yd) andnon-defective die (Yc) is traditionallyused to calculate the kill ratio accordingto equation (1). This results in a kill ratioestimate of 9.2 percent. Performing thesame calculation at the component levelbut treating die-level fails as single ele-ments results in a kill ratio estimate of17.4 percent.

(1)

The accuracy and selectivity of thedie-level correlation is clearly under sus-picion because of the relatively large diesize. However, the component-level calcu-lation is also questionable because the

Calculating Kill Ratios onMulti-Component Devices

defective components include a higherproportion of die-level fails (Figure 2c).The larger area of the die-level fails natu-rally have a higher probability of beingdefective than a true component andhence adversely influencing the kill ratio.This higher probability needs to be fac-tored into the component-level yield val-ues prior to calculating a component-level kill ratio.

The Impact of Component Area on Defectivity

Examining the difference in the proba-bility of die elements being defective fortypical die and component sizes over therange of wafer defectivity values pro-duces the response shown in Figure 3.Unsurprisingly, at low defectivity levels(i.e., <20 defects/wafer), the difference inthe probability of being defective between

Garry Tuohy GLOBALFOUNDRIES Inc.

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Figure 2. Artificially generated wafer maps showing (a) a defect density map and SORT maps highlighting (b) the defective die and (c) defective components plus defective die-level fails.

Figure 1. Example of 3 Die With a Defect-Generated Die-Level Fail on the Middle Die




a die and component is low and wouldonly marginally affect the kill ratios. Be-yond this defectivity level, the difference in the probability becomes unacceptable,as it will increasingly put any die-level failsinto the defective category, thus erro-neously increasing the kill ratio.

A Solution: Area CorrectionOne method of resolving this issue is

to use a yield model to translate the yieldvalues for the defective and non-defectivecomponents to the equivalent yield for die elements of the size of a typical com-ponent. This yield conversion is performedaccording to equation (2), which is derivedfrom the negative binomial equation asfirst proposed by Okabe, et al[1], Stap-per[2] and later comprehensively validatedby Stapper et al.[3]

These calculations are performed forthe defective and non-defective die ele-

ments at every wafer step, where the clus-tering factor (α) as defined by equation (3) is obtained from the inspection scanwhere λ− and σ2 are the mean and variancefor the number of defects per die, asdescribed by Cunningham.[4] The actualcomponent area is represented by Ac andthe average area and yield of the waferelements under investigation are repre-sented by Ai and Yi, respectively.

(2)

(3)

Applying equation (2) to the examplewafer results in the yield conversions asshown in Table 1. The area-correctedyields result in a kill ratio of 4.6 percent.This is in line with the expected value forthe primary defect mechanism at the

inspection step in question, and indi-cates that the area-correction methoddoes allow the component-level data tobe utilized as a more precise assessmentof kill ratios, for individual wafer inspec-tion steps.

Calculating Loss FromComponent-Level Kill Ratios

Estimating the number of die lost fromthe component-level kill ratio requires adifferent treatment than that normallyused by the die-level calculation. Themethod utilized is the same as that to esti-mate loss for die with a given number ofdefects where the kill potential per defectis known. In this case, instead of defects,the number of defective components perdie is used. The number of lost die is givenby equation (4).

(4)

Special consideration needs to be givenfor defect signatures that show a highdegree of selectivity for complete die-levelfails (i.e., high defect kill potential, Kc>80 percent) and that have no clustering (i.e., clustering factor >10). In such cases, the average area of the defective unitsapproaches that of the die area, and theabsence of any clustering means that nokill-ratio scaling occurs because there arerelatively few defective components perdie. This results in the component-levelloss estimate that significantly underesti-mates the loss that is accurately estimatedby the die-level calculation. The die-levelloss estimate should be used when thesecharacteristics are observed.

Component-Type Specific Kill Ratios

Naturally, once the data for all compo-nents have been combined to produce an

Calculating Kill Ratios on Multi-Component Devices METROLOGY, INSPECTION & FAILURE ANALYSIS

Figure 3. Probability of Die or Components Being Defective vs. Defects/Wafer

Figure 4. Visualization of specific component-type’s yield response vs. the number of defects per com-ponent (a) including A-type component redundancy repair [2.7% per defect, rising to 12.9% for all A-types]; and (b) excluding redundancy [12.7% per defect, rising to 29.1% for all A-types]

Yi [%] Yo [%]

Defective Elements 76 87

Non-Defective Elements 92 94

Table 1. Defective and Non-defective YieldsBefore (Yi) and After (Yo) Area Correction


WAFER FAB & PACKAGING INTEGRATIONClick here to return to Table of Contents

Cu-to-Cu Thermo-compressionBonding: The Reliability Challenge of TSV Integration

Higher IC density, reduced cost,improved electrical performance and high-reliability expectations have imposed sig-nificant challenges on the integration flowsof TSV. As in most cases, the simplest wayof forming a reliable interconnect bringsthe highest level of uncertainty and theneed for profound fundamental studies.

This is the case with Cu-to-Cu thermo-compression bonding in TSV. From the verybeginning of TSV development, the simplethermo-compression bonding of Cu hasattracted numerous research groups, uni-versities and companies. Data have beenreported at different conferences from aslow as room temperature bonding to ashigh as 600 °C. The bulk of data, though,comes from the 200-400 °C range, alwaysaccompanied with some form of a propri-etary surface pre-treatment process of theCu metal interface. These can be either wet(acidic rinse) or plasma (hydrogen) clean,pre-sputter Ar-etch or some form of organ-ic protective layers. Usually a post-bondingannealing step is also required to further

Christo BojkovSenior Package Development Engineer, TriQuint Semiconductor

improve the crystalline structure at theinterface. Preserving Cu-interface from oxi-dation and contaminations prior to bondingis a well-established process in the Cu-damascene flow, especially after the CMPstep, but the need for physical bonding has necessitated applying pressure and therequirement for metallurgical connectionbetween the two bulk Cu phases. In oneexample, engineers from EVG have shownthat uniform crystalline structure must beformed between the two bulk phases, thussecuring homogeneous and defect-freemetallurgical connection. A similar conc-lusion has been reached by a team fromimec (Belgium) developing the so-called“Insertion Cu-Cu bonding.”

In this section, you will find anotherexcellent example, from the Institute ofMicroelectronics (A*STAR) and NanyangTechnological University (Singapore) aimedat establishing high-reliability of the Cu-to-Cu bonding interface. This study is veryattractive in providing a correlation ofresults from temperature cycling with con-tact resistance at the interface along withthe thermo-mechanical stresses profilesdeveloped at the TSV bottom section.Looking forward to their next article.

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overall kill ratio for a wafer inspection step,the following questions arise: What are the kill ratios for the individual compo-nent types? Do they display differing yieldresponses? Displaying the yield responseversus the number of defects per compo-nent is best visualized by translating theyields into D0 values.

The shaded blue areas in Figure 4depict the expected response of thelargest component type (i.e., the A-typecomponent) if the yield relationshipbetween the non-defective A-type com-ponents and those with a single defect ismaintained over an extended range ofdefect density.

A monotonic response indicates a clearyield impact attributable to the relevantdefects and lends certainty to the modeledkill ratio. The average component-level killratio for all component types should normal-ly be within a range defined by the largestcomponent type, from the kill ratio for com-ponents with a single defect to the averagevalue for all A-type components. Any unex-plained divergence would indicate the pres-ence of an atypical failure mechanism.

ConclusionThe application of the negative bino-

mial model has been demonstrated toallow component-level SORT data to beutilized for more precise kill-ratio calcula-tion and subsequently yield loss assess-ment when quantifying the defect-assigna-ble loss on a wafer inspection step basis.

Plotting of D0 for each component typeversus the number of defects per com-ponent can illustrate differences in theresponse of different component types toincreasing defectivity for specific waferinspections scans and serve to increase theconfidence in the aggregated component-level kill ratios.

References1. Okabe et al. “Analysis on Yield of

Integrated Circuits and a NewExpression for the Yield,” Elec. Eng.,Japan, vol. 92, pp 135-141, December1972.

2. Stapper, C.H., “Defect Density Distri-bution for LSI Yield Calculations,”IEEE Trans. on Electron Devices,” vol.20, No. 7: pp 655-657, July 1973.

3. Stapper, C.H. et al. “Integrated CircuitYield Statistics,” Proc. of the IEEE, vol.71, No. 4: pp 453-470, April 1983.

4. Cunningham, J.A. “The Use andEvaluation of Yield Models in IntegratedCircuit Manufacturing,” IEEE Trans. onSemiconductor Manufacturing, vol. 3,No. 2: pp 60-71, May 1990.

About the Author

Garry Tuohy Garry Tuohy received his B.Sc. degree

in applied physics from the University ofSalford, Greater Manchester, U.K., in 1994. Hehas worked in the semiconductor industrysince 1996, mostly in the U.K. and Germany.Since 2003, he has been working in yieldengineering in Dresden, Germany, for AMDand now GLOBALFOUNDRIES, where he is a member of the technical staff. His work primarily involves developing systems for kill ratio and defect loss analysis, and web-reporting. �


Calculating Kill Ratios on Multi-Component Devices

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WAFER FAB & PACKAGING INTEGRATION WAFER FAB & PACKAGING INTEGRATION

AbstractThe Cu-Cu thermo-compression bond-

ing process being compatible with 3D inte-gration is important since all aspects of theFEOL, TSV, BEOL, back-side metalizationand assembly processes need to be con-sidered. Bonding temperature and forceare critical parameters during Cu-Cu bond-ing. A high bonding temperature induceshigh TSV stress in the Si substrate; mean-while, high contact resistance and its instability are observed when the bonding temperature is <300 °C, according to ourstudy. Therefore, bonding temperature of300 °C is suggested for Cu-Cu bondingand applied for 3D-IC stacking.

IntroductionCu-Cu thermo-compression bonding

is a promising technology for 3D waferstacking. Reports on Cu-Cu thermo-com-pression bonding have attracted signifi-cant attention.[1-3] Specifically, electrical

and reliability results of 200 °C directbonding were reported by Di Cioccio et al.[3] Cu-Cu thermo-compression bond-ing is critical technology to address the

An Optimal Cu-to-CuThermo-compressionBonding Process WindowCompatible With 3D WaferStacking and Stability

bonding condition is known to affect thekeep-out-zone (KOZ) between TSV anddevices around.[7] Thus, the bonding tem-perature has been identified as the primarycontributor to the buildup of TSV thermalstress compared with bonding pressure.[7]Therefore, Cu-Cu thermo-compressionbonding temperature is an importantparameter to be considered in the contextof 3D process integration.

Bonding Conditions and Effects on Embedded TSV

High bonding force and temperatureare required to ensure the bonding qualityand site-to-site uniformity. However, thebonding temperature and force are loadedon Cu-TSV as well. As a result, TSV gener-ates thermal stress in Si substrate duringbonding process. The thermal stress pres-

H.Y. Li,1 L. Peng,1,2 F.X. Che,1 C.S. Tan,2 G.Q. Lo1

1Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore 2Nanyang Technological University, Singapore

ever-scaling requirement of the bumppitch in order to increase the bump densi-ty. The important applications of Cu-Cubonding include direct Cu-TSV bondingwith Cu-pad to form 3D interconnect.[4-7]However, high-temperature Cu-Cu bond-ing during 3D wafer stacking can reducenegative impact on the process integra-tion; for instance, with temporary bondingresulting in de-bonding during the back-side CVD, PVD and metalization.

Cu-Cu bonding conditions are criticalfor the devices with Cu-TSV in via-middle(VM) implementation. Cu-Cu bonding isperformed after devices and Cu-TSV fabri-cation. Therefore, bonding temperatureand pressure are applied on the Cu-TSVand active device as well. Thermal stressfrom TSV affects the active device in thenearby surrounding Si significantly. The

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Figure 1. Thermal-stress Distribution When Heatand Pressure Are Applied and Hold at HighBonding Temperature

Materials CTE(ppm/°C)

Young’sModulus (GPa)

Poisson’sRatio

Silicon 2.8 131 0.28

Cu 17 117 0.35

Table 1. Parameters Used in Thermal StressSimulation

0

100

200

300

400

500

600

Ramp up to high temp

Apply pressure

High temp dwell

Remove pressure

Down to RT

Top wafer thinning

Sili

con

stre

ss S

1 (M

Pa)

Cu_Cu Bonding at 60 kN Bonding Force

200 °C

250 °C

300 °C

350 °C

Figure 2. Simulation Results of Cu-Cu Bonding at 60 kN for 1 Hour Held at Different Temperatures




ents challenges during subsequent waferprocesses such as back-grinding and TSVvia reveal. Therefore, simulation of bond-ing force and temperature is necessary toguide the 3D process integration. The ther-mal stress in Cu-TSV (Φ: 5 µm, H: 30 µm)from Cu-Cu thermal-compression bondingis simulated by ANSYS. The simulationconsiders temperature ramp-up, appliedpressure, high temperature dwell, pressureremoval and cooling down to room tem-perature. The major parameters used areshown in Table1.

The maximum stress is concentratedaround the TSV bottom corner area whenheat and pressure are applied and held athigh temperature. The result is illustratedin Figure 1. A second high stress is distrib-

uted in the Si substrate near TSV bottom.When the top bonded wafer was thinneddown to this area by the back-grindingsystem, complicated mechanical stresseasily induced wafer crack. The maximumstress near TSV in Figure 1 is not symmet-ric, which increases the via-revealingprocess challenge.

Extremely high thermo-mechanicalstress could cause the Si substrate tocrack. The stress weak point near the TSVbottom could affect wafer back-side thin-ning and via reveal. A previous study[8]showed that the bonding yield is improvedwith both the bonding force and the tem-perature. Therefore, it is essential to identi-fy and select a Cu-Cu bonding processthat results in the least-TSV-induced ther-

mo-mechanical stress in the Si substrate.The maximum thermo-mechanical stress inthe Si area near the TSV bottom is simulat-ed for Cu-Cu bonding process at 200, 250,300, and 350 °C with 60 kN bondingforce. The maximum stress distributionduring the bonding process is shown inFigure 2.

As shown in Figure 2, the Si-substrate is under high stress when the respectivebonding temperature is applied, which is reduced during the cooling step. Asexpected, a higher bonding temperatureresults in higher stress. However, there is no significant variation in the stressvalue when the bonding pressure isapplied, saturated at high temperature and removed within individual bondingprocess. Therefore, it is clear that thebonding temperature plays a significantrole in the Si substrate stress buildup.

To further understand the role of bond-ing pressure, the simulation is repeated at300 °C for 10, 30 and 60 kN of bondingforce, and the results are shown in Figure3. As can be seen, the maximum Si stresshas no significant dependency on the

bonding force. Again, based on an earlierstudy,[8] the bonding force merelyincreases the contact area to improve the overall bonding quality.

The conclusion drawn from the simula-tion results on the dependency of themaximum Si stress level in response tobonding temperature concurs with the earlier report.[7] One guideline is toreduce the bonding temperature whilemaintaining a reasonable level of bondingforce in order to obtain optimum bondingquality. The next section investigates andidentifies suitable Cu-Cu bonding tempera-ture for 3D process integration.

Impact on Cu-Cu ContactResistance and Its Stability

200 mm Si-(100) wafers with two layers of single damascene Cu are used for wafer-on-wafer face-to-face stacking.Self-assembled monolayer (SAM)[9] iscoated on a Cu bonding pad after a topdielectric recess that reduces the Cu oxi-dation effect. SAM is desorbed before Cu-Cu thermo-compression bonding. A cross-bar Kelvin structure is used to characterize

An Optimal Cu-to-Cu Thermo-compression Bonding Process Window Compatible With 3D Wafer Stacking and Stability WAFER FAB & PACKAGING INTEGRATION

0

100

200

300

400

500

600

Ramp up to high temp

Apply pressure

High temp dwell

Remove pressure

Down to RT Top wafer thinning

Sili

con

stre

ss S

1 (M

Pa)

Cu_Cu Bonding at 300 °C

10 kN

30 kN

60 kN

Figure 3. Simulation Results of Cu-Cu Bonding at 300 °C (1 hour) With Different Bonding Forces Figure 4. (a) Cross-bar Kelvin Structures Schematic; and (b) After Top Si Removal



the effect of bonding temperature on thecontact resistance as shown in Figure 4.This structure can overcome wafer-to-wafer misalignment during contact resist-ance study. The top and bottom metal linewidth is 5 µm.

The bonding process is performed at225, 275 and 300 °C, respectively, with 60 kN bonding force for one hour. The Cu-Cu thermo-compression bonding contactresistance is characterized by a four-pointmeasurement. The contact resistance is ~5, 3.5 and 2.3 mΩ for bonding tempera-ture at 225, 275 and 300 °C, respectively.As clearly shown in Figure 5, lower contact

resistance is achieved when higher bond-ing temperature is applied.

Cu-Cu contact resistance reliability isinvestigated by thermal cycle test (TCT).The sample is subjected to thermalcycling test with the temperature rangingfrom -40 °C to 125 °C. The ramp-up/downrate is ~15 °C/min and each thermal cycleis ~52 min. The Cu-Cu contact resistanceis measured after 200 and 500 thermalcycles. The Cu-Cu contact resistance isconsistent after 200 and 500 cycles ofTCT when bonding is done at 300 °C.However, fluctuation in the contact resist-ance is observed for Cu-Cu contact

bonded at 225 °C and 275 °C after TCT.Therefore, 300 °C is selected as the Cu-Cu thermo-compression bonding temper-ature in our bonding study. This bondingtemperature can provide stable contactresistance.

SummaryIn this study, it is noted that when the

bonding temperature is <300 °C, higherresistance and unstable contact resistanceare observed from the thermal cycling test.Meanwhile, increased bonding pressurecan improve bonding yield and quality.[8]Therefore, Cu-Cu bonding temperature at 300 °C is chosen along with 60 kN ofbonding force based on this study. In addi-tion, surface pre-treatment with SAM isapplied to achieve fine-pitch Cu-Cu inter-connects bonding for wafer-on-waferstacking.

References 1. R. Taibi et al. “Investigation of stress

induced voiding and electromigrationphenomena on direct copper bondinginterconnects for 3D integration,” inIEDM Tech. Dig., 2011, pp. 135-138.

2. Y.H. Hu et al. “Cu-Cu Hybrid Bonding as option for 3D IC stacking,” IITC 2012, pp. 1-3.

3. L. Di Cioccio et al. “200°C direct bond-ing copper interconnects: electricalresults and reliability,” IEEE 3D SystemsIntegration Conference, 2011, pp. 1-4 (9-8)

4. Y.H. Hu et al. “3D Stacking Using Cu-CuDirect Bonding,” IEEE 3D IC 2011, pp 1-4(1-3).

5. Cedric Huyghebaert et al. “Cu to Cuinterconnect using 3D-TSV and Wafer to Wafer thermo-compression bonding,”IITC 2010, pp. 1-3.

6. W.H. The et al. “Recent Advances inSubmicron Alignment 300mm Copper-

Copper thermocompressive Face–to-Face Wafer-to-Wafer Bonding andIntegrated Infrared, High-Speed FIBMetrology,” IITC 2010, pp. 1-3.

7. Chukwudi Okoro et al. “Analysis of the Induced Stresses in Silicon DuringThermocompression Cu-Cu bonding ofCu-Through-Vias in 3D-SIC Architecture,”IEEE ECTC 2007 pp. 249-255.

8. H.L. Leong et al. “Application of contacttheory to metal-metal bonding of Siliconwafer,” J. Applied Physics 2007 102 p.103510.

9. D.F. Lim et al. “Achieving low tempera-ture Cu to Cu diffusion bonding withself-assembled monolayer (SAM) passi-vation,” IEEE 3DIC, 2009.

About the Authors

H.Y. Li – Scientist, Institute ofMicroelectronics

L. Peng – Ph.D. student, NanyangTechnological University and Institute ofMicroelectronics

F.X. Che – Scientist, Institute ofMicroelectronics

C.S. Tan – Assistant Professor, NanyangTechnological University

G.Q. Lo – Deputy Executive Director,Institute of Microelectronics �


An Optimal Cu-to-Cu Thermo-compression Bonding Process Window Compatible With 3D Wafer Stacking and Stability AWAFER FAB & PACKAGING INTEGRATION

1

2

3

4

5

6

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ntac

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tanc

e (m

-Ohm

)

225

225 (200)

225 (500)

275

275 (200)

275 (500)

300

300 (200)

300 (500)

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With the current 2.5D and 3D tech-nologies, multi-functional die systems areconfined in a single package with fewinput/output (IO) going to the externalprinted circuit board (PCB) motherboard.In particular, the die-to-die (e.g., logic tomemory read and write operations) inter-faces can’t be probed with normal “intru-sive” test probes.

It is then necessary to review the testingmethodology to qualify 2.5D/3D systemsduring pilot test, and verify the properfunctionality of the different blocks withinthe system prior to and during operationson a larger PCB motherboard.

A set of existing chip-embedded testingstrategies can be used for such “closed”systems such as boundary scan testing andbuilt-in self test (BIST). Yet more advanced“chip embedded instrumentation” intellec-tual properties (IPs), mimicking laboratory

Surya Bhattacharya Director, Industry Development; IME

equipment test boxes (e.g., logic scope orbit error rate tester) inside the dies undertest (DUT) need to be developed as well.Those “chip-embedded instrumentation”IPs could be implemented as hard IP macroor soft IP macro and accessed through aJTAG interface from the PCB motherboard.

Currently, IME researchers (with theirindustrial partners) are developing a fieldprogrammable gate array (FPGA) with 3D-DRAM 2.5D high-performance system thatwill use “chip-embedded instrumentation”soft IPs to test the FPGA to 3D-DRAM wideIO interface.

This FPGA-assisted test technique forwide IO logic to 3D-DRAM systems willenable the proper qualification process forfuture high-performance applications andcould be migrated for an ASIC version of a wide IO-based system in a 2.5D or 3Dconfiguration at very high speed rates.

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Looking for the Panacea of TestThe test of electronic circuits has been a

key topic in the industry since the first tran-sistor was developed, and today it is as rel-evant as ever. Test strategies are graded byhow close they come to the ideal test solu-tion that doesn’t add any cost to the prod-uct under test, either during the design orduring production. Most of us agree thatproduct testing is absolutely necessary, aspart of design validation, as a quality indi-cator for manufacturing process control or for the detection of defective productsprior to shipping them to a customer. How-ever, we do have certain requirements thatshould be met by our test solutions: testdevelopment and execution should be fullyautomated and should be done in essential-ly no time; we want the test equipment tobe very inexpensive; and we want fault cov-erage of 100 percent. Industry trends givecause for concern, though, considering thatthe cost of test today can be a significantpart of the overall development and manu-facturing cost.

Responsible for this development areprimarily the complexity, high-speeddesigns and the lack of available test

access of many of today’s printed circuitboard assemblies (PCBAs), or boards, forshort. The combined forces of these char-acteristics result in systematic changes inthe balance of product design and producttest. We start to see a correlation betweenproblems seen in chip test and those seenin board test.

While boards look more like integratedcircuits (IC) due to the loss of access tointernal circuit nodes, the rapid develop-ment of three-dimensional (3D) ICs withmulti-die integration results in structuresthat are similar to boards and systems.The 3D board with very little physicalaccess seems to be looming on the hori-zon. At the same time, the combination ofnew packaging and integration technolo-gies result in hitherto-unaccustomed com-plexity. While several years ago, multipleboards were necessary to create completesystem designs, today some such systemscan be realized in IC as system-on chip(SOC) or system-in package (SIP) designs.As a result, board size can be minimizedand new possibilities are available to cre-ate super-complex systems. No matterhow a design is arranged, however, from

Embedded System Access:Changing the Paradigm ofElectrical TestThomas Wenzel, Heiko EhrenbergGÖPEL electronic GmbH

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The brilliance of IEEE Std 1149.1 is theopen expandability of its register architec-ture combined with the universal test businterface (test access port, TAP) and itsprotocol definition. These propertiesallowed IEEE Std 1149.1 to become thebase technology for new non-intrusivemethodologies and standards for testing,debugging, programming and emulation.As a result, the portfolio of test accessstrategies at the board level has definitive-ly changed.

Today we can differentiate three princi-ple classes of access strategies (Figure 1):• Native connector access (access

through design-integrated I/O inter-faces)

• Intrusive board access (access throughphysical test nails and probes)

• Embedded system access (accessthrough design-integrated test bus)

the perspective of test engineering, thefundamental questions are: 1) How suchhighly complex systems can be testedappropriately and efficiently; and 2) Howone can take advantage of synergiesbetween chip test and board testapproaches?

Non-invasive Test Access?Partitioning circuit structures into

testable elements is a prerequisite for asuccessful test strategy. This is one of thereasons why in-circuit test (ICT) becameso successful for board-level tests. ICTapproached circuit test structurally andtests components individually; however,the required bed-of-nail-based invasivetest access is becoming a big dilemmawith modern boards. Test access problemswere predictable, which resulted in the creation of IEEE Std 1149.1 in 1990.

Figure 1. Classification of Electrical Test Access Strategies at Board Level

Embedded System Access: Changing the Paradigm of Electrical Test ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

While these classes are not mutuallyexclusive in their practical utilization, theapplicability of an actual combination ofthese access strategies depends on theindividual capabilities of the chosen auto-mated test equipment (ATE) platform.

So, how do these access strategiesrelate to each other, and what does embed-ded system access mean practically?

Paradigm Change: A New Era?A look at the qualitative development

of trends for the various access strate-gies reveals interesting facts, including along adoption period of IEEE Std 1149.1as the first representative for embeddedsystem access. The accelerated adoptionof embedded system access in the mar-ket is primarily due to the fact that it isnow a class by itself, comprising a varietyof non-invasive access technologies,including:

• Boundary-scan test (IEEE Std 1149.1/.4/.6/.7)

• Processor-emulation test • Chip-embedded instrumentation

(IJTAG, IEEE P1687)• In-system programming • Core-assisted programming • FPGA-assisted test• FPGA-assisted programming • System JTAG (SJTAG)

The electrical access embedded in thetarget system allows embedded systemaccess to work without invasive test nailsand probes. In principle, every ESA technolo-gy utilizes a task-specific pin-electronic thatis controlled by the test bus and, as a result,can directly execute test functions and pro-gramming routines in the target system. Thistarget system can be an individual chip, aboard or a complete system assembly;embedded system access can be utilizedthroughout the entire product life cycle.

Property Boundary Scan Test Processor Emulation Test

Chip-Embedded Instruments FPGA-Assisted Test

Test type structural functional open* open*

Test speed static dynamic open* open*

Access through Boundary-Scan IC processor IJTAG-IC FPGA

Pin-electronics Boundary-Scan-Register

system bus IP-Interface IP-Interface

Configurable IP** no no open* yes

Fault coverage static dynamic open* open*

Level of diagnostics pin net/pin open* open*

Related IEEE standard IEEE Std 1149.x

IEEE Std 1149.7/ ISTO 5001

IEEE Std 1149.1,IEEE Std 1149.7,

IEEE P1687

IEEE Std 1149.1,IEEE Std 1149.7,

IEEE P1687

* Depending on the implementation ** Intellectual property

Table 1. Comparing ESA Technologies Relevant to Board-Level Test



Embedded System Access: A Portfolio of ComplementaryTechnologies

A detailed analysis of key ESA tech-nologies at the board level reveals con-siderable differences in operation andgoals.

Table 1 reflects the complementarycharacter of the various technologiesand, as the following discussion will further explain, it becomes clear howimportant it is for ATE platforms to sup-port all these ESA technologies alike.

Boundary Scan utilizes so-calledboundary-scan cells, combined into aboundary-scan register, as primary accesspoints for a target system’s circuit nodes.The boundary-scan register is accessedand controlled through the test accessport (TAP). All vectors are scanned serially.

However, since boundary-scan tests arestatic in nature, dynamic defects usuallycannot be detected, let alone be diag-nosed. In addition to IEEE Std 1149.1, vari-ous related standards have been createdor are in development.


Figure 2. Principle of Processor Emulation Test (PET)Figure 3. a) Programming flash memory per FPGA-assisted programming; b) Embedded test bus controller at board level



Processor Emulation Test (PET) utilizesthe debug interface to transform theprocessor core temporarily into a nativetest controller (Figure 2). The processorand its system bus interface become thepin-electronics used as access points forthe connected circuitry in the target sys-tems. Remote-controlled through the JTAGinterface or some other debug interface,the processor core utilizes write and readaccess to the system bus with respectivetest vectors in order to manipulate andtest the connected internal and externalresources and components.

Chip-embedded Instruments are testand measurement intellectual property (IP)blocks integrated into ICs, often accessible

through the JTAG port. The functionality ofchip-embedded instruments is completelyopen and ranges from simple sensors overcomplex signal processing and data col-lection all the way to complete analysisinstruments and programming engines.The IP is either integrated permanently inthe chip (hard-macro), or it can be tem-porarily instantiated and configured (soft-macro) in field-programmable gate arrays(FPGA). As a result, the pin-electronics areunrestricted in principle and can provide a wide variety of functionality, within theframe and scope of the respective tech-nology of the host device, of course.

In particular, FPGA-embedded instru-ments have enjoyed strong interest recently.


Figure 4. Control of ESA Applications Through External Hardware and Software

By enabling strategies such as FPGA assist-ed test (FAT) and FPGA-AssistedProgramming (FAP), they provide enor-mous flexibility for the adaptation to indi-vidual test and measurement requirements.

Chip-embedded instruments have beenutilized for years in chip test; for example, inthe form of built-in self-test (BIST) IP.However, access to these instruments hasnot been standardized in the past; some-thing that will be changed with the newIEEE P1687 (also known as IJTAG).

In-System Programming (ISP) is a col-lective term for the programming of Flashdevices via boundary scan and for the pro-gramming of PLD/FPGA devices throughtheir TAP and built-in programming regis-ters, while the devices are mounted on theprinted circuit board. For in-system pro-gramming of PLD/FGPA, special standardsexist, such as IEEE Std 1532, JESD-71 andan industrial standard called serial vectorformat (SVF).

The premise of the Core-AssistedProgramming (CAP) strategy is similar toprocessor emulation test. The processor iscontrolled through its native debug inter-face in a way that allows Flash or FPGA(design permitting) connected to the sys-tem bus to be erased, programmed andverified. In the case of Flash, it does notmatter whether it is integrated in theprocessor/micro controller unit (on-chipFlash) or connected as external, discreteFlash device(s). Furthermore, it is possibleto load only the Flash handler/program-ming engine via JTAG into the processorand to download the Flash data imagethrough a high-speed communication inter-face on the processor CAP technology.

One of the most interesting technolo-gies for Flash ISP, referred to as FPGA-Assisted Programming (FAP), is based onFPGA-embedded instruments. The embed-

ded instrument in this case is a program-ming engine (programmer) soft macro,typically provided by a tool vendor andtemporarily downloaded into the FPGA.Depending on the architecture of the pro-grammer IP and the performance of theexternal control system, drastic improve-ments in programming speed compared to boundary-scan based ISP are possible.

The last access technology in this discussion is referred to as System-LevelJTAG. While remote control through anexternal controller is possible, this tech-nique typically employs a central test control unit integrated directly into thesystem design. Test vectors are usuallystored locally on the system and a sepa-rate IC is commonly used as the test buscontroller (although there is also the pos-sibility of integrating the test bus con-troller function in an IC that also performsother functions in the system design). Asthe name implies, this method can beemployed not only for individual boardsbut also for systems comprising multipleboards and modules.

The Transformation to theSystem-integrated Tester

The transition from traditional invasivetest access and techniques to embeddedsystem access is not a marginal change inthe handling of test and programming vectors, but rather a fundamental techno-logical metamorphosis. Characteristics ofthese changes include:• Integration of test electronics in the

system under test• Un-separable coupling of functional

and test circuitry in the system design• Forming of partitioned test centers with

various features• Significantly wider range of test and

programming strategies


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required flexibility to support any of suchinterfaces; even a mix of different test businterfaces in multi-processor applicationsshould be supported. Furthermore, thevarious ESA technologies must be sup-ported by powerful software tools andmust be made available to the user in intu-itive graphical user interfaces. In this con-text, we need to consider not only theindependent use of individual ESA meth-ods, but also the potentially interactiveapplication of various ESA technologies in order to gain extra benefits.

About the Authors

Thomas WenzelThomas Wenzel is co-founder and manag-ing director of GÖPEL electronic GmbH inJena, Germany. He heads the company’sJTAG/Boundary Scan division. As graduateengineer, Thomas worked as a hardwaredesigner with Carl-Zeiss Jena beforefounding GÖPEL electronic in 1991.

Heiko EhrenbergHeiko Ehrenberg is president of GÖPELelectronics LLC in Austin, Texas. Heopened GÖPEL electronic’s subsidiary inthe U.S. Today Heiko works in several IEEEgroups, dealing with future test and pro-gramming standards. �


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• Possible utilization throughout the entireproduct life cycle

• Flexibility of reconfigurable pin-electron-ics with FPGAs

• Availability of completely new instru-mentation platforms

In practice, embedded system accessrepresents in principle a transformationfrom a purely functional design into afunctional design with integrated testcapabilities, a combination of unit undertest and tester, so to speak (Figure 3).

Depending on the actual implementa-tion of embedded system access, a widevariety of applications is possible (Figure4). Currently, FPGA-based test in particularis a technology driver for progressivelymore complex test and measurement func-tions. This includes applications such as:• Voltage measurements• Frequency measurements• Temperature measurements• Bit error rate tests (BERT) for high-

speed signals• Event counters• Logic scopes, etc.

Multidimensional Requirementsfor Tester Instrumentation

So far, we have primarily discussed theJTAG interface as the test bus. However,there are also a number of proprietary bus interfaces used in the industry; in particular, for debug interfaces on proces-sors, such as serial wire debug (SWD), spy-bi-wire (SBW) or background debug mode(BDM). For ATE vendors, this means theirtest bus controllers need to provide the

Embedded System Access: Changing the Paradigm of Electrical Test

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