Cypress FX2LP

2010/03/31

IntroductionUSB EZ-USB FX2LP USB Cypress FX2&FX2LP ) MCU

USB 2.0 EZ-USB (LP LOW POWER

EZ-USB FX2LP EZ-USB FX2LP CPU FX2LP KIT

CPU Endpoint 0 Control Transfers Bulk transactions ( )

EZ-USB FX2LPEZ-USB FX2LP RAM DOWN LOAD FX2LP SIE(Serial Interface Engine) USB FIFO 480Mbps FIFO FIFO CPU

EZ-USB FX2LPSIE(Serial Interface Engine) USB USB

EZ-USB FX2LPFX2LP CPU(EP0) USB CPU FIFO PC

USB

EZ-USB FX2LPFX2LP Logic Block Diagram

EZ-USB FX2LPFX2LP Endpoint RAM3x64bytes (EP0 1) 8x512bytes (EP2 4 6 8)

EZ-USB FX2LPCY7C68013A-128 TQFP

EZ-USB FX2LP CPUFX2LP CPU FX2LP CPU 8051 8051

8051

EZ-USB FX2LP CPU(USART) (TIMER2)

16-Bit 16-Bit 8 WAKEUP

T2

(INT2~INT6 USART1)

EZ-USB FX2LP CPU/ 2 ( RAM MOVX )

USB FIFO/GPIF 115K/230K USART 3 100 400KHz

I2C

EZ-USB FX2LP CPUFX2 USB SETUP 12 I/O 24 C 48MHz CPU SFR SETUP DATA

EZ-USB FX2LP CPUFX2 CPU1. 2. 3. 4. 5. 6. 7. 8. 9.

0xE400~0xFFFF

GPIF

/ USB GPIF/FIFO

FX2LP KITFX2LP KIT CYPRESS SETUP_FX2LP_DVK_1004.exe http://www.cypress.com/?rID=14321CYPRESS

USB

FX2LP KITFX2LP FX2LP FX2LP VID PID .

FX2LP KITDownload load FX2LP

FX2LP KITGet Dev Get Conf Get Pipes Get Strings Download Re-load Lg EEPROM URB Star HOLD RUN / (Endpoint) FX2LP RAM USB I2C USB FX2LP CPU FX2LP CPU EEPROM HOLD RUN

FX2LP KIT

Bulk Trans

FX2LP KIT2 512 0x05 FX2

MAX232

The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface

I2C EEPROM 24LC32 32K

ROM

MAX115 2x4 12Bit ADC 2s Conversion Time per Channel Throughput: 390ksps (1 Channel) 218ksps (2 Channels) 152ksps (3 Channels) 116ksps (4 Channels)

PC 480Mbps CPU FX2 EP0 64Bytes EP1 CPU (FIFO)

FX2LP FIFO

EP2 EP4 EP6 EP8 USB2.0 FIFO CPU

USB1.1

FX2LPFX2LP FX2LP CPU FX2LP EP2 4 6 8 2 3 4

/

FIFO CPU

USB2.0

USB

1.1

2.0

USB1.1 8 8 16 32 16 32 1-64 1-1023 64 64

USB2.0 64 512 1-1024 1-1024

EP2

4 6 8 FX2

CPUEP1OUTCFGB7 VALID R/W 1 B6 0 R 0 B5 TYPE1 R/W 1

EP1INCFG SFRB4 TYPE0 R/W 0 B3 0 0 0 B2 0 0 0 TYPE1 0 0 1 1 B1 0 0 0 TYPE0 0 1 0 1 ( ) b0 0 0 0

Bit 7 VALID Bit 5-4 TYPE1:0

CPUEP2 6 CFGB7 VALID R/W 1 B6 DIR R/W 0/1 B5 TYPE1 R/W 1 B4 TYPE0 R/W 0 B3 SIZE R/W 0 B2 0 R 0 B1 BUF1 R/W 1 b0 BUF0 R/W 0

EP4 EP8 CFGB7 VALID R/W 1 B6 DIR R/W 0/1 B5 TYPE1 R/W 1 B4 TYPE0 R/W 0 B3 0 R 0 B2 0 R 0 B1 0 R 0 b0 0 R 0

CPUVALID1 IN OUT

TYPETYPE1:0 00= 01= 10= 11=

(

)

CPUDIR1=IN 0=OUT

BUF1:0EP2 00= 01= 10= 11= 6

(

)

SIZE0=512 Bytes 1=1024 Bytes

CPU(Buffering) USB CPU USB RAM

FX2LP RAM USB FX2LP USB

FX2LP PC

PC PC

PC

FX2LP

PC PC PC

PC

FX2LP

The Magic Happens

USB FX2 CPU

USB

1. PC

0( )2. USB

(ROM3. PC

) USB USB

4.

PC USB

0( ) 5. USB

6. PC

USB

7. USB

(ROM 8. PC9. PC 10. USB 11.

) USB USB USB (ROM )

PC

111. 2. 3. 4. 5.

0

Endpoint 0 Control TransfersEP0 FX2LP 64 Bytes FX2 (EP0BUF)

Endpoint 0 Control Transfers

Endpoint 0 Control Transfers

Cypress FX2LP USB FX2LP USB USB

Cypress hooks)

(function

C:\Cypress\USB\TargetINC:FX2 LIB:FX2 FW: FX2.H FX2REGS.H EZUSB.LIB FW.C

:1. 2.

USB3. 4.

TD_Init()

SETUP SETUP

0

:1. 2.

:TD_poll()

3.

USB

USB TD_Suspend()

Bulk transactions (PC CPU 28 FX2 220 Bytes EP1 220Bytes

)EP1IN 64Bytes 64 64 64

64 PC

64Bytes EP1INBUF EP1INBC USB 64Bytes IN

Bulk transactions (BULKLOOPEP1OUTCFG = 0xA0; EP1INCFG = 0xA0; SYNCDELAY; EP2CFG = 0xA2; SYNCDELAY; EP4CFG = 0xA0; SYNCDELAY; EP6CFG = 0xE2; SYNCDELAY; EP8CFG = 0xE0; // see TRM section 15.14

)

EP2/4 OUT

EP6/8

IN

EP2468

;10x0 =| PUTESRTPOTUA erutaef retniopotua laud elbane // ;08x0 = LCB4PE ;YALEDCNYS .piks/w tnuoc etyb gnitirw yb TUO4PE mra // ;08x0 = LCB4PE ;YALEDCNYS ;08x0 = LCB2PE ;YALEDCNYS ;08x0 = LCB2PE ;YALEDCNYS .piks/w tnuoc etyb gnitirw yb TUO2PE mra //

Bulk transactions (

AUTOPTRSETUP |= 0x01;OUT EP2 EP4

)

} } TUO2PE )mra(er // ;08x0 = LCB2PE ;YALEDCNYS NI6PE mra // ;LCB2PE = LCB6PE ;YALEDCNYS ;HCB2PE = HCB6PE } ;1TADOTUATXE = 2TADOTUATXE )s(RETNIOPOTUA gnisu reffub NI6PE ot reffub TUO2PE refsnart ot putes // { ) ++i ;tnuoc < i ;0000x0 = i (rof NI6PE ot atad reffub TUO2PE pool // ;LCB2PE + )8