GIGABIT ETHERNET: AN AFFORDABLE SOLUTION

FINAL REPORT

GAURAV ASTHANA

JAMES DENARO GROUP 4

APRIL 23, 2002

ECE 4006C G4

SPRING 2002

GEORGIA INSTITUTE OF TECHNOLOGY

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Background on the evolution of the Gigabit Ethernet Standard As personal computers increasingly become multimedia centers in the home and

office, data transmission over local area networks is increasingly important. The most widely

implemented networking standard at this time is 10 BASE-T Ethernet, capable of transferring

at most 10 megabits/second. To truly transform a LAN into a multimedia center for the

home, faster connections will be needed. Currently, gigabit Ethernet is available as a faster

alternative, transferring at 1000 megabits/second. Unfortunately, faster alone is not enough to

motivate gigabit’s adoption by the market. Current fiber-based gigabit Ethernet cards cost

approximately $300. For most users, any improved networking technology must also cost

roughly the same as the current technology.

The 802.3 Standard

The IEEE Std. 802.3 2000 Edition sets forth parameters for systems embodying carrier

sense multiple access with collision detection (CSMA/CD) access method and an attendant

physical layer. For 1000BASE-X systems, the Physical Medium Dependent (PMD) sublayer

is set forth in section 38.2.1.

The IEEE 802.3 standard completely describes how the transmission and reception of

data must occur. In order to data to be successfully received, certain standards must be met.

Section 38.6.5 of the IEEE Std. 802.3 2000 Edition details the transmitter optical waveform

(transmit eye). The required transmitter pulse shape characteristics are specified in the form

of a mask of the transmitter eye diagram as shown below.

Eye mask. [802.3 pg. 1043]

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To determine if the receiver is in conformance with the 802.3 standard, it is tested

using a known pattern. The conformance test signal must be generated using the short

continuous random test pattern defined in section 36A.5. The conditioned test signal is shown

schematically in the figure below. The horizontal eye closure (reduction of pulse width)

caused by the duty cycle distortion component must be within a certain range. The vertical

eye-closure penalty shall be greater than or equal to the value specified in Table 38-4 for

1000BASE-SX and Table 38-8 for 1000 BASE-LX.

Characteristics of eye opening diagram. [802.3 pg. 1045]

Post-Amplifier

Since this group will be focusing on the receiver and post-amplifier, further

background on the post-amp is necessary. The function of the post amplifier is to amplify the

incoming Trans-Impedance Amplifier (TIA) voltage signals to standard I/O levels and

improve signal integrity of the system. The typical transmitter/receiver line card system is

organized in the following manner:

3

Typical transceiver setup. [Graphic from vitesse]

An optical reception system receives an optical signal and converts it to an electrical

signal. The optical receiver, a PIN diode or an Avalanche Photo Detector (APD) converts the

optical input to a small electrical current. The current is converted to an electrical voltage by

a TIA. Signals from the TIA can be from a few mV to 50mVpp or more. After processing by

the post-amplifier this signal has sufficient power to drive the CDR. The CDR device

converts the analog input signal to a digital bit stream with an associated clock signal.

Maxim Post-Amp/TIA Hardware

[see also http://dbserv.maxim-ic.com/appnotes.cfm?appnote_number=712]

The MAX3266 evaluation kit simplifies evaluation of the MAX3266 trans-impedance

preamplifier. The EV kit includes a circuit that emulates the high-speed, zero-to-peak current

input signal that would be produced by a photodiode. The kit also includes a calibration

circuit that allows accurate bandwidth measurements.

The MAX3264 evaluation kit (data rate up to 1.25Gbps) evaluates the MAX3264

limiting amplifiers. The EV kit allows programming of the loss-of-signal (LOS) threshold and

provides layout options for alternate termination configurations. The circuit includes space for

a user-supplied preamplifier and photodiode pair mounted in a TO-46 can. The EV kit has

evaluation sites for a 16-pin TSSOP with electrical input, a 10-pin µMAX with electrical

input, and a 10-pin µMAX with optical input (not installed).

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Testing

In telecommunication transmission, the bit error rate (BER) is the percentage of bits

that have errors relative to the total number of bits received in a transmission, usually

expressed as ten to a negative power. For example, a transmission might have a BER of 10-6

(out of 1,000,000 bits transmitted, one bit was in error). The BER is an indication of how

often a packet or other data unit has to be retransmitted because of an error. Too high a BER

may indicate that a slower data rate would actually improve overall transmission time for a

given amount of transmitted data since the BER might be reduced, lowering the number of

packets that had to be resent. A BERT (bit error rate test or tester) will be used to measure the

BER for transmissions between receiver and transmitter.

Jitter can be a major factor in bit error rate. In an ideal system there would be no

jittering of the positions of the data bits and no jittering of the clock edges in the system. In

such an ideal system, the error rate would be exactly zero and there would be no errors as a

result of jitter. In fact, the edges of the clocks involved do jitter around, and the positions of

the data bits also undergo jitter. Specifically, the transmitter logic is not perfect, and so the

positions of the bits jitter around. The multimode fiber optic will cause dispersion of the

signal and so the edge transitions that define the bit positions get smeared and jittered around

more. The clock strobe in the receiver also jitters around. As a result of these imperfections,

the IEEE 802.3 standard requires that the data have a certain minimum stability (the eye

opening) so that the receiver can sample the data correctly.

Approach to testing

Using the Tektronix TDS8000 series oscilloscopes which can test high-speed digital

data communications systems and the CSA software we can send stimulus to the D-link test

model and measure the response as shown in the figure below. For example, the software will

generate a test pattern of bits that, after passing through our test model, could be compared for

accuracy with regards to the desired bit error rate. The TDS800 also has built in functions for

measuring jitter (pk-pk, RMS), eye width, +width and –width.

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Test setup for testing the card

Project Goals

For this design project, first an optomodule from a D-link network card will be

detached and installed on a new board. This optomodule will be tested alone and in

conjunction with the original D-Link card. Using the D-link card to setup a network

between two computers, files will be transferred and error rates will be measured. Finally, a

more effective circuit design will be designed, simulated and constructed as a

substitute for the current designs available in the market.

These developments will be made keeping the following goals in mind:

• Reduction of cost, by exploring cheaper parts, technologies and designs.

• Compatibility with the existing Ethernet protocols.

• Minimization of the Bit Error Rate.

System Design Introduction

Recognizing the need for inexpensive networking, a major goal of this project is to

develop a less expensive implementation of the gigabit Ethernet PC card. The integrated

circuits necessary to support gigabit Ethernet are not inherently expensive. But because these

cards are based on optical transmission over fiber optic cables, they incorporate a relatively

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expensive optomodule. Therefore the focus of this group will be on isolating the optomodule

and its supporting structures.

Procedure

In this case, we are starting with a D-Link DGE-550SX Fiber Gigabit Adapter.

This is a high-bandwidth network adapter, providing up to 2000Mbps full-duplex bandwidth

capacity to support high-end servers or any other application for which high bandwidth is

desired. No schematics for this card have been made available by the developer. This card

incorporates the Agilent HFBR-53D5 fiber optic transceiver. The transceiver is shown below.

This particular transceiver consists of an 850 nm Vertical Cavity Surface Emitting Laser

(VCSEL) in an optical subassembly (OSA) which mates to the fiber cable. The OSA is

driven by an IC which converts differential PECL logic signals into an analog laser diode

drive current.

The HFBR-53D5 transceiver module.

Part I: Extraction of HFBR-53D5

If a different optomodule is to be integrated into the card, it will be necessary to

extract the existing Agilent optomodule and remount it on a board separate from the original

D-Link card to create a test setup. The custom breadboard will be provided. Here, this group

will be following the procedure developed in a previous semester’s work.

For the first part of the project we will desolder the optomodule from the D-link card

and mount it on a custom board. By looking at the D-link board, the optical transceiver unit

was determined to be an Agilent product having model number HFBR-53D5. The bias

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schematic for the optical transceiver is shown below. Note that not all of the components

shown on the schematic are necessary when the optomodule is extracted. While the

schematic below shows both these parts and the bias network required for operation the

optical transceiver, we work with only the HFBR-53D5 unit and not the HDMP

1636A/1646A serializer/de-serializer IC.

Bias network for the HFBR-53D5 optical transceiver as specified by Agilent.

This unit will be connected to the Tx+, Tx-, Rx+ and Rx- units of the D-Link card

using the purchased SMA connectors and coaxial cables with the appropriate impedance.

Issues under consideration:

• Implementation of bias network for the optical transceiver

• Reduction of noise by using a differential input

• Components to be used

• Use of SMA connectors vs. BNC connectors.

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• Type of cable, required resistors and capacitors.

Implementation of bias network for the optical transceiver

The bias network required to operate the Agilent optical transceiver is shown on the

specification sheet for the transceiver. From the specification we see that the receiver pins 2

and 3 require inputs to come in on 50Ω lines and to be de-coupled using 0.01µF capacitors.

Similarly, pins 7 and 8 transmit on 50Ω lines that are de-coupled by 0.01µF capacitors. These

capacitors help to remove any AC or disturbance on the lines. The bias network is shown

below.

SPICE schematic showing the resistors and capacitors to be used on the board.

Reduction of noise by using a differential input

The differential inputs Tx+, Tx-, Rx+ and Rx- provide a greater signal-to-noise ratio

than a single ended input. This improved ratio is due to the fact that the differentiator takes

the difference between the two signals. Assuming the transmit signals Tx+ and Tx- contain

the same noise (N) on both lines, the resulting signals are

(N + Tx+) and (N + Tx-). So, the difference between the two signals is

(N + Tx+) - (N + Tx-) = Tx+ - Tx-

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Now, since Tx- is the inverted Tx+, this gives us

Tx+ - (-Tx+) = 2Tx+

Hence not only is the noise removed, but the signal is also boosted.

A similar case can be presented for the Rx+ and Rx- signals.

Components to be used

SMA vs. BNC connectors

SMA is a vastly superior connector to BNC in all aspects except mechanically. SMA

is better shielded and maintains impedance better. SMA is the standard on most small

microwave equipment and has been for many years. SMA is, however, a more expensive

connector and is usually avoided by the manufacturers for economic reasons. It is a logical

choice for gigabit Ethernet because it provides functionality up to 1000 MHz.

Type of cable, required resistors and capacitors

The schematic above will be built using surface mount capacitors and resistors. These

components save space but the tradeoff is in soldering these on the board since these parts are

very small and difficult to handle. To connect the optical transceiver module to the D-link

card, we need a cable with a 50Ω resistance. Because the schematic shows a 50Ω cable input

to the Tx and Rx lines, we need a 50Ω cable to impedance match the system. Thus there will

be no

reflections from either side resulting in the best signal.

Planned Approach to testing

The bit error rate (BER) is an indication of how often a packet or other data unit has to

be retransmitted because of an error. A high BER may indicate that a slower data rate would

actually improve overall transmission time for a given amount of transmitted data. A slower

transmission may result in a lower BER and a lowering of the number of packets that had to

be resent. For this test we will be looking for a BER on the order of 10-10. A BERT (bit error

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rate test or tester) will be used to measure the BER for transmissions between receiver and

transmitter.

Jitter can be a major factor in bit error rate. In an ideal system there would be no

jittering of the positions of the data bits and no jittering of the clock edges in the system. In

such an ideal system the error rate would be exactly zero and there would be no errors as a

result of jitter. The horizontal eye close jitter has been specified by the IEEE 802.3 standard to

be no more than 65ps.

The Tektronix TDS8000 series oscilloscopes with CSA software will be used to test

the D-Link model by sending stimuli to the card and measuring the response. For example,

the software will generate a test pattern of bits that after passing through our test model will

be compared for accuracy. The TDS800 also has build in functions for measuring jitter (pk-

pk, RMS), eye width, +width and –width.

Part II: Integration of Maxim Parts

This group will further explore the use of Maxim transimpedance and limiting

amplifiers. Ultimately, the goal is to build a custom gigabit Ethernet board. To do this, the

transimpedance amplifiers and limiting amplifiers must also be isolated. Instead of using the

D-Link card for this functionality, this functionality will be provided by Maxim chips from

the MAX3266 and MAX3264 Evaluation Kits.

MAX3266EV kit (Transimpedance Amplifier)

The MAX3266 evaluation kit embodies a suitable transimpedance amplifier as well as

circuitry to emulate a current input signal that would be produced by an actual photodiode.

This additional circuitry is not necessary for this design project and can safely be ignored.

The MAX3266 transimpedance amplifier is designed to accept a DC-coupled input from a

high-speed photodiode, with an amplitude of 10µA to 1mA zero-to-peak. The following

parameters characterize the required input to the MAX3266 and its resulting output.

Supply Current 26 - 50 mA

Output Impedance 48 – 52 Ohm

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VCC +3.0V to +5.5V,

Voltage at OUT+, OUT- (VCC -1.5V) to (VCC + 0.5V)

The DC transfer function of the MAX3266 TIA is shown below. Note that output

voltage ranges from –150mVp-p to 150mVp-p.

The DC transfer function for the TIA.

Below, the MAX3266 and its bias network are explored.

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Pinouts and schematic for the MAX3266 TIA are shown below.

MAX3266 TIA bias network.

Important design considerations include the following parameters:

• INPUT should approximate 50mVp-p.

• OUT+ and OUT- need 50Ω terminations.

• The connector at INPUT is terminated with 50Ω to ground.

• The device operates from a +3.0V to +5.5V single supply and requires no

compensation capacitor.

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MAX3264EV Limiting Amplifier kit

The MAX3264 EV kit embodies a limiting amplifier suitable for connection to the

MAX3266 transimpedance amplifier. The following specifications characterize the

MAX3264 in relevant part:

Supply Voltage (VCC) -+3.0V to +5.5V

Voltage at IN+, IN- (VCC - 2.4V) to (VCC + 0.5V)

Differential Input Voltage (IN+ - IN-) 2.5V

PECL Output High Voltage Referenced to VCC -1.025 - 0.880

PECL Output Low Voltage Referenced to VCC -1.810 1.620

LOS Output High Voltage ILOS = -30µA 2.4 min

LOS Output Low Voltage ILOS = +1.2mA 0.4 max

Key:

PECL = Positive-Referenced Emitter Coupled Logic

LOS = Loss of Signal

A schematic for the MAX3264 limiting amplifier is shown below.

MAX3264 limiting amplifier schematic.

The gain of the MAX3264 limiting amplifier is shown below. Note that the gain has a

maximum at 1300mV.

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Limiting amplifier gain.

Important design considerations include the following parameters:

• The output current can be set for either of two levels. (16mA or 20mA)

• The device operates from a +3.0V to +5.5V single supply

• Potentiometers R3, R4, R12, and R13 adjust the VTH voltage.

Optomodule-TIA-Limiting Amplifier Connection

The MAX3266 chip providing transimpedance amplification must be mated to the

MAX3264 post-amplifier. A typical application of the MAX3266 in conjunction with a

limiting amplifier such as the MAX3264 is shown below. These connections will be made

using SMA connectors and appropriately impedance matched wires.

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Completed network.

Part III: Custom Board

No schematic is available for the D-Link card. Thus, the custom card will consist of

the Agilent optomodule lifted from the D-Link card, combined with the MAXIM TIA and

post-amp. As shown above, we have derived the minimum bias network for the Agilent

optomodule. As previously discussed, the minimum bias networks for the TIA and post amp

are available in schematic form.

Since the MAXIM transimpedance preamplifier has a singled ended input, it will be

necessary to use either the Tx+ or Tx- outputs of the optical module (but not both) for

connection. This may lead to noise in the circuit.

Results I. The Maxim Evaluation Test Kit Results

This design project will ultimately require the connection of a laser source to a Maxim

MAX3266 transimpedance amplifier which is then connected to a Maxim MAX3264 limiting

amplifier. The output from the Maxim MAX3264 will ultimately be decoded to extract data

encoded to Ethernet standards.

A. The Laser Source

The first section of this project involved removing the HFBR-53D5 optomodule from

the D-Link DGE-550SX Fiber Gigabit Adapter card and installing it onto its own board with a

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minimized bias network. This was accomplished by first carefully desoldering the

optomodule from the D-Link card. The soldering iron was set to the lowest temperature at

which the solder on the board could be melted and removed in conjunction with solder wick.

The optomodule was then soldered onto a PCB previously designed and provided by Erik

Pace. While the optomodule had a relatively extensive bias network in place on the D-Link

board, it is not necessary that the entire network be reproduced on the remote PCB.

The minimized bias network, discussed above, was reproduced on the given PCB

using surface mount components. The components, including a pair of power supply

receptacles, were soldered to the PCB using standard equipment available in the laboratory. It

is important to note one change to the design not show on the schematic above. Because of

the way the PCBs were designed, it was necessary to run a separate wire to ground on the

board. Once this was completed, the board was tested using the Tektronix GTS1250 Bit

Pattern Generator [PRBS7] in conjunction with the Tektronix TDS7154 series oscilloscope.

Because the Agilent optomodule produces differential output consisting of RX+ and

RX-. these two channels were tested independently and together. Initial tests showed that

only one channel was producing a usable eye. While the eye shown on RX+ was consistent

with the IEEE 802.3z specifications, the RX- channel appeared on the oscilloscope as random

noise. While the channel appeared on the scope as noise, turning off the RX- channel resulted

in complete loss of the eye on the RX+ channel.

In an effort to restore the RX- channel, additional study was undertaken of the PCB.

Solder joints were inspected under a magnifier. No bad solder joints could be located by

visual inspection. However, it was noted that large amounts of solder had been deposited on

or near the surface mounted components. Without removing any of the components, much of

the excess solder was removed using a soldering iron and solder wick. After removing the

excess solder, the board was retested using the same inputs and equipment. The both

channels were fully operational and a successful eye diagram was obtained. The eye diagram

is shown below.

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The IEEE 802.3z eye mask is shown in blue in the center. As can be seen from the

screen capture, the eye achieved does not exhibit any appreciable horizontal or vertical

closure and the eye is in compliance with the specifications.

B. The MAX3266 Transimpedance Amplifier

The MAX3266 transimpedance amplifier is the next signal step after the optomodule.

The RX+ or RX- output from the optomodule are input to the transimpedance amplifier.

Because the eye achieved with the optomodule above was in complete compliance with the

IEEE 802.3z specification, the input to the MAX3266 was taken directly from the GTS1250

Bit Pattern Generator. A power supply was attached to the MAX3266 Test Kit and the OUT+

and OUT- were inputs to the oscilloscope.

The eye diagram obtained from this test is shown below.

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This eye diagram roughly conforms to the shape of the eye mask specified by IEEE

802.3. This eye diagram was taken with the vertical axis set to 50mV/div, while the previous

diagram was taken with the vertical axis set to 200mV/div. Thus, this signal has

approximately ¼ the amplitude of the signal from the complete optomodule. It is evident that

post amplification is necessary.

C. The MAX3264 Limiting Post Amplifier

The OUT+ and OUT- signals of the MAX3266 TIA are input to the IN+ and IN-,

respectively, of the MAX3264 limiting post amplifier. This connection was accomplished

with the use of SMA connectorized cables. The expected result was that the output from the

post amplifier would show a nearly identical shape as the previous eye diagram but with a

greater amplitude.

This was tested in the laboratory. The eye diagram of a signal sent from the Bit

Generator, through the transimpedance amplifier and post amplifier is shown below.

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In this case, the vertical axis is set at 100mV/div. At this setting, the eye diagram

occupies approximately twice the vertical space on the screen as the output of the TIA at

twice the vertical resolution. Thus, the post amplifier produces approximately a 4X gain in

the signal.

Custom Board Design Having verified proper operation of the Agilent optomodule and the MAXIM test kits,

a custom board was designed to incorporate only the necessary components from the MAXIM

boards.

The custom board was designed using the TIA and POST AMP chips from the Maxim

3264 and 3266 evaluation kits. The specification sheets for the chips were referenced form the

web and the dimensions and pin outs were noted. The dimensions used for the two chips were

as shown below.

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s.

MAX 3264 dimension specification.

MAX 3266 dimension specifications.

The size parameters used were “e”. “L”, “B” and “H”. For the capacitors and resistors

we used the standard “0850” package specifications shown below. Similarly, the mountings

for the SMA connectors and power supplies were designed using SuperPCB.

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0805 package resistor specifications.

The MAX 3266 chip takes in a single ended input from the SMA connector and this

incoming signal is decoupled using a 0.01µF capacitor. The MAX 3266 has differential

outputs (OUT+ and OUT-) which are coupled to the differential inputs (IN+ and IN-) of the

MAX 3264 chip using 0.01µF capacitors. These capacitors serve to remove noise in the

incoming signal. The outputs of the MAX 3264 are connected to two pull up resistors, R1

and R2, which are connected to Vcc. The differential outputs (OUT+ and OUT-) of the MAX

3264 are also coupled to SMA connectors using coupling capacitors. The resulting SuperPCB

layout is shown below.

SuperPCB layout of custom board.

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Implementation of Custom Board

The SuperPCB software was used to design a custom layout and the custom board was

milled by Bob House. The requisite SMA connectors were soldered onto the board along

with the two MAXIM chips. This completed custom board is ultimately to be connected to an

optomodule provided by another group. The combined system would then be tested with the

oscilloscope for IEEE 802.3z compliance.

D-Link to Optomodule Link Setup

Thin SMA connectorized cables were ordered from Assemblies, Inc. and used to test

the previously extracted Agilent optomodule with the D-Link board installed in a PC testbed.

Given the high quality of the eye produced by the extracted optomodule, it was expected that

the point to point test would be successful.

The optomodule board was connected to the D-Link board using thin SMA

connectorized cables. The SMA cables, originally male to male cables, were cut in half and

the free ends soldered to the appropriate places on the D-Link. Careful attention was paid to

the length of exposed wire at the point of contact with the board. If an appreciable length of

unshielded wire is exposed at the end, the signal will be lost. Additionally, the shielding on

each pair of cables (RX and TX) was soldered together.

Several modifications were made to the D-Link board. Resistors R19, R20, R23, R24.

R28, and R29 were removed from the bias network on the D-Link board. These resistors had

been made redundant by the bias network in place on the optomodule board.

The capacitors on the D-Link board were left in place. The resulting combined board

is shown below. The green wires connect the signal detect and ground on the optomodule to

the D-Link board.

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This combined board was then installed in one of the testbed computers in a free PCI

slot. The testbed is shown below.

The second testbed (not shown) consisted of an identical PC running an Intel Gigabit

Ethernet card. The transmit and receive optical links from the optomodule were connected to

the appropriate receptacles on the Intel board on the second testbed.

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Next, the combined board was tested in a link with the Intel Gigabit Ethernet board.

The results of the test are shown below.

Note that the “Link” result shows a pass on this diagnostic test. From the Intel test

software, it appeared that the link between the cards was functional. To further test the link,

diagnostic software was installed on the D-Link testbed PC. A suite of diagnostics were run

on the combined board and the results are shown below.

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When tested on the D-Link side, it was apparent that the link was not working

correctly. The “Physical Layer Test” shows a status of “Failed.” Presumably, this failure is a

result of a fault in the link between the optomodule and the D-Link board. The optomodule

alone produced a compliant eye as shown above. Therefore, the focus of the circuit

debugging was on the link between the optomodule and the D-Link board. The exposed wire

leads at the SMA/D-Link interface were further shortened and resoldered so that no more

than 2mm of unshielded wire remained exposed.

The board was then re-tested with the diagnostic software. Identical results were

achieved.

The rear edge of the D-Link board has four LEDs indicating board status. At all

times, the middle two remained illuminated. At other times, the outer two LEDs would flash

intermittently. While the D-Link documentation noted the meaning of the LEDs, it did not

note which LED was one and which was four. The included PDF documentation noted that

the DGE-500SX Adapter features four LED indicators:

• FDX - Steady green indicates the adapter is operating in Full-Duplex mode.

• 1000M - The indicator lights green when a 1000 Mbps device is connected to the adapter.

• Link - Steady green indicates good linkage between the DGE- 500SX and its supporting

server or switch.

• TX/RX - Flashing green indicates activity (transmitting or receiving) within the adapter.

Assuming that the manual lists the LEDs from left to right or right to left, our tests found the

1000M and Link LEDs illuminated at all times. The other two were illuminated sporadically.

Possible Reasons for Test Failure

Because the optomodule was successfully tested apart from the D-Link board, the

failure is not believed to be a result of a problem in the optomodule. The soldered SMA

connections on the D-Link board exposed not more than two millimeters and thus were within

design specifications. The bias network on the D-Link board, however, was incompletely

specified and is the most likely source of the physical layer failure. D-Link provided no

schematics for the DGE-500SX board and it was difficult to determine which resistors were

redundant and needed to be removed. By following the traces on the D-Link board, those

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resistors believed to be redundant were removed. However, because it was not possible to

determine with certainty which resistors were redundant, it is possible that necessary

components were removed.

Custom Board Design –MAXIM TIA and Post Amp evaluation boards

The extremely thin pads on the MAX3264 chip presented some difficulty for soldering

on the milled board. To overcome this, we were advised to use a micro tip soldering iron and

very thin solder wire (15000’s). Due to the lack of the appropriate solder wire and soldering

tip, we improvised by using a solder tip that had been filed to a point and regular solder wire

(25000’s). A photo of the milled custom board with soldered components is shown below.

Note the single-ended input on the left (input from laser source) and differential outputs on

the right (output to clock and data recovery unit.)

The custom board is a condensed version of the MAXIM TIA and post amp evaluation

kits as shown below. The TIA chip (MAX3266) and the post amp chip (MAX3264) were

soldered to the custom milled board along with the required network of resistors, capacitors

and power supplies. The conversion is shown below.

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The custom board takes in a single-ended input to the MAX3266 chip (the

Transimpedance Amplifier) through SMA connectors and AC decoupling capacitors.

The AC decoupling capacitor along with the pull down resistor isolates the DC. Pin 3 is

the input for the decoupled signal and Pin 1 is connected to VCC (5 volts) with a

coupling capacitor to ground. Since a capacitor acts as an open circuit for DC (zero

frequency) and a short circuit for AC (high frequency), any AC noise will be directed to

ground. Pins 5 and 8 have been grounded according to the chip specifications. The

differential outputs of the MAX 3266 chip (pins 2 and 3) are connected to the differential

inputs of the MAX3264 chip (pins 4 and 5) via coupling capacitors. Pins 3 and 6 on the

MAX3266 are connected to ground according to specification. Pin 8 is connected to a

threshold resistor that is grounded. Pins 11 and 14 are connected to VCC and the outputs

(pins 12 and 13) are connected to SMA connectors through coupling capacitors that have

a pull up to VCC. There are four power connections on the board: two to VCC and two

to ground. The two VCCs and grounds are connected together on the back of the board.

The power supply connectors were connected to these ports as shown in the figure above.

Testing

The custom board was tested in manner similar to the testing of the maxim TIA

and post amp evaluation kits. The input to the board is single ended from a function

generator that can generate patterns such as D21.5, PRBS7 and K28.7.

Initially we obtained a very weak signal on the PRBS7, however the D21.5 did

give a signal on channel 1 and after tweaking the circuit by resoldering several

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components and pads, we obtained a strong signal in both channels as shown in the figure

below. Note that D21.5 was the input in this setup shown below.

The two channels superimposed together over the mask are shown below.

After further adjustments to the components soldered on the board, the PRBS7

gave a noisy eye as shown below. While the signal is weak and the eye is closed, the

contours of a signal can be discerned.

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Possible reasons for noisy PRBS7 eye

The PRBS7 has more high frequency components than the D21.5 and thus

requires more bandwidth. If the board traces are not sufficiently short, then performance

of the system will be degraded. Every attempt was made to keep the board traces as short

as possible. While the traces between the TIA and post amp were made as short as the

CAD tools would allow, the trace widths had to be between 15 and 30 milli-inches

because of fabrication constraints set by Bob House. Because of these thick traces,

sufficient distance had to be kept between connections to avoid overlap of traces and

pins. Within these constraints, the trace lengths between the chips were minimized.

Additionally, it is also possible that the traces running from the SMA connectors to the

chips may have been too long to properly carry a signal with the high frequency

components present in the PRBS7 signal.

Due to the difficulties involved in working with the extremely small chip leads, it

is also possible that there were problems with the input and output connections.

Specifically, one or more of the post amp leads may be floating or shorted. The bias

network, while implemented according to specification, might be missing necessary

components. While chip specifications limited the soldering temperature to less than

550°F and contact with the chip pins to less than ten seconds, damage to the chip is

possible during the soldering and re-soldering of components.

30

The traces on the milled board were very thin and some appeared to be severely

damaged during the soldering and re-soldering of components. Attempts were made to

restore the traces using solder and thin wires, but no improvement was found. While the

use of right angles for the traces was discouraged, in some places it was unavoidable and

these angles might have limited the performance of the board.

The small, closely spaced, leads of the MAX3264 limiting post amplifier were the

most likely cause of the weak output on the PRBS7 signal. It was extremely difficult to

solder these leads and on visual inspection the status of several leads could not be readily

determined.

Conclusion

It is the conclusion of this group that gigabit Ethernet may become an affordable

solution capable of supplanting 10/100BaseT networks already in place. While the

results of the tests performed in this study showed the need for further analysis of the

systems under test, it is apparent that these systems can be made to perform in

compliance with the IEEE 802.3 specification.