gate level minimization - digital logic design (eee...
TRANSCRIPT
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Gate Level Minimization
Lecture 06,07,08
By : Ali Mustafa
![Page 2: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/2.jpg)
Outline
•Introduction
•The Karnaugh Map Method
–Two-Variable Map
–Three-Variable Map
–Four-Variable Map
–Five-Variable Map
•Product of Sums Simplification
•Don’t-Care Conditions
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Introduction – The Map Method • K map provides a pictorial method of grouping together
expressions with common factors and therefore eliminating unwanted variables.
• The K map can also be described as a special arrangement of a truth table.
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Choice of Blocks
• We can simplify function by using larger blocks –Do we really need all blocks? –Can we leave some out to further simplify
expression? • Function needs to contain special type of blocks –They are called Essential Prime Implicants • Need to define new terms –Implicant –Prime implicant –Essential prime implicant
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Terminology
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Procedure for Simplifying Boolean Functions
1.Generate all PIs of the function.
2.Include all essential PIs.
3.For remaining minterms not included in the essential PIs, select a set of other PIs to cover them, with minimal overlap in the set.
4.The resulting simplified function is the logical OR of the product terms selected above.
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Examples to illustrate terms
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2 variable map example
F = m3 F = m1 + m2 + m3
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Two Variable Map
• Consider the following map. The function plotted is: Z = f(A,B) = A + AB
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3-variable K Map
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Example : 3-variable K Map (Cont..)
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Example : 3-variable K Map
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Another Example : 3-variable K Map
F = yz + xz’
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3-variable K Map
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Self Tasks
• Solve the expression using K MAP
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Solution of Self Tasks
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4-variable Karnaugh Map
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4-variable Karnaugh Map • K map can be extended to 4 variables:
• Top cells are adjacent to bottom cells. Left-edge cells are adjacent to right-edge cells.
• Note variable ordering (WXYZ).
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Four-variable Map Simplification
• One square represents a minterm of 4 literals.
• A rectangle of 2 adjacent squares represents a product term of 3 literals.
• A rectangle of 4 squares represents a product term of 2 literals.
• A rectangle of 8 squares represents a product term of 1 literal.
• A rectangle of 16 squares produces a function that is equal to logic 1.
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Example : 4-variable K Map
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Example
• Simplify the following Boolean function g(A,B,C,D) = Σm(0,1,2,4,5,7,8,9,10,12,13).
• First put the function g( ) into the map, and then group as many 1s as possible.
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Example: 4-variable Karnaugh Map
• Example: F(w,x,y,z)=Σ(0,1,2,4,5,6,8,9,12,13,14)
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Simplifying logic Function using 4-variable K-Map
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5-variable Karnaugh Map
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Example: 5-variable Karnaugh Map
• F(A,B,C,D,E) = Σ(0,2,4,6,9,13,21,23,25,29,31)
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Product of Sums Minimization
• How to generate a product of sums from a Karnaugh map?
–Use duality of Boolean algebra (DeMorgan law)
• Look at 0s in map instead of 1s –Generate blocks around 0’s –Gives inverse of function –Use duality to generate product
of sums • Example: –F = Σ(0,1,2,5,8,9,10) –F’ = AB+ CD + BD’ –F = (A’+B’)(C’+D’)(B’+D)
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You can easily do product‐of‐sum too
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You can easily do product‐of‐sum too
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Example: POS minimization
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Don't Care Conditions
• There may be a combination of input values which will never occur if they do occur, the output is of no concern.
• The function value for such combinations is called a don't care.
• They are usually denoted with x. Each x may be arbitrarily assigned the value 0 or 1 in an implementation.
• Don’t cares can be used to further simplify a function
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Minimization using Don’t Cares
• Treat don't cares as if they are 1s to generate PIs.
• Delete PI's that cover only don't care minterms.
• Treat the covering of remaining don't care minterms as optional in the selection process (i.e.they may be, but need not be, covered).
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Minimization example
• F(w,x,y,z) = Σ(1,3,7,11,15) and d(w,x,y,z) = Σ(0,2,5)
• What are possible solutions?
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Another Example
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Self Tasks
• Self reading chapter 3 (Revision)
• 3.1 to 3.15 Chapter 3 exercise
• Self reading chapter 2 (Revision)
• 2.1 to 2.28 Chapter 2 exercise
Except 2.10,2.15,2.16,2.24-2.26
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Recap
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2 Variable K-Map
1
1
1
0
A B B’ B
A’
A
Group 1
Group 2
A’
B’
F= A’ + B’
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3 Variable K-Map
m0
m1
1
m3
1
m2
m4
1 m5
1 m7
m6
A BC
A’ 0
A 1
B’C’ 00 B’C 01 BC 11 BC’ 10 Group 1
A’B Group 2
AC
IGNORE
F= A’B + AC
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3 Variable K-Map
1
m0
1
m1
1
m3
1
m2
m4
1 m5
1 m7
m6
A BC
A’ 0
A 1
B’C’ 00 B’C 01 BC 11 BC’ 10 Group 1
A’ Group 2
C
F= A’ + C
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3 Variable K-Map
1
m0
1
m1
1
m3
1
m2
1
M4
1
m5
1
m7
1
m6
A BC
A’ 0
A 1
B’C’ 00 B’C 01 BC 11 BC’ 10 Group 1
1
F= 1
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3 Variable K-Map
1
m0
0
m1
1
m3
0
m2
0 m4
1 m5
0 m7
1 m6
A BC
A’ 0
A 1
B’C’ 00 B’C 01 BC 11 BC’ 10
A’BC
AB’C
ABC’ A’B’C’
F= A’B’C’ + A’BC + AB’C + ABC’
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4 Variable K-Maps
0
m0
0
m1
0
m3
0
m2
0
m4
0
m5
0
m7
0
m6
0 m12
0 m13
0 m15
0 m14
1
m8
1
m9
1 m11
1 m10
AB CD
C’D’ 00 C’D 01 CD 11 CD’ 10
A’B’ 00
A’B 01
AB 11
AB’ 10
Group 1
AB’
F= AB’
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4 Variable K-Maps
0
m0
0
m1
0
m3
0
m2
1
m4
1
m5
0
m7
0
m6
1 m12
1 m13
0 m15
0 m14
0
m8
0
m9
0 m11
0 m10
AB CD
C’D’ 00 C’D 01 CD 11 CD’ 10
A’B’ 00
A’B 01
AB 11
AB’ 10
Group 1
BC’
F= BC’
![Page 43: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/43.jpg)
4 Variable K-Maps
0
m0
1
m1
1
m3
0
m2
0
m4
0
m5
0
m7
0
m6
0 m12
0 m13
0 m15
0 m14
0
m8
1
m9
1 m11
0 m10
AB CD
C’D’ 00 C’D 01 CD 11 CD’ 10
A’B’ 00
A’B 01
AB 11
AB’ 10
Group 1
B’D
F= B’D
![Page 44: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/44.jpg)
4 Variable K-Maps
0
m0
0
m1
0
m3
0
m2
1
m4
0
m5
0
m7
1
m6
1 m12
0 m13
0 m15
1 m14
0
m8
0
m9
0 m11
0 m10
AB CD
C’D’ 00 C’D 01 CD 11 CD’ 10
A’B’ 00
A’B 01
AB 11
AB’ 10
Group 1
BD’
F= BD’
![Page 45: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/45.jpg)
4 Variable K-Maps
0
m0
1
m1
1
m3
0
m2
1
m4
0
m5
0
m7
1
m6
1 m12
0 m13
0 m15
1 m14
0
m8
1
m9
1 m11
0 m10
AB CD
C’D’ 00 C’D 01 CD 11 CD’ 10
A’B’ 00
A’B 01
AB 11
AB’ 10
Group 1
BD’
Group 2
B’D
F= BD’ + B’D
![Page 46: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/46.jpg)
5 Variable K-Maps
1
m0
1
m1
1
m3
1
m2
1
m4
0
m5
0
m7
0
m6
1
m12
0
m13
0
m15
0
m14
1
m8
0
m9
0
m11
0
m10
1
m16
0
m17
0
m19
1 m18
1 m20
0 m21
0 m23
0 m22
1 m28
0 m29
0 m31
1 m30
1 m24
1 m25
1 m27
1 m26
A’ 0 A 1
Adjacent Rows
BC DE
BC DE
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5 Variable K-Maps
1
m0
1
m1
1
m3
1
m2
1
m4
0
m5
0
m7
0
m6
1
m12
0
m13
0
m15
0
m14
1
m8
0
m9
0
m11
0
m10
1
m16
0
m17
0
m19
1 m18
1 m20
0 m21
0 m23
0 m22
1 m28
0 m29
0 m31
1 m30
1 m24
1 m25
1 m27
1 m26
A’ 0 A 1
Adjacent Columns
BC DE
BC DE
![Page 48: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/48.jpg)
5 Variable K-Maps
1
m0
0
m1
0
m3
1
m2
1
m4
0
m5
0
m7
1
m6
0
m12
1
m13
1
m15
0
m14
0
m8
1
m9
1
m11
0
m10
0
m16
1
m17
0
m19
0 m18
0 m20
1 m21
0 m23
0 m22
0 m28
1 m29
1 m31
0 m30
0 m24
1 m25
1 m27
0 m26
A’ 0 A 1
BC
DE
BC
DE
Simplify F = ∑m(0,2,4,6,9,11,13,15,17,21,25,27,29,31)
B’C’ 00
BC’ 10
BC 11
B’C 01
B’C’ 00
B’C 01
BC 11
BC’ 10
D’E’ 00 D’E 01 DE 11 DE’ 10 D’E’ 00 D’E 01 DE 11 DE’ 10
A’B’E’ + AD’E + BE F =
![Page 49: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/49.jpg)
5 Variable K-Maps
1
m0
0
m1
0
m3
1
m2
0
m4
1
m5
1
m7
0
m6
0
m12
1
m13
1
m15
0
m14
0
m8
0
m9
0
M11
0
m10
0
m16
0
m17
0
m19
1 m18
1 m20
1 m21
1 m23
0 m22
1 m28
1 m29
1 m31
0 m30
0 m24
0 m25
0 m27
0 m26
A’ 0 A 1
BC
DE
BC
DE
Simplify F = ∑m(0,2,5,7,13,15,18,20,21,23,28,29,31)
B’C’ 00
BC’ 10
BC 11
B’C 01
B’C’ 00
B’C 01
BC 11
BC’ 10
D’E’ 00 D’E 01 DE 11 DE’ 10 D’E’ 00 D’E 01 DE 11 DE’ 10
A’B’C’E’ + ACD’ + CE + F = B’C’DE’ F = A’B’C’E’ + B’C’DE’ + ACD’ + CE F = B’C’E’(A’ + D) + ACD’ + CE
![Page 50: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/50.jpg)
6 Variable K-Maps
m0
m15
A’B’00 EF CD
m31
A’B 01 EF CD
m47
AB 11 EF CD
m63
AB’10 EF CD
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Simplify 4 Variable K-MAP
• Find the groups and write the desired equation
1
m0
1
m1
1
m3
1
M2
1
m4
0
m5
0
m7
0
M6
1 m12
0 m13
0 m15
0 m14
1
m8
0
m9
0 m11
0 m10
1
m0
0
m1
0
m3
1
m2
1
m4
0
m5
0
m7
0
m6
1 m12
0 m13
0 m15
1 m14
1
m8
1
m9
1 m11
1 m10
1
M0
1
m1
1
m3
1
m2
1
m4
1
m5
1
m7
1
m6
0 m12
0 m13
0 m15
0 m14
0
m8
1
m9
1 m11
0 m10
![Page 52: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/52.jpg)
Self Task
• Y = ∑m(1,5,7,9,11,13,15)
• Y = ∑m(1,3,5,9,11,13)
• Y = ∑m(4,5,8,9,11,12,13,15)
• Minimize the following expression using K-Map and realize it using number of gates
![Page 53: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/53.jpg)
Product of Sum K-MAP
Two ways to express
–Y = ∑ (0,1,2,5,8,9,10)
–Y = ∏ (0,2,3,5,7)
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POS K-MAP Y = ∑ (0,1,2,5,8,9,10) Make POS expression
1
m0
1
m1
0
m3
1
m2
0
m4
1
m5
0
m7
0
m6
0 m12
0 m13
0 m15
0 m14
1
m8
1
m9
0 m11
1 m10
F = (C’+D’)(A’+B’)(B’+D)
AB CD
C’D’ 00 C’D 01 CD 11 CD’ 10
A’B’ 00
A’B 01
AB 11
AB’ 10
CD + AB + BD’ F’ =
Applying De Morgan Law
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POS K-MAP
0
m0
m1
0
m3
0
m2
m4
0 m5
0 m7
m6
A BC
A’ 0
A 1
B’C’ 00 B’C 01 BC 11 BC’ 10
B’+C’
A’+C’
A+C
F= (B’+C’)(A+C)(A’+C’)
Simplify Y = ∏ (0,2,3,5,7)
But in POS we consider 0 as a positive logic SO
![Page 56: Gate Level Minimization - Digital Logic Design (EEE 241)digitallogicdesign.weebly.com/uploads/1/3/5/4/13541180/lecture... · Gate Level Minimization Lecture 06,07,08 By : ... •Introduction](https://reader034.vdocument.in/reader034/viewer/2022052217/5aacddc17f8b9a693f8d9b03/html5/thumbnails/56.jpg)
Self Tasks
1. Simplify the following expression with POS
A. Y = ∏ (0,2,3,7) B. Y = ∏ (0,2,8,10) C. Y = ∑ (0,1,2,5,8,10,13)
2. Simplify the following expression with SOP & POS
A. Y = X’Z’ + Y’Z’ + YZ’ + XY
3. Exercise questions 3.1 to 3.14