gem project, c-band polarimetry using a full digital

08/11/2508/11/25 22ºº CongressoCongresso URSI PortugalURSI Portugal

GEM Project, C-Band Polarimetryusing a full digital correlator

Miguel BerganoGRIT – Aveiro

www.av.it.pt/gem

FCT Grants• POCTI/CTE-AST/57209/2004• PTDC/CTE-AST/65925/2006

08/11/2508/11/25 22ºº CongressoCongresso URSI PortugalURSI Portugal 22

AuthorsAuthors

Miguel Bergano1, Francisco Fernandes1,2, L. Cupido 4, D. Barbosa1,2, R. Fonseca1,2,3, D. M. Santos1,3, G. Smoot5,6,Ivan S. Ferreira7, Luis Reitano7

1 Grupo de Radioastronomia, Instituto de Telecomunicações, Portugal2 CENTRA, Instituto Superior Técnico, Lisboa, Portugal

3 DET Universidade Aveiro, Aveiro, Portugal4 Centro de Fusão Nuclear, Lisboa, Portugal

5 Lawrence Berkeley National Laboratory, USA6 Physics Dept., University of California, Berkeley, USA

7 INPE – Instituto Nacional de Pesquisas Espaciais, Brasil


OverviewOverview

UnveilUnveil thethe SkySky to CMBR;to CMBR;Applicable to a Galactic Experiment;Applicable to a Galactic Experiment;High sensitivity radiometer;High sensitivity radiometer;SuperheterodyneSuperheterodyne ReceiverReceiver withwithDoubleDouble DownDown ConversionConversion –– Zero IF;Zero IF;IF chain developed and tested;IF chain developed and tested;FullFull Digital Digital BackBack--endend;;StokesStokes ParametersParameters CalculationCalculation..


SuperheterodyneSuperheterodyne ReceiverReceiver(Base(Base--band Complex band Complex CorrelatorCorrelator))

Novel approach to digital correlators!The radiometer/polarimeter gain budget:

Antenna LNA Passive Filter

Mixer IF Pre Amplifier

IF Amplifier

Converter ADC

-105,6 -79,6 -83,6 -90,6 -59,6 -3,6 -1,6 -2

31 56 2 Output(dBm)

Input (dBm) 26 -4 -7


Receiver characteristicsReceiver characteristicsBandwith of 200MHz around 4.9GHz; ADS designedTant ~10K - total power of -105.6dBm–TOTAL GAIN~104 dB;RF Cryogenic PHEMT InP LNAs (@ 77K);Image rejection filter;

Latest RF technology and microstrip linesSMD components; central freq. 600MHzSlope Compensation Network application;Diode Mixers; IF Preamplifier – filter 31dB gain;IF Amplfier 71dB gain with digital control attenuator;Zero IF converter; I/Q modulation per polarization Full Digital correlator:

ADC at 200 MSPS with 8 bits of resolution;Altera Cylone II FPGA working at 100MHz with Interleaving;


IF part designed and testedIF part designed and tested

IF Chain+RF Filter

4.9GHZ; B=600MHzCoupled Line filter

B=200MHz; 31dB; ButterworthMMIC (best response flatness)

Flat gain; 71dB;Digital attenuation

120dB isolation between portsFrequency 600MHz; VCO; MMIC Amp.;

PLL synthesyzer; 7dBm


PortP2Num=2

PortP1Num=1

MCFILCLin4

L=9263.161 umS=35.599 umW=574.232 umSubst="MSub1"

MCFILCLin3


MCFILCLin2


MCFILCLin1


MicrowaveMicrowave PassivePassive FilterFilter

Central Central FrequencyFrequency = 4,9 GHz;= 4,9 GHz;BandwidthBandwidth = 800 MHz;= 800 MHz;CoupledCoupled LinesLines;;ADS Design ADS Design aidedaided;;ElectromagneticElectromagnetic SimulationSimulation..

Substrate – RO4003C

Substrate Thickness H 20 mil

Relative Dielectric Constant εr 3,38

Conductor Thickness T 0,35μm

Dielectric Loss Tangent tan δ 0,0021

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 190 20

-60

-50

-40

-30

-20

-10

0

-70

10

frequency [GHz]

[dB

]

S - parameter

dB(S(2,1))

dB(S(1,1))

dB(S(1,2))

dB(S(2,2))


L1 C1

L2 C2

L3

C3

Vcc =8V

IF Pre IF Pre -- AmplifierAmplifier

GainGain = 31 = 31 dBdBSlopeSlope CompensationCompensation NetworkNetwork;;GainGain variationvariation withwith frequencyfrequency;;GainGain variationvariation withwithTemperatureTemperature;;SS--ParametersParameters SimulationSimulation..

HighHigh Q Q filterfilter;;Central Central FrequencyFrequency = 600 MHz;= 600 MHz;BandwidthBandwidth = 200 MHz;= 200 MHz;T T configurationconfigurationButterworthButterworth PrototypePrototype;;HandHand mademade InductancesInductancesADS Design ADS Design aidedaided;;

Amplifier Filter

P1dB = -24 dBm


Vcc =8V

4 4

µC

IF AmplifierIF AmplifierGainGain = 71 = 71 dBdB;;FlatFlat gaingain;;Digital Digital attenuationattenuation controlcontrol;;SlopeSlope CompensationCompensation NetworkNetwork;;GainGain variationvariation withwith frequencyfrequency;;GainGain variationvariation withwith TemperatureTemperature;;SS--ParametersParameters SimulationSimulation..

P1dB = -61 dBmIP3= -41 dBm


ConverterConverter

75 1455 210

-28

-18

-8

-38

2

Frequency [MHz]

[dB

m]

Converter output

Zero Zero –– IF IF ConversionConversion (LB = 100MHz);(LB = 100MHz);PhasePhase (I) (I) andand QuadratureQuadrature (Q) (Q) ModulationModulation;;SignalSignal AmplificationAmplification (G(GSINALSINAL = 16 => 25 = 16 => 25 dBdB););PortPort IsolationIsolation = 120 = 120 dBdB;;SuitableSuitable for for StokesStokes ParametersParameters CalculationCalculation;;MicrostripMicrostrip LinesLines withwith equalequal lengthslengths;;ProtectionProtection ((outsideoutside interferenceinterference & & parasiticsparasitics).).


Local Local OscillatorOscillator

VCO

50Ω

50Ω

50Ω

50Ω

0 dBm

0 dBm

10 dBm

90º

90º

0º

0º≈ 7 dBm

≈ 7 dBm

≈ 7 dBm

≈ 7 dBm

R1

R2

R2

R3

R3

PLL

0,6 dBm

FrequencyFrequency = 600 MHz = 600 MHz withwith 7 7 dBmdBm;;ProvidesProvides thethe converter converter withwith 4 4 signalssignalsPLL PLL SinthesizedSinthesized;;MicrostripMicrostrip LinesLines withwith equalequal lengthslengths;;ProtectionProtection ((outsideoutside interferenceinterference & & parasiticsparasitics).).


Full 4Full 4--channel Digital channel Digital CorrelatorCorrelatorCorrelations computed in a FPGA after signal digitalization (ADC interleaving) and outputs I,Q,U Stokes signals:

Why an FPGA Cyclone II from ALTERA?Why an FPGA Cyclone II from ALTERA?

• Embedded Multipliers;

• Number of pins;

• Frequency.


Digital CorrelatorDigital CorrelatorISA Interface output

• ADCs AD9481 from AnalogDevices.• 250 Msps• 8 bits of resolution

Analog inputs • FPGA EP2C8Q208C7 Cyclone II from ALTERA• 8256 LE.• Number of 9 bits multipliers = 36;• 208 pins• Speedgrade 7

Active Serial modeprogramming interface

Cristal Oscilator100 MHz


1. Signals correlation from the 4 ADCs, (8 bits sum andmultiplications every)

2. Integration of correlated signals.

3. Output Stokes parameters to PC104

FPGA calculates the Stokes parameters (I, Q, U).(VHDL code implementation by Francisco Fernandes)

Full Digital Full Digital CorrelatorCorrelator

FPGA is anALTERA

Cyclone II and works at

100 MHzFPGA

⊗ ∫→ I, Q, UPC104

N

N+1

100 MHz

Cyclone IIADC 1

N

N+1ADC 2

N

N+1ADC 3

N

N+1ADC 4

8 bits ofresolution200 MSPS

0,5Vpp

I,Q,U,V=F(ADC1,ADC2,ADC3,ADC4)

08/11/2508/11/25 22ºº CongressoCongresso URSI PortugalURSI Portugal 151508/11/2508/11/25 22ºº CongressoCongresso URSI PortugalURSI Portugal 1515

MainMain FeaturesFeatures ofof PC104 (PC104 (MOPSlcdLXMOPSlcdLX**))

HardwareHardware•• 500 MHz AMD LX800500 MHz AMD LX800TM TM

ProcessorProcessor•• 256 256 MByteMByte DDRDDR--RAMRAM•• ChipDiskChipDisk IDE 1 IDE 1 GByteGByte•• Support: ISA, EthernetSupport: ISA, Ethernet•• Power supply: 5VPower supply: 5V

SoftwareSoftware•• Linux, kernel 2.4Linux, kernel 2.4• Dedicated, custom-made

software for FPGA communication via ISA bus (C lang. –implemented by Francisco Fernandes).

•• SSH File transfer.SSH File transfer.* www.kontron.com/MOPS


LIRAeLinux for Radio Astronomy embedded

LIRAe is a microlinux distribution, to run on CPU embedded systems and control radioastronomy digital correlators based on FPGA chips.

The system was tested and runs on a PC104 from Kontron, model MOPSlcdLX.

Download available soon.LIRAe main developer: Francisco Fernandes

email : [email protected]


MechanicalMechanical LayoutLayout


ConclusionConclusion : : RadiometerRadiometer factsfactsTsys < 20 K; B = 200 MHz; 104 dB gainHigh-performance IF strip Latest RF tech+ microstrip design + MMIC

New Radioastronomy Design:Zero-IF Converter + I,Q modulationDigital Correlator : 4-channel, FPGA implemented!Dynamic Range: Total=20dB, Instantaneous=80dBSuitable for state of the art radioastronomyapplications.

gem project, c-band polarimetry using a full digital

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