gemma (gem mixed-signal asic): design & developing second year ph.d. activity report alessandro...

GEMMA (GEM Mixed-signal Asic):Design & DevelopingSecond Year Ph.D. Activity Report

Alessandro PEZZOTTA

26 September 2013

Tutor: Prof. A. Baschirotto

Scuola di Dottorato di Scienze – Corso di Dottorato in Fisica e AstronomiaCiclo XXVIII

Emails: [email protected], [email protected]

mailto:[email protected]

mailto:[email protected]

Alessandro PEZZOTTA "GEMMA (GEM Mixed-signal Asic): Design & Developing" 2

Outline

• The application: Triple-GEM detector

• Project Time Evolution

• Main Design Features

• Layout and Post-Layout Simulations

• GEMMA Overall Performance

• Future perspectives

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Outline







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The Application

• The GEM detector• Belonging to MPGC family• Employed for tracking, time-of-flight, counting, beam

monitoring measurements

• Main features• High count rate: > 106 cps• Low-cost• Adaptability• Portability

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300 µm

1 cm


Existing Read-Out Systems

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• All the systems now in use have been re-adapted from other applications:

• CCDs• Semiconductor Detectors• Multi-Wire Chambers

• Not exploiting the full GEM detector potential• Uniquely analog or digital systems• Limited number of detecting channels included on

a single chip


The Main Issue

• The Pixellated Output• It can be adapted according to measurement necessities• Variable Pixel Parasitic Capacitance

• Issues for read-out• Adaptability • Efficiency• Speed

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Outline







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First Attempt: GEMINI v1

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Parameter ValueCMOS Technology STM 130 nm

# of Channels 8

Max Pixel Capacitance 15 pF

Analog Outputs Preamp Analog (selectable)

Digital Output CMOS ToT & Event Detection

Max Count Rate 4 Mcps

Power Consumption 3.8 mW/channel

Sensitivity 6 fC

Gain 0.5 mV/fC

Dynamic Range From 30 fC to 1 pC

Reset Mode Digital


GEMINI v1 Problem

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PAD To chip

VDD_PAD

PAD To chip

How it should be How it was


Why GEMMA?

• Problems faced in the first version tests

• Decision to make a second version, GEMMA• CMOS technology changed (and related software) to

180nm AMS IBM, more stable and reliable

• Re-adjustment of specifications• Complying with updated detector performance

• Channel number increased to 16 (instead of 8)

• LVDS digital outputs and analog output for each channel

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Updated System Requirements

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Parameter Value

Count Rate > 3 Mcps

# of Channels 16

Sensitivity < 3 fC

Output Analog and LVDS Digital

Max Digital Output Jitter 9 ns

Max Pixel Capacitance 40 pF

Charge-to Voltage Gain 1 mV/fC

Gain Accuracy 5%

Reset Trigger Event-Based


Outline







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GEMMA Channel Scheme

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I2C INTERFACE

DACn<8:0>

CALIBRATION BLOCK

dCAP<4:0>

SCL

SDA X 16

CF

RST

VPRE

DAC<8:0> R-2R DAC

VTH

LVDS

RESET TRIGGER

CF

RST

VPRE

DAC<8:0> R-2R DAC

VTH

LVDS

RESET TRIGGER

CF

EXT_RST

VPRE

DAC<8:0>R-2R DAC

VTH

AOUT

LVDS

DOUTP

DOUTM

DET_IN

DET_GND

RESET TRIGGER

X 16Read-Out Channel

SoT

EoT

VRST

VDIS

IDET

TimeMAX 350 ns

IDET

VPRE

VTH

VDIS

VRST

CD

IL

Detector, Signal Lines and I/O pad

CP


GEMMA Main Blocks• Charge-Sensitive Preamplifier

• Two-Stage Miller OTA• 65 dB DC-Gain• 320 MHz UGBW• 100 V/µs SR• 4.3 nV/√Hz IRN• 1.5 mW Power

• Comparator• Single Ended Mirrored• 0.9 mV offset• 700 uW Power

• R-2R Resistive Ladder DAC• 9-bit resolution• 500 mV full scale• 1.2 mV LSB• Sets the comparator threshold

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• Tuning machine for CF cap• 5-bit resolution• Switched-off during measure• 5% Max Capacitance error

• Reset switches• High speed• Low charge injection• Low on-resistance

• A2D & D2A Level Shifters• Interface elements• Digital Supply 1.8 V to 0 V• Analog Supply 1 V to -1 V• Negligible signal time delay

• I2C Interface• Setting the DAC input words


GEMMA Digital Layout

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• The digital blocks substrate has been isolated for strongly reducing coupling with the analog, implementing a Triple-Well structure

n+ n+

p-substrate

p-well

n+ n+p+ p+

DIGITAL NFET

n+ n+p+ p+

ANALOG NFET

Deep n-well

p+ p+

n-well

DIGITAL PFET

n+


Outline







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GEMMA Layout

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Area = 6.89 mm2


GEMMA Simulations Settings

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• Parasitic Extraction after Layout Procedure

• Simulation including those parasitics

• Input Parameters for 100 Monte-Carlo iterations• Pixel Capacitance 40 pF• Chain of Minimum (30 fC) and Maximum Input Signal

Pulses (500 fC)• Detector first 2 e- threshold (-2.5 mV with 0 mV Input

Signal common mode)


GEMMA Simulations Results

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• 30 fC simulation


GEMMA Simulations Results

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• 500 fC simulation


Outline







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GEMINI v1 vs GEMMAParameter GEMINI v1 GEMMA

CMOS Technology STM 130 nm AMS IBM 180 nm

# of Channels 8 16

Max Detector Capacitance 15 pF 40 pF

Analog Outputs Preamp Analog (selectable) Preamp Analog (each channel)

Digital Output (each channel) CMOS ToT & Event Detection LVDS Event Detection

Max Count Rate 4 10∙ 6 cps 5 10∙ 6 cps

Power Consumption 3.8 mW/channel 2.7 mW/channel

Sensitivity 6 fC 2.5 fC

Max Digital Output Jitter 18 ns 6.2 ns

Gain 0.5 mV/fC 1 mV/fC

Dynamic Range From 30 fC to 1 pC From 30 fC to 500 fC

Input signal common mode 900 mV 0 mV

Reset Mode Digital Auto-Triggered or External

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Outline







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Future Perspectives

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• The design has been sent to the foundry last weeks• Expected to come back in January 2015• 40 packaged samples (Ceramic QFP 144 pins)

• In the meanwhile• Designing a GEMMA compliant read-out system (Detector Chip

Modules and Motherboard)• Setting up an irradiation test to verify the GEMMA under-radiation

performance

• The first version (GEMINI v1) has been corrected and re-sent to the foundry

• Expected to come back in a few days• Tests on first prototype should now be possible! (finger crossed)

gemma (gem mixed-signal asic): design & developing second year ph.d. activity report alessandro...

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