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Page 1: Generation Connected Markets
Page 2: Generation Connected Markets

2

JCET Confidential |

High Density Packaging Needs for Next Generation Connected Markets

2018.05.31

Urmi Ray

2

Page 3: Generation Connected Markets

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JCET Confidential |

Contents

• Industry Advanced Packaging

• System integration and COO optimization

• eWLB as high density packaging platform

• Conclusion

3

Page 4: Generation Connected Markets

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JCET Confidential | 4

System Integration Trends (1/5) 10000

1000

100

Analog Wifi

BB

PMIC

RF/RFFEM

GPU, C P U C P U + Memories

FPGA HPC Processors

+ Memories

MEMS CIS

Display Drivers

Application Processors

AP+BB

A P+D R A M

5 G M o d u l e s

2x2 5x5 10x10 15x15 20x20 >20x20 >>20x20

# o

f IO

s

Package size

Page 5: Generation Connected Markets

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JCET Confidential | 5

System Integration Trends (2/5) 10000

1000

100

Codec

P o w e r Wifi

BB

PMIC

RF/RFFEM

GPU, C P U C P U + Memories

FPGA Large Processors

+ Memories

MEMS CIS

Display Drivers

Application Processors

AP+BB

A P+D R A M

5 G M o d u l e s

2x2 5x5 10x10 15x15 20x20 >20x20 >>20x20

# o

f IO

s

Package size

Page 6: Generation Connected Markets

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JCET Confidential | 6

10000

1000

MIDDLE END

HIGH END

GPU, C P U C P U + Memories

FPGA Large Processors

+ Memories

Application Processors

AP+BB

A P+D R A M

2x2 5x5 10x10 15x15 20x20 >20x20 >>20x20

Migration from QFN->WLP

Multi –die SIP

FOWLP

Low cost substrates & MIS

100

L OW END QFN, P WLCSP FC-MIS

FOWLP Multi-die FOWLP

Single side RFFEM

# o

f IO

s

Package size

System Integration Trends (3/5)

Page 7: Generation Connected Markets

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JCET Confidential | 7

10000

1000

Codec

P o w e r Wifi

GPU, C P U C P U + Memories

FPGA Large Processors

+ Memories

MEMS CIS

Display Drivers

2x2 5x5 10x10 15x15 20x20 >20x20 >>20x20

Higher density interposer -POP

POP Module subsystem

Double sided RFFEM

Effective memory integration

Antenna in package for 5G

BB

PMIC

RF/RFFEM

MLP, Interposer POP FOWLP-POP

POP Module Subsystem

Double side RFFEM

5G Module with antenna in package

100

# o

f IO

s

Package size

System Integration Trends (4/5)

Page 8: Generation Connected Markets

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JCET Confidential | 8

10000

1000

Codec

P o w e r Wifi

MEMS CIS

Display Drivers

Application Processors

AP+BB

A P+D R A M

2x2 5x5 10x10 15x15 20x20 >20x20 >>20x20

Large Body fcBGA

2.5D TSI- SIP

High Density Fan out EMIB

BB

PMIC

RF/RFFEM

2.5D-SIP eWLB-SIP

fCBGA-H

5G Module with antenna in package for network

AA AA UDC

100

# o

f IO

s

Package size

System Integration Trends (5/5)

Page 9: Generation Connected Markets

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JCET Confidential | 9

Packaging Technology Towards 4G+/5G

\ SS MBGA w/Passive

SS MBGA SIP

DS MBGA SIP

SS MBGA SIP w/EDS

Discrete Antenna in Package

Embedded Antenna in Package

Time

Incr

eas

ed

fu

nct

ion

alit

y/p

erfo

rman

ce

De

cre

ase

d f

orm

fac

tor

Page 10: Generation Connected Markets

eWLB - high density packaging platform

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JCET Confidential |

Package Configuration (3L RDL)

Die Size 11.16 x 5.58 mm & 11.16 x 5.58 mm

PKG Size 15x15mm

Ball Composition SAC305

Ball Pitch (Bottom / Top) 400um / 200um

Die Thickness (min) 200um

RDL Stack Thickness (nominal) 39um

Package ball height/size 185um

PKG Total Thickness (nominal) 424um

Silicon Die

POP Bar

Silicon Die 1 PSV1 RDL1 PSV2 RDL2 PSV3

Solder Ball

Mold Mold

Silicon Die 2

RDL3 PSV4

RDL Stack 39um+/-10um

PSV1 4um +/- 1.0um

RDL1 3um +/- 1.0um

PSV2 5um +/- 1.0um

RDL2 4um +/- 1.0um

PSV3 6um +/- 1.5um

RDL3 8um +/- 1.5um

PSV4 9um +/- 1.5um

Bump Height (SAC305) 185um

High Density eWLB Package

11

eWLB and Fan out packages can serve as means of high density

packaging

An Example is shown here

Page 12: Generation Connected Markets

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JCET Confidential |

RDL1 Litho (2um L/S) RDL1 after Plating/Etch

• BTM CD ~ 2.03um • Sidewall Angle ~ 85o

• RDL1 thickness ~ 2.82 um • BTM CD ~ 2.34um • Sidewall Angle ≥ 85o • No undercut

Technology: Fine Pitch RDL1 – Litho, Plating and etching

12

Fine Pitch RDL Development successfully completed

Page 13: Generation Connected Markets

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JCET Confidential |

RDL2 Litho (5um L/S) RDL2 after Plating/Etch

• BTM CD ~ 5.2um • Sidewall Angle ≥ 85o

• RDL thickness ~ 4.1 um • BTM CD ~ 5.0um • Sidewall Angle ≥ 85o • No undercut

Technology: RDL2

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JCET Confidential | 14

•3L RDL Stack

•Stacked Via

Technology: 3L RDL – PSV Via Stack and RDL Stack

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JCET Confidential |

Technology: RDL 1 (2u L/S)

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Technology: RDL1 Connection – between Die 1, Die 2

Page 17: Generation Connected Markets

Conclusion

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JCET Confidential |

Micro-Electronics Industry: Paradigm Changes • Heterogeneous Integration is key enabler to solve the next decade’s

system challenges

• Diverse packaging solutions will provide customers with cost-effective solutions

• Successful product introductions will be facilitated by partnership and collaboration across supply chain partners:

• OEMs/system houses

• Design houses

• Foundries/OSATs

• Materials suppliers

• Component vendors

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JCET Confidential | 19