geneva, switzerland, 13 july 2013 synchronization architecture michael mayer, editor, g.8265, g.8275...

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Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

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Page 1: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Geneva, Switzerland, 13 July 2013

Synchronization architecture

Michael Mayer,Editor, G.8265, G.8275

Joint IEEE-SA and ITU Workshop on Ethernet

Page 2: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Overview

Architecture in ITUWhy?RequirementsSynchronization recommendation structure

General aspects of architecture in ITU-TFormal model example

Overview of key Synchronization architecture recommendations

G.8264, Physical layer frequency (SyncE)G.8265, Packet based frequencyG.8275, Packet based time/phase

Geneva, Switzerland,13 July 2013 2

Page 3: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Architecture development

RequirementsRequirements

Start here

Network Model

Network Model

Equipment specifications

Equipment specifications

DeploymentDeployment

Development of architecturestarts with Requirements

A network model is thendeveloped

Which constrains equipmentspecifications

Ensuring that deployedcomponents meet all functional requirementsfor the network application

Geneva, Switzerland,13 July 2013 3

Page 4: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Key aspects of NGN synchronizationPacket network infrastructure

Moving away from SONET/SDHBut can’t throw out existing network

New synchronization requirements wireless backhaul requirementsAir interface requirements

New methodsCES, PTP, Synchronous Ethernet

New clock structuresBC, TC, GM

Architecture helps see how all pieces fit together

Next generation synchronizationinput constraints

Geneva, Switzerland,13 July 2013 4

Page 5: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Switch Switch

CES

CES

E1 E1

ETH

ETY

UTC

E1 E1

ETH_CI ETH_CI

TDM timing

Ext.Ref.Ext.Ref.

ETH

ETY

UTC

E1 E1

ETH_CI ETH_CI

TDM timing

Ext.Ref.Ext.Ref.

UTC

E1 E1

ETH_CI ETH_CI

TDM timing

Ext.Ref.Ext.Ref.

E1 E1

ETH_CI ETH_CI

TDM timing

Ext.Ref.Ext.Ref.

G.805 FunctionalModel forCES FromG.8264

NetworkElementModel

Formal models basedon G.805

5Geneva, Switzerland,13 July 2013

Page 6: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Details of functions

Individual functions may be specified in different recommendationsMay include other aspects related to basic transport, in addition to synchronizationSome blocks may contain significant detail

Sync functions in G.781Clocks in G.8262 (e.g. EEC)Transport functions in G.8021 (Ethernet)Not all functions developed by Q13/15

6Geneva, Switzerland,13 July 2013

Page 7: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Inputs OutputsETYn_AP: ETYn_AI_Data ETYn_AI_Clock ETYn_AI_TSF ETYn_AI_TSFrdi ETYn_AI_TSFfdi

ETH_PP: ETH_PI_Data

ETYn/ETH_A_Sk_MP: ETYn/ETH_A_Sk_MI_FilterConfig ETYn/ETH_A_Sk_MI_MAC_Length

Holdover control MI

ETH_FP and ETH_TFP: ETH_CI_Data ETH_CI_Clock ETH_CI_SSF ETH_CI_SSFrdi ETH_CI_SSFfdi

ETH_FP: ETH_CI_ESMC

ETYn/ETH_A_Sk_MP: ETYn/ETH_A_Sk_MI_pErrors ETYn/ETH_A_Sk_MI_pFramesReceivedOK ETYn/ETH_A_Sk_MI_pOctetsReceivedOK

7

From Ethernet equipment specification: G.8021

Ethernet Synchronization detail

7Geneva, Switzerland,13 July 2013

Page 8: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

• Description of functional block will specify as much detail as necessary to define implementation requirements

• Ensures a high degree of interoperability is achievable using standards provided by both IEEE and ITU

Filter

ETH_ CI( ETH _FP)

ETH _CI(ETH _ TFP )

ETYn_ AI

ETH_ PI( ETHTF _PP)

ETH_ PI( ETHF _PP)

ETYn Server Specific

Replicate

MI_pFramesReceivedOKMI_pOctetsReceivedOK

MAC Length Check

MI_FilterConfig

MAC Frame CheckMI_pErrors

MAC Frame Counter

802.1AB/X protocols

802.3 protocols

MI_MAC_Length

ETH _CI_ESMC ETH_CI_Clock

…More detail can be illustrated

8Geneva, Switzerland,13 July 2013

Page 9: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

G.8264/Y.1364: Distribution of timing information through packet networks

G.8264/Y.1364 (10/2008)G.8264/Y.1364 (2008) Amd. 1 (09/2010)G.8264/Y.1364 (2008) Cor. 1 (11/2009)G.8264/Y.1364 (2008) Amd. 2 (02/2012)G.8264/Y.1364 (2008) Cor. 2 (02/2012)

G.8265/Y.1365 : Architecture and requirements for packet-based frequency delivery

G.8265/Y.1365 (10/2010)G.8265/Y.1365 (2010) Amd. 1 (04/2011)G.8265/Y.1365 (2010) Amd. 2 (10/2012)

G.8275: Architecture and requirements for packet-based time and phase delivery

Consented July 12, 2013

Current versions

Geneva, Switzerland,13 July 2013 9

Page 10: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

New Options becomeavailable

The development of a coordinated architecture allows

Network to evolveUnderstand limitationsAllow new capabilities to become availableExample follows:

Multiple frequency distribution options for wireless backhaul timing over multiple networks

Geneva, Switzerland,13 July 2013 10

Page 11: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Architecture resultsin flexibility

Geneva, Switzerland,13 July 2013 11

G.8264-Y.1364.A m d.1(10)_F12.2

M o b ileO p e ra to r A R A N

B S

C a rr ie rO p e ra to r B

(O T N )

D ire c t io n o f tim in g d is tr ib u tion

R A NN C

M o b ileO p e ra to r A

S y nc h ro n ou sE th e rn e t s ig n a l

(c a rry in g O p era to r Are feren c e)

S y nc h ro n ou sE th e rn e t s ig n a l

(c a rry in g O p era to r Are feren c e)

N e tw o rk lim its

G.8264-Y.1364.A m d.1(10)_F12.3

M o b ileO p era to r A R A N

B S

C arr ie rO p era to r B

(E th erne t)

D irectio n o f tim in g d is tr ib u tion

R A NN C

M o b ileO p era to r A

E th e rn e t s ig n a l(sy n ch ro n o us o ra sy n ch ron o u s)

S y nch ro n ou sE th e rn e t s ig n a l

(traceab le to ca rr ie rtim in g refe rence )

N e tw o rk lim its

Physical layer: Service owner provides timing

Physical layer: Intermediate carrier provides timing

Packet layer: Service owner provides timing

Page 12: Geneva, Switzerland, 13 July 2013 Synchronization architecture Michael Mayer, Editor, G.8265, G.8275 Joint IEEE-SA and ITU Workshop on Ethernet

Summary

Architecture recommendations are importantDeveloped to provide an overall framework for how technology can be deployed in a networkProvide a framework for controlled technology evolutionSynchronization related architecture documents

Provide controlled evolution of technologyEnsure high degree of interoperability of different synchronization technologiesGuidance for developing equipment recommendations to support telecom specific requirements Synchronization solutions must fit with packet traffic functions of NEsStrong linkage to Hypothetical Reference Model (HRM) developmentProvide guidance to other SDO’s

Geneva, Switzerland,13 July 2013 12