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Hidden Performance Limiters in the Signal Path
June 6 to 9, 2010
San Diego, CA USA
Gert HohenwarterGateWave Northern, Inc.
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 2
ObjectiveIdentify potential sources for hidden contributions
- parallel lines on PCBs- wiring harnesses- interposers- short coupled sections of multiple transmission lines - unused, unterminated or improperly terminated transmission lines
Examine impact of examples for these contributors- Coupled lines- Interposer- Faulty contacts- Power delivery system design and components
Provide guidance for detection and remedy of problems
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 3
Problem:S21 (f)
-20-18-16-14-12-10-8-6-4-20
0 1 2 3 4 5 6f [GHz]
dB
Target value: -3dB at 2 GHz
??
But - 4 GHz fres. Who cares?
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 4
Potential problem areas
• Coupling– Adjacent signal lines– Adjacent power lines– Adjacent sense lines
• Mismatch– Unterminated/lightly terminated DUT– Unterminated tester (power/sense)
• Resonances– Interposer pin assignments– Ceramic/DUT arrays– PCB
• PDS connections and component locations
• Discontinuities
-Vias
-non-50 Ohm sections
- interposer
- PCB loss
- DUT input
- contacts
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 5
Problem manifestations• Resonances
– Reduced bandwidth / operating speed– Reduced switching margins
• Crosstalk– Increased noise levels– Reduced switching margins
• PDS ‘weakness’– Reduced operating speed– Reduced switching margins
Consequences range from none to reduced test yield and complete probe card failure
-> loss of a sale -> loss of customer
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 6
Example problem 1:
Measured shmoo plot reveals periodic structure in the yield (red=fail, green=pass) as a function of one parameter
….a shmoo plot is a graphical display of the response of a component or system varying over a range of conditions and inputs.
Wikipedia:
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 7
Observed: Peaks in Crosstalk
Line to line crosstalk and step response plot (blue line = without crosstalk)
Site-to-site crosstalk
-90-80-70-60-50-40-30-20-10
0
0 200 400 600 800 1000
f [MHz]
dB
?
Cause: Inductance in ground path
V
ns
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 8
Common mode coupling
Line to line crosstalk impact is increased from multiple aggressors
Crosstalk
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 100 200 300 400 500
f [MHz]
dB
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 9
Site-to-site crosstalk
-90-80-70-60-50-40-30-20-10
0
0 200 400 600 800 1000
f [MHz]
dB
Common mode coupling
Line to line crosstalk and shmoo plot after design changes (blue curve)
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 10
Coupled lines
R8
C1
T12R9
R7
R6
T11
T7
T8T6
T4R4
T2
C2L2 R5
T10
Tester PCB Interposer Ceramic DUT
Most likely locations for inadvertent coupling are the PCB, the interposer and the signal distribution on the space
transformer (ceramic)
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 11
Example problem 2:Short coupled lines on the space transformer
Example: Coupled length = 1 cm
-> free space wavelength at ~33 GHz
-> on Alumina at ~10 GHz
o> quarter wavelength at ~2.5 GHz
Should I worry ?
guard trace
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 12
Coupled lines SPICE models
Insertion loss (normalized at 0 MHz) into 150 Ohm DUT
-8
-7
-6
-5
-4
-3
-2
-1
0
0 200 400 600 800 1000
f [MHz]
dB
PCB sho - DUT 100 PCB open - DUT open PCB open - DUT 150 PCB 50 - DUT 150 PCB 10uF - DUT open no coupling LTCC sho - DUT150
1) Resonances appear upon coupling
2) Increased insertion loss – energy is taken away
3) Point 2 also equates to increased crosstalk
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 13
Coupled lines model and measurement Insertion loss (normalized at 0 MHz) into 150 Ohm DUT
-8
-7
-6
-5
-4
-3
-2
-1
0
0 200 400 600 800 1000f [MHz]
dB
PCB connected open-DUT open
PCB connected 50 - DUT open
no PCB-LTCC open-DUT 150
no coupling
LTCC sho - DUT open
LTCC sho - DUT 150
LTCC open - DUT sho
Matters get worse with increasing coupling length
Probe card measurement (scale model) demonstrates impact of coupled line on insertion loss measurement
Insertion loss S21
-10
-8
-6
-4
-2
0
0 200 400 600 800 1000
f [MHz]dB
no 2nd linecpld-to line
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 14
Impact of resonances on time and frequency domain performance
While the frequency domain response shows a strong resonance, the voltage step has only small aberrations, but…….
Insertion loss model
3 GHz
Transmitted step model
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 15
Eye diagram change due to an adjacent pin open/short resonance
Noticeable degradation of an eye diagram at 6Gbps from a 3 GHz resonance*
no resonance resonance
*For resonances at lower frequencies data rates scale accordingly to lower values
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 16
Capacitive loading from devices
RC time constant and mismatch cause timing shift as well as rise time reductions
R2
T12-P2
C4 R4
T5
C11
C10 C9T9
L4C8
R11R13
C12
R12
V4
Device inputs often have pFlevel capacitances
Graph shows simulation results for a representative selection of DUT input capacitance values
dT=200ps
RT = 817ps to 971 ps
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 17
Shared resources
Capacitive loading from devices and parallel lines causes timing shift as well as rise time reductions
R1
R2
R3
R9
T12-P2
R7C7
R6C6
R5C5
C4 R4
T5
T1
T4
T6
<-Tester
Device inputs
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 18
Example problem 3:Long coupled lines, PCB
Example: Coupled length = 10 cm
-> = free space wavelength at 3 GHz
-> = on FR-4 at ~ 1.4 GHz
o> quarter wavelength at 330 MHz
Time to worry !
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 19
R7
R6
T9
T10
T11
T3
T7
T8T6
T4R4
T2
C2L2 R5
T5
Coupled lines remedy
Resonance elimination by resistive loading – even relatively large values can reduce resonance peaks
Loading can potentially be located somewhere along the offending line, not necessarily at the end
Insertion loss S21
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 20
Coupled pins
Example: Interposer - coupled length = 3 mm
-> = free space wavelength at ~100 GHz
-> = in typical socket dielectric at ~50 GHz
o> quarter wavelength at ~12 GHz
Should I worry ?
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 21
Helmholtz resonator
Transmission line, open on one end, shorted on
the other
Opportunities for open/short
circuited transmission lines exist
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 22
Consequences of an open/short pin
Measured time domain signals sent through a representative contact array (on yellow pin) show some changes as a result of an open/shorted pin (1) in the assembly:
A noticeable timing error results at the 80% level
(red curve)
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 23
Insertion loss (S21) performance with varying number of ground connections
S21 (f)
-8
-6
-4
-2
0
0 10 20 30 40f [GHz]
S11
[dB
]
12345678
S21(# gnd)
-2.5
-2
-1.5
-1
-0.5
0
0 1 2 3 4 5 6 7 8 9# G
dB
21020
Insertion loss Insertion loss change as a function of #GND at 3 different frequencies
As in the open/shorted pin scenario the impact on timing will again be noticeable
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 24
Interposer contact instabilityMeasured S21 insertion loss and transmitted step signal variations of an interposer contact
S21 (f)
-5
-4
-3
-2
-1
0
0 5 10 15 20
f [GHz]
S21
[dB
]
TDT THRU
-0.20.00.20.40.60.81.01.2
-0.05 0.05 0.15t [ns]
rho
DUTSystemDUT
There will be significant timing variations (error) at the 80% signal level
(blue vs. red curve)
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 25
Diagnostics
Phase deviation from linear can be used to examine and visualize signal path quality. It also aids in adjusting models
to the measurements.
Compensated phase
freq
deg
Measurement Model
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 26
Power Delivery System (PDS)
• Transmission lines between capacitors
• ‘Near’-die capacitance in conjunction with probe card inductance and capacitance
• Unterminated branch and sense lines
Potential sources of resonances:
L4
R5T3T2
R4
R22
C16
L19 L25
R28
C20R29
T5 T1R9
C1
R6
L3
L1
L20
R25
C19
L23
R7
R8
R13
L2
L6
L5
L7
T4
DUT Vq
Vq sense
C1
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 27
PDS resonances
Simplified PDS model SPICE simulation (with power delivery path and unterminated sense path as well as additional capacitance
very near active device)
Z pds
0
1
2
3
4
5
6
0.05 0.15 0.25 0.35f [GHz]
Ohm
sMeasured PDS impedance as
a function of frequency
(upper curve is for location in center of array)
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 28
Where is any of the above an issue ?
• At / near speed test
• Burn-in
• Increasing speeds
• Fast devices transmitting back into probe card
• Power delivery system (PDS)
• Marketing
June 6 to 9, 2010 IEEE SWTW - Hidden Performance Limiters 29
ConclusionExamples demonstrate that seemingly insignificant individual effects can compound, thereby reducing performance
Some problems may not be readily apparent during the design phase and show only during verification via measurement or on the test floor
Resonances at high frequencies can have an impact on relatively slow signals via timing errors or ringing
Verification of performance via select measurement techniques can be a valuable tool to spot potential problems