glast large area telescope: electronics, data acquisition & instrument flight software

GLAST LAT Project DOE/NASA Peer Critical Design Review, March 19-20, 2003

G. Haller 4.1.7 Elex Overview-Management V6 1

GLAST Large Area Telescope:GLAST Large Area Telescope:

Electronics, Data Acquisition & Instrument Flight Software Peer Critical Design Review March 19-20, 2003

Gunther HallerStanford Linear Accelerator CenterManager, Electronics, DAQ & FSWLAT Chief Electronics Engineer

[email protected](650) 926-4257

Gamma-ray Large Gamma-ray Large Area Space Area Space TelescopeTelescope



CDR AgendaCDR Agenda

Day 1 - March 19 (all times PST)Section 1: Electronics, DAQ, FSW Overview 8:00 – 8:40

Section 2: Management 8:40 – 9:20

Section 3: System Engineering 9:20 – 10:30

BREAK 10:30 – 10:45

Section 4: Electronics 10:45 – 12:00

LUNCH 12:00 – 13:00

Section 5: Instrument Software Overview 13:00 – 13:30

Section 6: Instrument Software I 13:30 – 14:45

BREAK 14:45 – 15:00

Section 7: Instrument Software II 15:00 – 15:30

Section 8: Instrument Software III 15:30 – 16:15

Discussion 16:15 – 17:00



CDR Agenda (Con’t)CDR Agenda (Con’t)

Day 2 - March 20

Section 9: Mechanical & Thermal 8:00 – 9:00

Section 10: Power - EMI 9:00 – 9:30

Section 11: Monitoring & Thermal Control 9:30 – 10:00

BREAK 10:00 – 10:10

Section 12: EEE Parts 10:10 – 10:40

Section 13: Manufacturing 10:40 – 11:10

Section 14: Summary 11:10 – 11:20

Discussion/Closeout 11:20 – 12:00

Adjourn 12:00



Review Board TeamReview Board Team

• Hartmut Sadrozinski/UCSC Chairman • Al Vernacchio/GSFC Co-Chairman - GLAST

Deputy Project Manager• Fred Huegel /GSFC Electrical Engineering• John Fox/SLAC Electrical Engineering -

Applied Physics• Steve Smith/SLAC Electrical Engineering –

System Engineering • Bob Jackobsen/LBL Software• Rick Schnurr/GSFC Software • Lowell Klaisner/SLAC LAT Chief Engineer• Steve Scott/GSFC Systems Engineering• Ron Zellar/GSFC Software




Electronics, Data Acquisition & Flight Software Overview






Overview OutlineOverview Outline

• Overview of LAT and Electronics• Level III Requirements Summary• Meeting Key Requirements• Flowdown – Requirements to Design• Design Evolution• Optimization• Technical Heritage• Status of July PDR Recommendation Items



e+ e–

Overview of LATOverview of LAT

• Precision Si-strip Tracker (TKR) Precision Si-strip Tracker (TKR) 18 XY tracking planes. Single-sided silicon strip detectors (228 m pitch) Measure the photon direction; gamma ID, ~880,000 channels.

• Hodoscopic CsI Calorimeter(CAL)Hodoscopic CsI Calorimeter(CAL) Array of 1536 CsI(Tl) crystals in 8 layers. Measure the photon energy; image the shower.

• Segmented Anticoincidence Detector Segmented Anticoincidence Detector (ACD)(ACD) 89 plastic scintillator tiles. Reject background of charged cosmic rays; segmentation removes self-veto effects at high energy.

• Electronics System Electronics System Includes flexible, robust hardware trigger and software filters.

Systems work together to identify and measure the flux of cosmic gamma Systems work together to identify and measure the flux of cosmic gamma rays with energy 20 MeV - >300 GeV.rays with energy 20 MeV - >300 GeV.

Calorimeter

Tracker

ACD [surrounds 4x4 array of TKR towers] DAQ Electronics



LAT ElectronicsLAT Electronics

16 Tower Electronics Modules– DAQ electronics module (DAQ-EM)– Power-supplies for tower electronics

* Primary & Secondary Units shown in one chassis

ACD

spare

EPU-3

EPU-2EPU-1

spare spare

Pwr Dist. Box

GASU

spare

spare

SIU-P SIU-R

3 Event-Processor Units (2+1 spare) – Event processing CPU– LAT Communication Board– SIBSpacecraft Interface Unit

– Spacecraft Interface Board (SIB): Spacecraft interface, control & data

– LAT control CPU– LAT Communication

Board (LCB): LAT command and data interface

Power-Distribution Unit (PDU)*– Spacecraft interface, power– LAT power distribution– LAT health monitoring

Global-Trigger/ACD-EM/Signal-Distribution Unit*

TKR

CAL

TKR Front-End Electronics (MCM)ACD Front-End Electronics (FREE)

CAL Front-End Electronics (AFEE)



Specification TreeSpecification Tree

Mission SystemSpecification

ScienceRequirem ents

Docum ent

LAT-SC InterfaceRequirem ents

Docum ent

LAT P erform anceSpecification

LA T-SS-00010

LATEnvironm entalSpecification

LA T-SS-00778

LAT IOCPerform anceSpecification

LA T-SS-00015

ACD SubsystemSpecification

LAT-SS-00016

TKR SubsystemSpecification

LAT-SS-00017

CAL SubsystemSpecification

LAT-SS-00018

Trigger & DataflowSubsystem

SpecificationLAT-SS-00019

SASSubsystem

SpecificationLAT-SS -00020

LO FSubsystem

SpecificationLA T-SS-00021

PowerSubsystem


MechanicalSubsystem


Mission

LAT

LATSubsystem

ScienceRqm ts

Miss ionRqm ts

G round System Rqm ts

Interface Rqm ts

Interface Rqm ts

TCS Perform anceSpecification

LAT-SS-00715

SAS DesignSpecification

LAT-SS -00505

CAL DesignSpecification

LAT-SS-00210

LAT TriggerSpecification

LAT-SS -00284

LAT TK R DesignSpecification

LA T-SS-00134

LA T O perationsFacility


Tower PowerSupplies


ACD DesignSpecification

LAT-SS-00352

DesignSpecification

LA T DataflowSpecification

LAT-SS-00285

LAT Flight SWSpecification

LAT-SS-00399

LAT ReadoutElectronic


LAT IOC/MOC/SSC Interface

ControlDocum ents

Radiator DesignSpecification

LAT-SS-00394

X-LAT P lateDesign


Grid Box DesignSpecification

LAT-SS-00775

LAT-SC InterfaceControl

Docum ents



Level III Key Requirements SummaryLevel III Key Requirements Summary

Adjust Input timing resolution <100 ns Test 50 nsTrigger acknowledge output Test/Demonstration Meet Requirement

TACK latency < 1.3 s Test < 1.3 usecTiming Jitter < +/- 50 ns Test < 50nsDead-time contribution < 5 s Test < 200 nsec

Acknowledge blocking Test/Demonstration Meet RequirementDead time cause Test/Demonstration Meet Requirement

Event Deadtime Report < 500 ns Test < 500 nsEvent Data Contribution Test/Demonstration Meet RequirementDiagnostics Mode Test/Demonstration Meet Requirement

Control SystemVerify commanding interface Test/Demonstration Meet RequirementGRB response Test/Demonstration Meet Requirement

Event DataReadout and overwrite protection Test/Demonstration Meet RequirementFiltering functions Test/Demonstration Meet RequirementPointing & coordinate system Test/Demonstration Meet RequirementDead-time for average orbit condition < 5% Test/Demonstration < 5% for T&DF

Monitoring & calibration Test/Demonstration Meet RequirementVolume < 0.25 m3 Inspection < 0.25 m3

< 188 kg Inspection < 188 kg

Power < 142 W (dayly average) Test < 142 W (daily average)< 330 W (peak, average over 1 sec) Test < 330 W (average over 1 sec)

Mass

ElectronicsRef: LAT-SS-00019



Level III Key Requirements Summary (2)Level III Key Requirements Summary (2)

Parameter Requirement Verification Expected Performance

28 VDC +6/- 6V Test 22 V to 37 V DC< 1000 Watts peak Test/Analysis < 750 W< 650 Watts (daily average) Test/Analysis < 650 WImpedance Analysis tbdPrimary/Redundant input power source Analysis Meet RequirementSwitching Test Meet Requirement8 primary power circuits of 14 A Analysis 2 to 5 circuitsControl Test Meet Requirement

Telemetry Telemetry monitoring internal voltage, current, and temperature

Test Meet Requirement

Output Power Supply power to Tower Electronics Test Meet RequirementSupply power to EPU Test Meet RequirementSupply power to SIU Test Meet RequirementSupply power to GASU Test Meet Requirement

Input Power

Power SystemRef: LAT-SS-00136



Flowdown – Requirements to DesignFlowdown – Requirements to Design

Parameter Requirement Constraint Characteristics Needed Design

Trigger

Adjust Input timing resolution

<100 ns Power Hardware/Firmware system Central Trigger

TACK latency < 1.3 us Mass Decision BlockTiming Jitter < +/- 50 ns Volume (Global Trigger,Dead-time contribution < 5 us Complexity located in GASEvent Deadtime Report < 500 ns Reliability Unit)

DataflowReadout and overwrite protection Power Event buffering in Front-end

electronics, TEM, GASUCentral Event Builder

Efficient Event Assembly Mass (Hardware, locatedFiltering functions Volume Hardware event assembly in GAS Unit)Dead-time for average orbit condition < 5%

Complexity of hardware versus software

Buffering for burst up to 20,000 photon events

Reliability Processor for filtering PowerPC Processor Farm

Error Recovery



Evolution of DAQ DesignEvolution of DAQ Design

Proposal Design:• No global trigger, ability to reduce hardware trigger rate from tracker marginal • Data router to move partial event fragments into central processor• Event building in software• 16 processors, one on each tower to process data • Communication to TKR/CAL/ACD systems very unique

Current Design:• Global trigger, ability to reduce hardware trigger rate from tracker• Event building in hardware• Data switch to move complete event fragments from hardware event builder to

processor• 2 processors for event processing• Communication to TKR/CAL/ACD systems unified



Optimization – SummaryOptimization – Summary

• Serial LVDS (Low-Voltage-Differential-Swing) protocol with Data, Clock, Reset, Return-Data to each front-end system and between DAQ modules (see LAT-TD-00606)

• Buffering of event data fragments at each module stage to meet dead-time requirements– TKR front-end -> TEM -> Event-Builder -> LAT

Communication Board -> CPU -> Spacecraft Solid-State Recorder

• Flow-control between buffer stages to meet non-overwriting and data consistency requirements

• Utilization of ASIC’s to meet volume, power, and cost constraints



HeritageHeritage

• Similar data-acquisition system was used on balloon flight (TEM, one event-processing CPU, one spacecraft-interface-equivalent control CPU)

• Electronics components: mostly components with flight-heritage (FPGA’s, LVDS converters, memories)

• ASIC technology same as for tracker, calorimeter, ACD systems

• Trigger, dataflow, event assembly, and event filter processing very similar to past high-energy physics experiments



Summary of July Delta-PDR ReviewSummary of July Delta-PDR Review

• “The electronics including software was already baselined at the January PDR review”

• “Work with GSFC branch to qualify poly-switches for use in the LAT electronics”– Approved

• “Ensure that FPGA design practices adhere to GSFC guidelines and recommendations for space-flight applications”– Working with Rich Katz at GSFC to review LAT FPGA

designs. In process of sending designs to GSFC for review



Summary of July Delta-PDR Review (Con’t)Summary of July Delta-PDR Review (Con’t)

• “Determine the need date for processor down-select based on software design impact”– Have selected BAE RAD750

• “Finalize the flight-software management plan and test plan”– Flight software management plan (LAT-MD-00104-02)

entered into cyberdocs 6 November 2002– Flight software test plan (LAT-TD-00786-01) entered into

cyberdocs 10 June 2002



Summary of July Delta-PDR Review (Con’t)Summary of July Delta-PDR Review (Con’t)

• “Identify solution path to replace the functionality that would have been provided by SCL COTS tool in the flight software. Coordinate with I&T and mission operations”– I&T has adopted a low level toolset (Python, Qt, XML,

MySQL) to implement the EGSE side of the I&T test environment. FSW provides the hardware drivers for the embedded system. Code already exists and is running on test stands to replace the SCL register manipulation model. FSW has adopted the I&T low level toolkit for its Test Executive.




Electronics, Data Acquisition & Flight Software Management






Management OutlineManagement Outline

• Team Leads• Team Partners• Contingency (Mass, Power, Cost)• Organization Chart• Work Flow• Testing Overview• Fabrication Plan• Schedule & Critical Path• Cost• Procurements• Configuration Management• Issues and Concerns• Summary



Team LeadsTeam Leads

• Gunther Haller– Project Manager Electronics, DAQ, Instrument Software– Chief Electronics Engineer– PCMS Schedule & Cost Lead

• JJ Russell– Instrument (Flight) Software Lead

• Mike Huffer– Data-Acquisition System Lead

• Dave Nelson– Mechanical & Thermal Engineering Lead– I&T Lead– Power/EMI System Lead

• Jobe Noriel– Packaging Engineering Lead

• Jerry Clinton– Manufacturing Lead

• Nick Virmani/Darren Marsh– Mission/Quality Assurance



Team PartnersTeam Partners

• Naval Research Lab– Spacecraft interface board (Silver Engineering)– Instrument flight software (Boot Code, SC Interface)– CAL front-end electronics

• University of Santa-Cruz– Tracker front-end electronics

• Goddard Space Flight Center– ACD front-end electronics



Contingency HandlingContingency Handling

• All contingency (Power, Mass, Cost) is held at LAT project level• Change requests to LAT Change Control Board are required to

account for variance• 4.1.7 Changes which required increase in cost, mass, power:

Change Request # Description StatusLAT-XR-01242 Flight Software

Labor Increase (SLAC)

Approved

LAT-XR-01753 Flight Software Labor Increase (NRL)

Approved



Organization ChartsOrganization Charts

Section 7.4 Elec, DAQ, Flt SW Overview

ReliabilityD. NelsonSU-SLAC

WBS 4.1.7.2

Quality AssuranceD. Marsh/N. Virmani

SU-SLAC/NRLWBS 4.1.7.2

DAQM. HufferSU-SLAC

WBS 4.1.7.4/4.1.7.5

Enclosures/HarnessM .FreytagSU-SLAC

WBS 4.1.7.7/4.1.7.8

Power SystemD. NelsonSU-SLAC

WBS 4.1.7.6

Instrument SoftwareJ. RussellSU-SLAC

WBS 4.1.7.9

GSE & OperationM. HufferSU-SLAC

WBS 4.1.7.A

Instrument I&TG. HallerSU-SLAC

WBS 4.1.7.C

Tracker ElexWBS 4.1.4

CAL ElexWBS 4.1.5

ACD ElexWBS 4.1.6

Front-End ElexG. HallerSU-SLAC

Electronics, DAQ & Flight SoftwareG. HallerSU-SLACWBS 4.1.7



Development Testing LAT SystemDevelopment Testing LAT System

• Processor: Motorola Power-PC• Flight Software• LAT COM engineering modules for

– LAT Communcation– Trigger

• TEM DAQ Assembly• TEM Power-Supply Assembly• 28-V Supply• LAT-TD-00861

Tower Power Supply Assembly

(1.5V/2.5V/3.3V/ 0-100V/0-150V)

TEM DAQ Assembly

COM-card 1: LAT Communication Module

COM-card 2: Trigger Module

28-V Power Supply

Power-PC Processor

Flight Software



Testing PlanTesting Plan

• ASIC’s are 100% acceptance tested before assembly on boards– Radiation performance is lot

tested for single event effects and total ionizing radiation.

• Function/Performance is tested at the board level

• Qualification and acceptance tests including performance, vibration, EMI/EMC, and thermal vacuum are performed at the component sub-assembly (box) level.



Fabrication PlanFabrication Plan• ASIC’s

– Design: SLAC– Fabrication: Agilent– Packaging: ASAT

• Printer-Circuit Boards– Design:

• Spacecraft Interface Board: Silver Engineering

• All other DAQ custom modules: SLAC– Fabrication: qualified vendor– Parts procurements: SLAC– Assembly: qualified vendor

• Enclosures– Design: SLAC– Fabrication: qualified vendor

• Module Assembly (PCB’s/cables/enclosure)– Design: SLAC– Assembly: qualified vendor

• Tower Power Supplies– Circuit & board design, fabrication,

assembly: qualified vendor– Enclosure design: SLAC– Assembly: qualified vendor

• Harness– Design: SLAC– Assembly: qualified vendor

• Installation at SLAC



Work FlowWork Flow

TEM DAQ Assembly

TEM DAQ BoardGCCC, GTCC ASICs TEM DAQ Enclosure

TEM PS Assembly

TEM PS Board

TEM Power Supply Enclosure

GASU Assembly

GASU DAQ BoardGLTC ASIC

GASU Enclosure

PDU Assembly

PDU DAQ BoardGLTC ASIC

PDU Enclosure

SIU Assembly

SIB Board

Crate Enclosure

LCB Board

CPU Board

PS Board

EPU Assembly

Harness

TEM Assembly

LAT Integration 1st stage

Acceptance Test

Acceptance Test

Acceptance Test

Acceptance Test

Acceptance Test

Acceptance Test

GLTC ASIC

Acceptance Test

LAT Integration 2nd stage

LAT Integration 3rd stage

First layer DAQ modules

Second layer DAQ modules

Add Harness

Software Acceptance Test



Key MilestonesKey Milestones



Key Milestones



Critical PathCritical Path

• TEM DAQ Assembly– Flight TEM DAQ PC Board fab and loading Feb 04

• Requires flight TEM ASICs • Tower Power Supplies

– Flight assemblies by March 04• Is out for RFP, expected back March 25

– Depends on vendor response



Cost by Fiscal YearCost by Fiscal Year

FY00in K$

FY01in K$

FY02in K$

FY03in K$

FY04in K$

FY05in K$

Totalin K$

692 930 1,727 7,013 4,097 1,281 15,737

• W.B.S. 4.1.7 without contingency



Cost Contingency and ScheduleCost Contingency and Schedule

Item In k$

Budget at Complete (a) 15,737

Contingency at Start* 2,830 18% of (a)

Budgeted Cost for Work Scheduled (b) 4,206

Budgeted Cost for Work Performed 4,148

Actual Cost for Work Performed 4,238

Cost Variance -90 -2.1% of (b)

Schedule Variance -48 -1.1% of (b)

• Status below is as of Jan 31-03

*contingency is held at project level

• Software-specific contingency: see Instrument Software presentation



Manpower PlanManpower PlanFT

Es

4.1.7 Electronics



ProcurementsProcurements

• Long-Lead Procurements– Tower power supplies (RFP close March 25)– Processor (RFP in April)– Voltage regulators (after CDR)

• Major Upcoming Procurements Near-Term (< 4 months)– FPGA’s– Connectors– MOS Transistors– DC/DC Converters & Filters– ASIC’s

• Major Upcoming Procurements Long-Term (>4 months)– Enclosures– Harness

• Minor Upcoming Procurements– Miscellaneous electrical components



Configuration Management and Information Configuration Management and Information TechnologyTechnology

• SLAC CM System– Cyberdocs (web-based document storage): Electronically

stored documents, drawings, procedures, Work-Order-Authorization (WOA’s)

– Risk Item Database– Document Library

• Electronics, DAQ, Flight Software web-site– http://www-glast.slac.stanford.edu– Website is used to share information and store draft

documents, – Directly access CM documents stored in cyberdocs

http://www-glast.slac.stanford.edu/



Issues and ConcernsIssues and Concerns

• Schedule is very tight– Critical path has little room for delay

• Dependency on delivery of procured items



SummarySummary

• Technically the electronics and instrument software are on track

• Schedule and budget plan are fully in PCMS down to level 7 since PDR, both are on track

• Critical path and contingency analyzed• No unusual risks besides risks of any high-energy physics

experiment and space flight instrument• Testing, fabriation, and workflow plans in place• Experienced management and technical team

glast large area telescope: electronics, data acquisition & instrument flight software

Documents