going beyond risc-v general purpose solutions · security was always an afterthought in computing...

InCore Semiconductors

Going beyond RISC-V General Purpose Solutions

Neel Gala

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RISC-V Workshop @ Chennai ‘18


Genesis of InCore Semiconductors

▪ InCore Semiconductor is founded by members of the Shakti Research team to create commercial RISC-V solutions leveraging the Shakti Open Source IP and research efforts.

▪ Focus is on AI/ML, Security, IoT Wireless and Fault Tolerant applications.

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Computing - The Way forward▪ The challenge till recently was performance/area improvements.

▫ But the free lunch of node improvements has ended and OO micro-arch improvements have also reached their limit.

▪ Performance improvements can now come only using domain specific architectures. AI/ML are probably the domains that matter the most.

▪ Security was always an afterthought in computing but that no longer can be the case since computing is too integral a part of our day to day lives for it to be optional.

▪ And computing has to be reliable if our increasing reliance on computing does not come to a grief.

▪ The future is in processors enhanced for AI/ML computation, designed from ground up to be secure and reliable.

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The Relevance of AI/MLComputing is increasingly moving to the edge. In sheer numbers, computing will reside mostly in the edgeWith devices like Amazon Echo/Google Home and AI enhanced mobile devices, AI/ML compute is becoming the dominant narrative in IoT and edge devicesAutomotive systems are also dependent completely on AI/ML for autonomous functions, the dominant theme in that segment.

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Intelligence is a Major Concern


Security is now center stageWith the growth of IoT today, new challenges have risen

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IoT devices have now encroached into critical compute domains: banking, payment gateways, real-time data monitoring

These compute platforms need to provide guarantees of security and privacy of data.

Security is a Major Concern


The Reliability ChallengeWith more electronics entering the medical, industrial , aerospace and transportation sectors, it is imperative that the devices and processors used here are highly-reliable and capable of error-recovery.Reliability can no longer be traded-off for area and performance.

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Reliability is a Major Concern


Rethinking Processor Design

▪ Intelligence, Security and Reliability need to be treated as first-class citizens while designing solutions today.

▪ These features need to be present inherently in all devices redefining the very notion of general purpose solutions

▪ The current approach is to attach “add-ons” to existing processors. The core processor design remains constant.

▪ This approach does not scale well because what is really required is a ground-up rethink of processor architecture.

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The InCore Strategy▪ Establish leadership across the RISC-V core spectrum

for edge devices.▫ From ultra low power IoT to Desktop.

▪ Leverage these cores to bring AI/ML, Security and Reliability to center-stage.

▪ Leverage RISC-V to establish leadership in new markets.

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We do have a Plan !!


The InCore Strategy

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Enhanced General Purpose Cores

Intelligence Enabled

Cores

Security Enabled

Cores

Reliability Enabled

Cores

Edge is where the Action is !


Foundation Core 1 : E-ClassOverview▪ In-order 3 stage 32/64 bit microcontroller

supporting a subset of RISC-V ISA. ▪ Low area and power consumption -

operational freq. of <200MHz on silicon.▪ Optimized variants for FPGA based

soft-cores.▪ AXI4/AXI4-Lite/TileLink peripherals

supported▪ Positioned against ARM’s M class cores

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Specifications▪ Open source IP supporting RV*IMAC▪ Push button flow to generate variants and

subsets of ISA supports▪ Optimized sequential Multiplier and Divider

for ASICs and FPGAs ▪ OpenOCD based SoC debug support.▪ 64-bit core uses <3K LUT on a 7-series Xilinx

FPGA▪ OS Ports: FreeRTOS

Target Domains: IoT devices, Edge Devices, Robotic Control, Smart cards


Foundation Core 2 : C-Class

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Overview▪ An in-order 5-stage 64-bit microcontroller

supporting the entire stable RISC-V ISA.▪ Dual issue support for high performance

variants▪ Targets mid-range compute systems:

200-800MHz. (can be customized for 2 Ghz applications)

▪ Supports RISC-V Linux, secure L4▪ Variants for low-power and

high-performance.▪ Positioned against ARM’s Cortex A35/A55

Specifications▪ Supports RISC-V ISA: RV64G.▪ Compatible with latest privilege spec of

RISC-V ISA and supports the sv39/48 virtualization scheme.

▪ Supports the OpenOCD based debug environment.

▪ Includes a High performance branch predictor with a Return-Address-Stack.

▪ Caches: 16-64KB non-blocking pipelined Instruction and Data caches. Optional L2.

Target Domains: Reliable Computing, Secure Computing, IoT & Edge Computing hubs, Auto/Aerospace/Industrial Controls


AXON SeriesIntelligence Enabled Cores

InCore Semiconductors13

Accelerating Sparse Models

Real-Time Guarantee

Custom HW Accelerators

AXON


Sparsity Aware Extensions▪ Low end Edge-Devices are resource constrained.▪ Workloads in these scenarios will have sparse characteristics.▪ Incore’s sparsity aware cores leverage this behaviour.▪ We provide customized hardware to accelerate sparse

computations:▫ Specialized data-structures which enable skipping

redundant operations from being fetched [1].▫ Provides energy reduction

▫ Optimized Cache-hierarchy to leverage sparsity further.

[1] “SparCE: Sparsity aware General Purpose Core Extensions to Accelerate Deep Neural Networks”, Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan

https://arxiv.org/search?searchtype=author&query=Sen%2C+S

https://arxiv.org/search?searchtype=author&query=Jain%2C+S

https://arxiv.org/search?searchtype=author&query=Venkataramani%2C+S

https://arxiv.org/search?searchtype=author&query=Raghunathan%2C+A


Sparsity Aware Extensions


Light-Weight Systolic Arrays▪ Mid-range IoT devices employ regular workloads.▪ Applications in these scenarios also need a hard

time-bound on the execution pattern▪ InCore integrates its cores with a light-weight customized

systolic arrays▫ Follows a data-flow architecture.▫ Can be integrated to any base risc-v core through a

common native interface.▫ Uses open-source TVM software stack to support

common modelling platforms like Caffe, TensorFlow, etc.


Light-Weight Systolic Arrays

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Hard Real-Time Guarantees▪ Time Guarantees are a growing concern with AI/ML

solutions being deployed in life-critical systems : autonomous cars, avionics, etc.

▪ InCore provides a complete SoC subsystem comprising of:▫ A RISC-V core running sel4 with time-guarantees▫ An AI accelerator with time-guarantees▫ A software framework to evaluate and customize

SoC for variable real-time requirements


AEGIS SeriesSecurity Enabled Cores


Side-Channel Mitigation

Tagged Architectures

Standard Secure Designs

AEGIS


Side-Channel Mitigation (Power)Power based side-channel attacks are common today.The aim is to identify micro-architectural limitations which lead to such vulnerabilities.Our Solution:▪ Methodology to identify heat signatures of various

modules using Hamming-distance as metric. ▪ Identify blocks/modules from heat-maps which are

potential data leakage sites.More info by Arsath tomorrow @ 10am

21Work done by Prof. Chester and Mr. Arsath at IIT-Madras


Standard Secure Design Techniques

▪ Crypto accelerators▫ AES, SHA2, etc.▫ ISA extensions to provide low overhead performance

boost for crypto-applications. ▪ Standard Secure Design Strategies:

▫ Secure Boot.▫ Memory Protection.▫ Tamper Detect mechanisms.▫ Trusted Execution Environment

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Tagged Architectures

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Lightweight Tags● Preventing all manifestations of spatial

and temporal memory attacks.● A one bit tag is associated with every

memory word which indicates if the word is a pointer or not

● Make all pointers as fat pointers, and associate a base and bound with them (with one level of indirection)

○ The associated base and bounds are used to validate all memory accesses

Micro VMs● Tag based isolation of functions and

code blocks● Semantics of a stripped down VM with

cost of a function call● Lightweight context isolation● Minimal or zero changes to compiler● Easy addition of new protection

mechanisms.


Lightweight Tag Micro-Arch

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TCU: Tag Computation Unit SEU : Security Execution Unit


AEON Reliability Enabled Cores


Lock-Step Cores

Fault Tolerant FabricsRESO

AEON


Reliability Enabled Cores

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Variants of our C-Class cores with the following extensions:

● SECDED: Single error correction and Double error detection logic for each combo-circuit. ECC for memory structures such as register files, pipeline fifos, TCMs, etc.

● RESO: To detect and mitigate single error upsets due to radiation or environmental effects, we propose to use recompute methodology for certain critical compute blocks. This explores the temporal redundancy paradigm. We shall also add a TMR structure to certain components to provide modular redundancy.

● Redundant Bus: To use multiple fault-tolerant bus architectures to mitigate single-error upsets while transmissions on the high speed buses.

● Lock-Step Multi-core: Idea is to have multiple cores execute the same application/software perform comparison at the core level.

Additional analysis on the design process side in terms of power supply redundancy, rad hard process, high reliability memory will also be carried out for a particular variant


Reliability Enabled CoresFault Tolerance within ALU:

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Re-Computation Techniques:▪ Adder/Subtractor:

▫ Complement of operands with Carry set are given as inputs.

▪ Multiplication : ▫ complement only the 1st

operand. Result of complement of original result.

▪ Many more techniques:Sukrat Gupta et. al.. 2015. SHAKTI-F: A Fault Tolerant Microprocessor Architecture. In Proceedings of the 2015 IEEE 24th Asian Test Symposium (ATS)


Reliability Enabled Cores

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Sukrat Gupta et. al.. 2015. SHAKTI-F: A Fault Tolerant Microprocessor Architecture. In Proceedings of the 2015 IEEE 24th Asian Test Symposium (ATS)


Contact Info

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For more info on InCore Semiconductors

[email protected]


Challenges in Next Gen Computing [remove]

▪ Evolution of processors from 1970 to 2000 had been tremendous:▫ Key improvements have been in area and performance.▫ Area efficiency has been obtained primarily through shrinking technology

nodes - “The free lunch”▫ Core optimizations were primarily focused on providing better

performance. Faster speed again was a free-ride.▪ Power soon became a huge issue:

▫ For lower technology nodes dynamic power exceeded leakage power.▫ Several techniques were introduced to tackle Power

▫ Multi-Core computing.▫ Stochastic and Approximate Computing.▫ Power Aware application scheduling.

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Intelligent Bots▪ Plenty of undergrad courses use Robotic Platforms to teach

embedded systems (programming, architecture, etc.)▫ E-Yantra Initiative: www.e-yantra.org

▪ With growth of AI, intelligence needs to be embedded in bots as well. ▫ Enable students to leverage AI stack on small platforms.

▪ We are building an FPGA based board to serve the same purpose:▫ The FPGA is enabled with E-Class/C-Class.▫ Accelerators like systolic arrays, sparse computation units,

smart DMA, etc. will be available for off-loading AI tasks.▫ These can be integrated with Core through Bus or native

interfaces.▪ The software tool-chain for development will be open-source.▪ Enables development of HW accelerators for custom workloads.

http://www.e-yantra.org

going beyond risc-v general purpose solutions · security was always an afterthought in computing...

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