gps controler

8/8/2019 GPS Controler

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The STA2051 GPS Controller

Steve SuttonMarketing Manager GPS and

Navigation

STA2051 2-Chip GPS Solution

12 Channel GPSDSP Hardware

UARTS/BSPI/I2C

Programmable Memory Interface

Interrupts

Gyro

Single chip

GPS Radio(STB5610 orSE4100L)

XTL

256KB FLASH

RTC/ Oscill

JTAG

ARM7TDMI

16/32 bitRisc Core

InterruptController64KB SRAM

CAN

12 bit A/D

Smart Card i/f

Multi Media Card i/f

Timer/Counter/PWM

HDLC

USB

Low PowerController

GPIO

Telepass/TollingWatchdog

Wakeup

Watchdog Enable


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STA2051 Top Level Features

Features CMOS M8T 0.18um Technology 60MHz ARM7TDMI 16/32 bit RISC CPU 12 Channel GPS Correlation DSP Complete Embedded Memory System

FLASH 256K bytes +16K bytes (100K erasing/programming cycles)

RAM 64K bytes. Large array of Peripherals and General Purpose I/O 2 package options

TQFP144 TQFP64

External Memory Interface (144pin Only) -40 C to +85 C operating temperature range

STA2051 Power Supply Modes

Power Supply: 2.7V to 3.6V operating supply range for Input/Output

periphery 3V to 3.6V operating supply range for A/D Converter

reference 1.8V operating supply range for core supply provided either

by internal Voltage Regulator with external stabilizationcapacitor,or by external supply for higher power efficiency.


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STA2051 Clock Strategy

0-66 MHz internal clock frequency managed by a Reset andClock Control Unit

The unit is able to provide low power modes(WAIT,SLOW,STOP,STANDBY) and to generate the internalclock from the external reference through integrated PLL.

STA2051 Power Consumption

Power consumption STA2051 Working condition approx. 35mA @16MHz

Assumes operation from internal memory WFI Mode @ 1 MHz ~ 5 mA Low Power WFI Mode @ 32 KHz ~ 500 uA Stop Mode ~ 200 uA Stand-by Mode ~ 20 uA


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STA2051 GPS Correlation DSP 12 Independent Channels

2 Correlators/Channel, One In-Phase and One Quadrature

Fast Acquisition mode 1KHz for tracking 16KHz for acquisition

Numerically Controlled Oscillator (NCO) for fine tuning No TCXO Required Differential Ready

Support for RTCA-SC159 WAAS/EGNOS/MSAS Software readable timebase registers

PRN output for testing or optional external correlators HW driven One Pulse Per Second (1pps) output accurate to +/- 50ns

1 Pulse Per Second On STA2051


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STA2051 External Memory Interface 4 separately configurable external memory regions (Banks)

Corresponding to 4 available chip selects (CSn.0,..,CSn.3) Support for mixed memory, ROM, FLASH, SRAM.

Each Bank uses all 24 bits of A [23:0 ] addressing up to 16 MBytes of external memory space each

bank Total external memory space of 64 Mbyte

Programmable timings Up to 15 configurable wait states for each external memory

region.

8/16 bit bus width (software selectable) External memory transfers are configurable to be 8,16 or 32-

bit wide (multiple cycle access) to 8/16 bit external memorydevices.

STA2051 System Boot Modes Four Different Boot Modes available

USER Mode BOOTEN = 0, BOOT[1:0] = Dont careOR BOOTEN = 1, BOOT1 = 0, BOOT0 = 0

Standard mode of operation All user FLASH sectors visible Boot-FLASH sector not accessible

BOOT Mode BOOTEN = 1, BOOT1 = 0, BOOT0 = 1 Wake up in BOOT Mode when FLASH first programmed

eg in the manufacturing line Boots from internal RAM after config. code (EMBALGO)

executes from reserved BOOT-FLASH sector.

Allows the internal RAM to be programmed via a UART. Necessary to use this mode to program at least one Flash

sector with a boot code including in-system boot-loader, toallow a normal system start-up or ISP in user mode.


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STA2051 System Boot Modes

RAM Mode BOOTEN = 1, BOOT1 = 1, BOOT0 = 0

In RAM mode the system boot is performed from theinternal RAM,which is also visible at address 0h (seeBOOTCONF register).The Ram must be pre-loaded bythe user,for example through the Development System(MultiICE or equivalent).

EXTMEM Mode BOOTEN = 1, BOOT1 = 1, BOOT0 = 1 In EXTMEM mode the system boot is performed from the

external memory,block 0 (CSN0 is activated).Theexternal memory is also visible at address 0h (seeBOOTCONF register).

STA2051 System Services

Real Time Clock Module Real time clock module with 32KHz low power oscillator and

separate power supply to continue running during stand-by

mode.

Watchdog Timer Module 16-bit Watchdog Timer with 8 bits prescaler for system

reliability and integrity.

Wake-up Unit Wake-up unit allows exiting from power down modes by

detection of an event on one external pins or on internalReal Time Clock alarm


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STA2051 System Services

Timers

Four 16-bit programmable Timers with 7 bit prescaler up to two input capture/output compare one pulse counter function one PWM channel with selectable frequency each.

Enhanced Interrupt Controller supports 2 interrupt vectors, independently maskable, with

interrupt vector table for faster response and 16 prioritylevels,SW programmable for each source.Up to 2 maskableinterrupts may be mapped on FIQ.

STA2051 Peripherals

General Purpose I/O 48 programmable General Purpose I/O, Each pin programmable independently as digital input or

digital output 40 (30 in TQFP64) are multiplexed with peripheral functions 16 can generate an interrupt on input level/transition.

CAN Module CAN module compliant with the CAN specification V2.0 part

B (active). The bit rate can be programmed up to 1 MBaud.


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STA2051 Peripherals A/D Converter

4 channels 12-bit sigma-delta Analogue to Digital Converter

single channel or multi channel conversion modes single-shot or continuous conversion modes sample rate 1KHz (4 KHz when single channel) conversion range 0-2.5V.

UARTs Three UARTs allow full duplex, asynchronous,

communications with external devices

independently programmable TX and RX baud rates up to625K baud. One UART adapted to suit Smart Card (SC) interface needs,

for asynchronous SC as defined by ISO 7816-3; it includesSC clock generation.

STA2051 Peripherals

Serial Peripheral Interfaces Two Serial Peripheral Interfaces (SPI) allow full duplex,

synchronous communications with external devices

master or slave operation max baud rate:8Mb/s. One SPI may be used as Multimedia Card interface.

I2C Interfaces Two I2C Interfaces provide multi-master and slave functions support normal and fast I2C mode (400 KHz) 7/10 bit addressing modes

One I2C Interface is multiplexed with one SPI so either2xSPI + 1xI2C or 1xSPI + 2xI2C may be used at a time.


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STA2051 Peripherals

USB unit V1.1 compliant Software configurable endpoint setting USB Suspend/Resume support (TQFP144 only)

High Level Data Link Controller (HDLC) unit supports full duplex operating mode NRZ, NRZI, FM0 and MANCHESTER modes internal 8bit Baud Rate Generator

GPS Terms Almanac

The database of the complete system, satellite orbits, ionosphere,health, utc offsets.

Transmitted continuously, repeated every 12.5 minutes

Updated dailyvalid 2 weeks for acquisition aidingvalid 6 months for satellite selection

Ephemeris Accurate database of the orbit and clocks for the transmitting

satellite onlyTransmitted continuously in subframes 1,2,3

Repeats every 30 secondsUpdated every 1 or 2 hours


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GPS Terms Cold Start

As when equipment is first manufactured

No Almanac, Ephemeris, time of day or position estimates

Warm Start Starting with Almanac and time of day No accurate time, no Ephemeris in memory Estimated position

Hot Start

Starting with Ephemeris data already loaded

GPS Terms

Re-Acquisition After a tunnel or similar blockage Position is known to a few 100 metres Clock is not interrupted

TTFF Time To First Fix in each of the previous cases


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STA2051 GPS Performance12 Channel fully Parallel receiver, with carrier phase tracking,

differential and WADGPS facilities Accuracy

With SA 100m (16m RMS)

Without SA 3m 95% Horizontal5m 95% Vertical

Time To First Fix (TTFF) Typical Cold start (no data in memory) 90 Seconds Power Down Start

Data in memory Under Test Warm start 30 40 Seconds

Find first satellite 0.5 Seconds

Find Rest 0.5 Seconds Download time 30 40 Seconds

Hot start, no download time 3 Seconds Obscuration recovery 2 Seconds (150ms internal)

STA2051 Sensitivity

Current STA2051 SW tuned for automotive applications Acquire first satellite @ 41dB C/No

Acquire following satellites @ 33dB C/No Track down to 25dB C/No

New release of software currently under development Improvements to acquisition of first satellite

Acquire first satellite @ 35db C/No High Sensitivity SW written and under test

Sensitivity Management SW currently under development Try normal sensitivity/fast mode first Switch to high sensitivity if fast mode time-out User selectable


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STA2051/ST5610 Sensitivity vsSample rate vs Integration time

ST GPS Software The Complete Solution

Represents a complete implementation of a GPS receiver Digital signal processing GPS positioning maths Handling for differential corrections Management and I/O processes

Customer Choice 2 levels of license available

Binary Object code (libraries)


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STA2051 Development tools

SW Toolset ARM Real View Developer Suite US$6750

Host Interface ARM Real View MultiICE US$3500

STA2051 Low Cost Development tools

Rowley Associates (www.rowley.co.uk) SW Toolset

CrossWorks for ARM US$795

GNU based toolset, includes: Compiler, Debugger, Linker, Editor etc.

Host Interface Wiggler in place of MultiICE

Macraigor Systems OCDemon (US$150) www.macraigor.com, www.ocdemon.com,

www.ocdemon.net

ACM Microsystems 60 www.acm-micros.com

Can debug from Flash


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GPS RF ICs for STA2051 Currently 2 options:

ST Microelectronics STB5610 Single Chip GPS radio Mature stable design in Hi-Speed Bi-Polar Fully automotive qualified Recommended for all automotive applications Fully supported by ST Microelectronics

SiGe Semiconductor SE4100 Low power Single Chip GPS radio Ultra Low power design in Silicon Germanium process

Not Automotive qualified Recommended for applications where ultra-low power

consumption is paramount e.g. Hand held portable applications Supported by SiGe Semiconductor

STB5610 Block Diagram

Discrete IFfilter

DualgainLNA

DCK

Q

PLL ~1.55GHz

20MHz

SAWFilter

RF Amp. Mixer Lim.amp.

Discrete IFfilter

Lim.amp.

D LatchOutput buffer

VCO

External Tank

1.57GHz

FrequencySelect.

GainSelect

.

Power Down 1 Power Down 2LoopFilter

Data@4 MHzCMOS levels

CLK@16MHzCMOS levels

Pure Si Bipolar TechnologyTQFP48 Package


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STB5610 Features and Benefits

Features

Min Supply Voltage = 2.7V

Switched gain LNA

16.368MHz Crystal

Integrated Local Oscillator

Active current ~35mA

On chip VCO/PLL circuitry

Separate CE pins for clock and Signal

Resulting Benefits

Compatible with Portable applications

Support for Passive or Active Antennas

Support for standard crystals or TCXOs

Reduced Bill of materials

Reduced power consumption

Reduced Bill of materials

Allows Interval mode for very low power

STB5610 Status

Maturity Level 29 Pre-Production

Datasheet available

BOM available

Application schematic available

STB5610/STA2051 Reference Design available


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GPS RF DOWN CONVERTER ROAD-MAPcompatible with ST GPS correlators

STB5600Bipolar

technology

1996 2004

STB5610Bipolar

technology

20022000

3V DiscreteGPS radio

design

1998

STB58xx

STB56xxBiCMOS/CMOS

technology

I n

t e g

r a

t i o

n

SE4100L Single Chip GPS RF

SE4100L: Single Chip GPS RF using SiGe process

Fully compatible with ST Microelectronics STA2051

Excellent BOM Cost Power Consumption Size Ease of use


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SE4100L Block Diagram

~

PhaseDet.

~

~

~

96

Quadrature 2

I Q+45?/ -45

~

QClk D

MixIn L N A O u t

LNAIn LNA

Xtal1

Xtal2

O s c E n b

XtalOscillator

R x E n b

VCO

C l k O u t

DataOut

PhaseShift /

Combiner

D-type

IF FilterMixersRF Amp

Vtune

AntDetP

AntDetN

AntOK

Ant currentmonitor

L o w

G a i n

SE4100L Features

On-Chip LNA 1.9dB NF allows direct

connection to passiveantenna

Filtering No SAW No LC BPF

RF PLL components on-chip No resonator No varactor No off-chip LO components

No EMC issues! All in a 4mm x 4mm LPCC

package

DigitalOut

Clock Out

LNA

OptionalSAW Filter

VCO

RFAmp

DFF

LPFPDXTALOSC

96

+45/ -45

BP Filter

+45/ -45ActiveAntennaDetect


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SE4100L Integration with STA2051

PCB Passive Antenna

Remote Active Antenna

SE4100LRF

STA2051Baseband

Clock 16.368MHz

Data 16.368Mbit

Antenna OK

Antenna Switch

NMEA

Vcc

Power Control

Regulator/Switch

SE4100L + STA2051 Example PCB

9 15V supply Twin UARTs

NMEA and debug Battery-backed RTC Flash upload JTAG for software

development Phantom antenna power over-

current protection


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SE4100L + STA2051- THE Low Power Solution

- SE4100L + STA2051 designgives low power withoutcompromising performance

- Typical RF supply current10 mA @ 3V Including on-chip LNA

- Typical Baseband supplycurrent 16mA @ 3V

- True 2-chip design with internalmemory

No off-chip memory buses- Ideal forPDA / laptopCellularTracking & Security

0

10

20

30

40

50

60

70

80

S u p p l y c u r r e n

t @ 3

V ( m A )

Baseband

RF

SiRFMotorola Valence+ Sony

SiGeSiGe++

STST

Applications Support

SE4100L example RF schematic and PCB layoutprovided by SiGe

STA2051 example schematic and layout providedby SiGe in conjunction with ST Microelectronics

GPS SW support provided by ST Microelectronics


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SE4100L Availability and Sampling

Demo PCBs available May 2003 1 10 off samples available now to active developments Pre-production sampling September 2003 Production available December 2003

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