graduate institute of electronics engineering college of

國立臺灣大學電機資訊學院電子工程學研究所

博士論文

Graduate Institute of Electronics Engineering

College of Electronics Engineering & Computer Science

National Taiwan University

Doctoral Dissertation

應用電感耦合型電漿蝕刻且與 CMOS製程相容之微機電

微波濾波器及生醫遞送藥箱

Micromachined Microwave Filter and Biomedical Drug

Delivery Box Using CMOS-Compatible ICP Deep Trench

Technology

黃本立

Pen-Li Huang

指導教授﹕呂學士博士

Advisor ﹕Dr. Shey-Shi Lu

中華民國 100 年 12 月

December, 2011

致謝

來自許多人的協助，使得此博士論文得以完成。首先，感謝我的指導老師呂

學士教授，給本立機會進入電子所，在這幾年的研究過程中，沒有老師給予學生

實驗室全部的支援，本立是無法進行任何研究，更遑論完成學位。

感謝林佑昇教授，在這不算短的修業過程中，給予學生撰寫論文上的協助。

感謝孫台平教授、楊燿州教授、邱弘緯教授以及汪濤教授，能在百忙之中，抽空

來擔任學生的口試委員，感謝你們給予學生論文上許多的寶貴意見，讓我的論文

能更加的完整。

在此感謝實驗室歷屆學長及學弟妹，仿拂還記得你們的容貌，記得幫助過我

的你們，真誠的謝謝你們。此外，感謝毓傑、柏宏以及信宏，沒有你們的協助，

我無法達成畢業門檻；宥佐，謝謝你在這幾年的支持與幫助。亦師亦友的汪濤，

沒有你的技術傳承及協助，絕對無法走完全程。實驗室的冠廷、芳仁、憲穀、建

宇，將使用設計電路的經驗分享給我，讓我的晶片可以實現；應力所北區微機電

中心的魏博、蕭博、張博以及其他同仁，謝謝你們友情相助，讓我施做後製程時

獲得更多資源。最重要的是，感謝老師，是您給本立機會，得以認識你們，這

是我的福份。

感謝我的內人，綾娟，在攻讀博士學位期間，給予我最大的支持，照顧兩個

還算可愛的柏諭、律誠小朋友，讓我完成學業。感謝我的弟弟，治立，幫我分擔

照顧雙親。還有感謝我的父母，給我的教育，讓自己一路走來，能依循正途，不

致行為偏差，成就今日的本立。

最後，感恩老師及陪我走過這段過程的所有人，謝謝你們。

應用電感耦合型電漿蝕刻且與

CMOS製程相容之微機電微波濾波器及生醫遞送藥箱

研究生: 黃本立指導教授: 呂學士博士

國立台灣大學電子工程研究所

摘要

將以電感耦合型電漿蝕刻為主，利用微機電矽基板蝕刻技術(深槽技術)，應

用於CMOS微波被動元件，特別是高頻微波濾波器，以檢驗其相容性與功效。實驗

結果顯示，藉由深槽技術將CMOS元件底下具有損耗性的矽移除之後，該濾波器

insert loss相較於未施作深槽技術之濾波器為佳。

除了上述被動元件外，基於考慮先進CMOS製程過於昂貴，藉由摺疊設計四分

之一波長之被動濾波器來減少濾波器的面積，並設計工作頻率在V頻段之濾波器，

並可藉由分別改變金屬-絕緣層-金屬電容的重疊長度調整該電容值，控制低頻傳

輸零點，以及改變L-C共振腔與濾波器地端的間隔調整高頻傳輸零點，形成V頻段

帶通濾波器，再以深槽技術將CMOS元件底下具有損耗性的矽移除，使得該濾波器

的輸入損耗的3dB帶頻頻寬範圍為46.5~85.5 GHz，最小輸入損耗在60GHz頻率有

-1.8dB。就現有所知道的V頻段帶通濾波器特性最佳。

此外，本研究提出遞藥系統整合在晶片上，藉由電極通電後將水電解產生微

氣泡，藉由所產生的力開啟藥箱釋放藥物。經代工廠將無線技術中電路元件製作

整合在晶片上，再將該技術施作應用於生醫送藥系統，利用CMOS製程將在定義藥

箱後，藉由深槽技術移除矽基板後，再以顯式蝕刻將保護層及二氧化矽移除，即

完成藥箱結構，再充填藥物結構，完成晶片面積2.48㎟，消耗功率約7.57毫瓦，

並驗證體外實驗可行性。

最後，本研究將矽基板損耗在微波濾波器所造成的影響，作為提供為未來相

關電子元件矽基板損耗之研究參考。

關鍵字—電感耦合型電漿蝕刻；互補型金氧半；微機電；深槽技術；遞藥；系統

整合晶片；體外實驗。

Micromachined Microwave Filter and Biomedical Drug

Delivery Box Using CMOS-Compatible ICP Deep Trench

Technology

Student: Pen-Li Huang Advisor: Dr. Shey-Shi Lu

Graduate Institute of Electrical Engineering

National Taiwan University

Abstract

Using a micromachining technique, Deep Trench Technology has been invented to

completely remove the lossy silicon underneath the bandpass filters of microwave

passive components by utilizing Inductively-Coupled Plasma etching (ICP). In addition

to its use with passive devices, the approach is being further applied to active circuits

used in biomedical applications.

Using the proposed technique, it has been observed that the performance of a

microwave filter is significantly improved. A low-insertion-loss V-band CMOS

bandpass filter serves to demonstrate this. The proposed filter architecture has the

following features: the low-frequency transmission-zero (z1) and the high-frequency

transmission-zero (z2) can be tuned by adjusting the value of the series capacitor (Cs)

and the size of the built-in LC resonator. The folded short-stub technique is used to

reduce the chip size of the filter. To reduce loss of the silicon substrate, the

CMOS-process-compatible backside inductively-coupled-plasma (ICP) deep trench

technology can be used to selectively remove silicon underneath the filter. After the ICP

etching, the filter achieves an insertion-loss (1/S21) lower than 3 dB over the frequency

range of 46.5~85.5 GHz. The minimum insertion-loss is -1.8 dB at 60 GHz. To our

knowledge, this is one of the best results ever reported for a V-band CMOS bandpass

filter.

A drug delivery system on a chip (SOC) with integrated drug reservoirs is proposed

herein. Electrolysis is utilized to generate micro-bubbles; these act as a force used to

open the reservoirs and release the drug. Wireless components, including: an OOK

(on/off keying), receiver, micro-control unit, regulator, clock divider and power-on reset

are integrated for remote drug activation. The proposed microchip is fabricated by

TSMC 0.35 um CMOS technology followed by a post-IC processing. The total size is

2.48 mm2, and power consumption is 7.57mW. In-Vitro experiments have proven the

feasibility of the proposed drug delivery SOC.

The impacts of substrate removal upon the CMOS RFIC are quantified here for the first

time, providing a direction for further study to understand substrate loss more

completely; it will also allow this technique to be applied by integrating biomedical

circuits with drug delivery boxes or other MEMS devices.

Keywords: ICP, CMOS, MEMS, Deep Trench Technology, drug delivery, system on a

chip (SOC), In-Vitro

I

Table of Contents

1. Introduction

Bibliography of Chapter 1.............................................................................

1

6

2. Deep Trench Technology

2.1 Earlier Methods used to Improve Inductive Devices..............................

2.2 Inductively-coupled Plasma Etching.......................................................

2.3 Deep Trench Technology........................................................................

Bibliography of Chapter 2.............................................................................

7

7

20

27

30

3. Microwave Passive Filters

3.1 Introduction.............................................................................................

3.1.1 Deep Trench Technology.............................................................

3.1.2 Transmission lines……………………………………………...

31

31

32

33

3.2 E-band Bandpass Coplanar Filters..........................................................

3.2.1 Filter Structure.............................................................................

3.2.2 Measurement Results and Discussions........................................

39

39

42

3.3 50 GHz/60 GHz Phi Filters.....................................................................

3.3.1 Filter Design and Structure..........................................................


46

47

49

3.4 V-band CMOS bandpass filter.................................................................



55

55

56

3.5 CPW Band-Pass Filter Utilizing the LC Structure..................................



59

59

63

3.6 SiGe HBT Ultrawideband Low-Noise Amplifier....................................

3.6.1 UWB LNA Design......................................................................


72

73

74

3.7 Summary.................................................................................................. 79

Bibliography of Chapter 3............................................................................. 83

4. A Controlled-release Drug Delivery System on a Chip Using Electrolysis

4.1 Introduction.............................................................................................

4.2 System Architecture................................................................................

4.3 On-Chip Electrolysis...............................................................................

4.4 Drug Reservoir Design and Fabrication..................................................

4.5 Sub-Blocks..............................................................................................

4.6 Experiment Results.................................................................................

4.7 Practical Issues........................................................................................

89

89

92

94

95

99

99

104

II

Bibliography of Chapter 4............................................................................. 106

5. Conclusions 111

III

List of Figures

Fig. 2.1: Current distribution in a metal strip: skin effect and proximity effect... 8

Fig. 2.2: Section of a planar inductor and mapping lumped model...................... 9

Fig. 2.3: Model descriptions................................................................................. 12

Fig. 2.4: Problems with solid ground shield......................................................... 14

Fig. 2.5: Electric field and magnetic field penetration.......................................... 16

Fig. 2.6: Patterned ground shield of a planar inductor.......................................... 16

Fig. 2.7: Prior methods to improve inductors (a) thickening dielectric (b)

front-side etching (c) proton-implementation/porous silicon...............................

18

Fig. 2.8: Conventional plasma etching system..................................................... 22

Fig. 2.9: Illustration of alternating passivating and etch cycles............................ 23

Fig. 2.10: Inductively-coupled plasma etching system......................................... 25

Fig. 2.11: Schematic diagram of STS inductively coupled etch system used for

ASETM

...................................................................................................................

27

Fig. 2.12: Procedure of Deep Trench Technology................................................. 28

Fig. 2.13: Result of substrate removal.................................................................. 29

Fig. 3.1: Processing steps of the backside ICP deep-trench etching technology.. 33

Fig. 3.2: Complete small-signal equivalent circuit model of a TL inductor, in

which the effect of test pads is included………………………………………...

36

Fig. 3.3: Measured S21 versus frequency characteristics of STD TL-IND1, ICP

TL-IND1, ICP TL- IND2, and ICP TL-IND3 and an equivalent circuit does to

calculate the S21 of TL inductors………………………………….....................

37

Fig. 3.4: (a) Front-side die photo (before ICP etching) of filter-1. (b) top-view

and 3D schematic diagrams of filter-1. (c) backside die photo (after ICP

etching) of filter-2.................................................................................................

41

Fig. 3.5: Measure and simulated (a) S11 and (b) S21 of filter-1 after the backside

ICP etching...........................................................................................................

43

Fig. 3.6: Measured (a) S11 and (b) S21 of filter-1 both before and after the

backside ICP etching.............................................................................................

44

Fig. 3.7: Measured (a) S11 and (b) S21 of filter-2 both before and after the

backside ICP etching.............................................................................................

44

Fig. 3.8: The lumped-element model of the filter………………………………. 45

Fig. 3.9: Layout of the proposed bandpass filter (a) the 50GHz filter and (b) 3D

schematic diagram at the input port of the proposed band-pass filter...................

48

Fig. 3.10: Backside chip photo.............................................................................. 49

Fig. 3.11: S11 and S21 of the 50GHz filter............................................................. 49

IV

Fig. 3.12: S11 and S21 of the 60GHz filter........................................................... 51

Fig. 3.13: Maximum available power gain derived from the measured S

parameters.............................................................................................................

51

Fig. 3.14: The lumped-element model of the filter............................................... 52

Fig. 3.15: Comparison between modeling and measurement results.................... 54

Fig. 3.16: Equivalent circuit (a), front-side die photo (b), and backside die

photo (after ICP etching) of fabricated V-band CMOS filter (c)..........................

57

Fig. 3.17: Simulated and measured S21 and S11 against frequency

characteristics of proposed filter...........................................................................

58

Fig. 3.18: (a) Top view and cross-sectional schematic diagrams, and (b)

small-signal equivalent circuit model of the V-band CMOS bandpass filter........

60

Fig. 3.19: (a) Simulated S21 and S11 versus frequency characteristics of the

band-pass filter at various MIM capacitor dimensions. (b) Simulated S21 and

S11 versus frequency characteristics of the bandpass filter at various LC

resonator gaps……………………………………………………………….......

62

Fig. 3.20: (a) Front-side die photo, and (b) backside die photo (after ICP

etching) of the fabricated V-band CMOS filter.....................................................

63

Fig. 3.21: Measured and simulated S21 and S11 versus frequency characteristics

of the bandpass filter both with and without the silicon substrate

removal.................................................................................................................

65

Fig. 3.22: The lumped-element model of the filter............................................... 66

Fig. 3.23: (a) Chip micrograph, and (b) measured S-parameters of a test filter

with the series capacitor (Cs) but without the LC resonator.................................

68

Fig. 3.24: (a) Chip micrograph, and (b) measured S-parameters of a test filter

without the series capacitor (Cs) but with the LC resonator.................................

69

Fig. 3.25: (a) Schematic of the SiGe HBT UWB LNA. (b) Front side (before

the etching) and backside (after the etching) chip micrographs of the SiGe

HBT UWB LNA. The LNA occupied an area of 0.6×0.4 mm2, excluding the

test pads.................................................................................................................

76

Fig. 3.26: (a) shows the measured input return loss (S11) versus frequency

characteristics of the SiGe HBT UWB LNA both before and after the backside

ICP etching............................................................................................................

77

Fig. 3.27: The lumped-element circuit extracted from the first-order bandpass

filter……………………………………………………………………………...

79

Fig. 4.1: Architecture of SOC for drug delivery................................................... 93

Fig. 4.2: Proposed drug delivery system in package............................................. 96

Fig. 4.3: Opening of the integrated reservoir: (a) microbubbles generated on

the surface of electrodes by electrolysis, (b) membrane ruptured by gas

V

pressure................................................................................................................. 96

Fig. 4.4: Post-IC processing steps......................................................................... 98

Fig. 4.5: Die photos:(a) front-side (b) back-side................................................... 100

Fig. 4.6: Drug delivery SOC................................................................................. 100

Fig. 4.7: Measured sensitivity of the OOK receiver............................................. 102

Fig. 4.8: In-Vitro measurement setup................................................................... 102

Fig. 4.9: Measured drug release results: (a) before electrolysis (b) after

electrolysis............................................................................................................

103

Fig. 4.10: In vitro measurement results of the concentration of the fluorescent

dye versus time after an opening command is given............................................

103

VI

List of Tables

Table 2.1: Etching parameters..............................................................................

Table 3.1: Extracted small-signal equivalent circuit parameters of the E-band

bandpass filter both before and after the ICP etching...........................................

Table 3.2: Extracted small-signal equivalent circuit parameters of the 50 GHz

filter both before and after the ICP etching...........................................................

Table 3.3: Extracted small-signal equivalent circuit parameters of the V-band

bandpass filter both before and after the ICP etching...........................................

Table 3.4: Summary of the implemented V-band CMOS bandpass filter, and

recently reported state-of-the-art CMOS bandpass filters....................................

Table 4.1: Power and energy in different activation techniques...........................

27

46

53

67

71

104

1

Chapter 1

Introduction

Microelectromechnical Systems (MEMS) originated in the 1970s and micromachining

technology is now available for fabrication of micron-sized mechanical and electronic parts.

Micromachining has had a major influence in combining semiconductor processes to

fabricate micro devices such as pressure/temperature sensors, accelerometers and actuators,

in the same general manner as integrated circuits. The tiny size of these devices allows for a

high integration of mechanical and electronic components. This is a new technology that in

its most general form can be defined as including miniaturized mechanical and

electromechanical devices and structures manufactured using the techniques of

microfabrication. MEMS have many advantages including cost reduction through batch

fabrication, and advancements in dimensional downscaling, which leads to significant

reductions in the size and weight of components.

MEMS switches for low-frequency application were first demonstrated in the 1980s.

These devices used mechanical movements such as electrostatically actuated cantilever

beams to control the short circuiting or open circuiting of the transmission line. The idea of

adopting micromachining for radio-frequency application has grown and been displayed in

various designs ever since. In 1990 and 1991, Dr. Larry Larson demonstrated the first

MEMS switches for microwave applications. The device could operate at a frequency up to

50GHz [1.1][1.2], which was as good as any switching diode fabricated using GaAs

technology. The excellent performance of Larson’s work led to more widespread interest in

introducing conventional micromachining technology into microwave applications. In 1993,

2

RF MEMS capacitive switches were first invented as a means of achieving the low RF loss

afforded by MEMS and micromachining technology. By 1998, the University of Michigan,

the University of California at Berkeley, Northeastern University, Columbia University,

MIT Lincoln Labs and other reputable universities were devoting resources to similar work.

In 2001, more than 30 companies, including: NEC, Motorola, Samsung and

ST-Microelectronics, initiated operations in this area. The term radio-frequency (RF)

MEMS was therefore invented to address a new art that combines traditional MEMS

techniques and RF functionality.

Recent development of biomedical sensors and biosensors has assumed a significant

place in the application of micro sensor technology. This is especially true in the

development of micro biomedical sensors used primarily for diagnostic analyses. Since

their sizes are small, these sensors typically require a minute sample and can produce

results significantly more quickly than traditional biomedical instruments. In addition, these

sensors can be manufactured in batches using standard CMOS technology at a decreased

cost per unit. In the end, semiconductor sensors with integrated IC circuits and devices have

entered a new era of development, an era marked by the rapid growth of new applications

such as in biomedical sensors.

MEMS obviously differs from IC technology; from the perspective of device

fabrication, the most obvious difference between them is revealed in their etching depths

during processing. To sculpt the desired shape of the micro machines, the etching depth

required for the MEMS device can vary from as little as a few micron-meters to hundreds

of micron-meters. This is much larger than the etching depth required for the standard IC

process, which is usually carried out at the sub-micron level. From a geometrical point of

view, the MEMS device is more like a three-dimensional device since the vertical sidewalls

3

of these devices are generally large enough to be recognized; on the other hand, IC devices

are comparatively two-dimensional as most of the transistors are planted near the surface of

the wafer. Even though both technologies may utilize the same equipment, the ways the

equipment is used can actually result in large differences and cause the compatibility

problem that prohibits MEMS devices from being integrated with standard CMOS chips.

Although restricted by the rules enforced by CMOS transistor manufacturing, MEMS

technology allows RF devices to be built using a variety of materials. Whether the substrate

is thin or thick, conductive or insulated, a practical choice of designs can be applied to

RF-MEMS devices. As a result, there have been many innovative microwave devices

proposed in past decades, including RF switches, micromachined transmission lines,

inductors, filters and antennae [1.3]. The results of these approaches were so impressive

that they were quickly adopted by industry. Unfortunately however, although these

RF-MEMS devices gain many advantages by using micromachined components, when it

comes to the scale of system-on-a-chip, the inherent problem of incompatibility arises,

entailing limitations in the practicality of applying conventional MEMS technology for

CMOS IC. In the past, there were many MEMS techniques claiming compatibility with

CMOS technology; however, most of them were only demonstrated without actual active

circuit integration, with the exception of an article published in 1993 by Prof. Abidi who

implemented surface wet-etching to reduce substrate loss of LNA [1.4]. In 1999, G. M.

Rebeiz focused on the design using shunt sections which are open-ended stubs loaded at

the ends with a smaller MEMS bridge switch, and implementation of coplanar waveguide

(CPW) shunt capacitive switches tuned configurations for high isolation applications from

20-40 GHz [1.5].

To demonstrate how MEMS techniques can be applied to active circuits, we developed

4

a new approach referred to as deep trench technology; this can totally remove the

underlying silicon by defining and improving circuit performance in advance. The proposed

technique Wang invented involves post-IC processing, as the chip is fabricated using the

standard CMOS process. Moreover, the radio-frequency CMOS-integrated devices such as

LNA and microwave filters had taken advantage of this technique. Those results verified

the practicality of deep-trench technology, and the adoption of MEMS techniques in IC

technology is no longer an experimental curiosity. The following chapters exhibit how to

implement CMOS ICs using the proposed technology and how to make each component

used in microwave passive devices and biomedical sensors benefit from its application.

The first consideration in applying MEMS technology to improve the RF elements is

usually to make use of its high aspect-ratio etching. This reduces the lossy silicon

underneath inductive devices and improves their performance. Chapter 2 begins with an

overview of the loss mechanisms of inductive devices in CMOS ICs. Prior techniques used

to reduce these losses will be introduced afterward, followed by the principle and process

steps of our proposed deep trench technology.

The main subject of this thesis is examined in Chapter 3. Passive filters using deep

trench technology to improve their performance will be demonstrated and discussed in the

microwave frequencies.

At the beginning of Chapter 3, the previous design of microwave bandpass filters using

GaAs technology will be implemented using standard CMOS technology. An example

adopting these layouts and equations will be verified by implementing a 60GHz bandpass

filter through the CMOS 0.18um or advanced technology. Following this will be a

demonstration of deep trench technology applied to the very same microwave bandpass

filter. In addition, besides the filter mentioned above, an identical method will be applied to

5

an active circuit like LNA. The differences caused by substrate removal will also be

discussed.

In Chapter 4, a technology extended from deep trench technology will be proposed for

realization in the biomedical field using standard CMOS technology. The technology is

able to carve holes on the silicon substrate for the volume of the drugbox, which may be

opened by an electrochemical reaction in order to deliver the drug.

Chapter 5 concludes with a summary and suggestions for future study.

6

Bibliography of Chapter 1

[1.1] L. E. Larson, R. H. Hackett, M. A. Melendes, and R. F. Lohr, "Micromachined

microwave actuator (MIMAC) technology-a new tuning approach for microwave

integrated circuits," in Microwave and Millimeter-Wave Monolithic Circuits

Symposium, IEEE, 10-11 Jun 1991, pp. 27 – 30.

[1.2] L. E. Larson, R. H. Hackett, and R.F. Lohr, “Microactuators for GaAs-based

microwave integrated circuits” in International Conference on Solid-State Sensors

and Actuators, 24-27 Jun 1991 pp.743 – 746.

[1.3] W. H. Weedon, W. J. Payne, G. M. Rebeiz, and RI Warwick, “MEMS-switched

reconfigurable antennas” in Antennas and Propagation Society International

Symposium, 2001. IEEE 2001 pp. 654 - 657 vol.3

[1.4] C. Y.-C. Chang, A. A. Abidi and M. Gaitan, “Large suspended conductors on silicon

and their use in a 2-um CMOS RF amplifier”, IEEE Electron Device Letters, vol. 14,

Nay, 1993.

[1.5] Jeremy B. Muldavin and Gabriel M. Rebeiz, “High Isolation CPW MEMS Shunt

Switches Part 2: Design”, in Transactions on Microwave Theory and Techniques,

IEEE, Jun 2000 vol.48 no.6 pp.1053 – 1056.

7

Chapter 2

Deep Trench Technology

Passive components have been indispensable devices in microwave millimeter designs.

These are usually applied for use in matching networks, tuned loads, transformers and

resonators. The filters are key elements in the microwave designs and are usually designed

by active devices. Since the heavily doped (~1e19

-1e20

/cm3) silicon substrate and the

MOSFET suffer from poor unit frequency ft in the standard CMOS technology, active

filters are difficult to model and their performance is quite poor at high frequency.

This chapter first provides a review of the basic mechanisms of substrate loss by

studying the inductor substrate and describing how to improve the performance of inductors.

Several methods proposed to moderate the substrate effects will be given as an introduction

to this chapter. Next, the inductively-coupled plasma (ICP) etching system will be

introduced, and how its use can achieve the desired goals. The principle of ICP function

will be explained briefly, followed by the details of the processing steps used by deep

trench technology in passive filters and drug delivery boxes.

2.1 Earlier Methods used to Improve Inductive Devices

Until recently, the inductor has been fabricated using standard CMOS technology.

Owing to the standard CMOS which adopts a silicon substrate doped with high resistivity,

the performance of the inductor suffers from several power dissipation mechanisms caused

by both the electric field and the magnetic field getting through the substrate at high

8

frequencies. As is well known, the skin effect and the proximity effect lead to a degradation

of the quality of the inductor [2.1].

Fig. 2.1: Current distribution in a metal strip: skin effect and proximity effect

At high frequencies, the electromagnetic field effect will cause a non-uniform current

distribution in the inductor. The propagated wave inside a good conductor with a circular

cross section instead of providing the full area to current flow and the current, is pushed to

the outside of the conductor where it will decay quickly. Therefore, the electromagnetic

field and the conducting current in the conductor mentioned above will be pushed to and

crowded at a small area near the surface; this is the so called skin effect. The current

distribution in a metal strip is shown in Fig. 2.1. As can be seen, most current is distributed

(crowded toward) on the edge of the conductor. Putting the equivalent circuit model into

perspective, the fact that the effective area used for current conduction is limited

consequently increases the series resistance of the signal path and contributes to the

conductive loss of the inductor. The key (Fig. 2.2) to solving this problem is to increase the

thickness of the metal strip so that the cross-section area for the current conduction can be

9

enlarged so that its resistive loss can be reduced. In fact, using ultra-thick metal as an

interconnection has generally become the current option in CMOS foundries for

commercial applications.

Fig. 2.2: Section of a planar inductor and mapping lumped model [2.2]

In a dc field, the current density is uniform in a conductor, but the formation of eddy

currents cause the current density to become non-uniform when the frequency is increased.

The eddy current, which leads to a significant effect on the inductance of the spiral inductor

fabricated by standard CMOS processes, manifests itself not only as a skin effect, but also

as a proximity effect. At around 1 GHz, it is demonstrated that the proximity effect between

turns of the spiral inductor in the same plane can be neglected, especially normal on the

cross section of the inductor where the width of the metallic trace is relatively larger than

its thickness. However, when the frequency is below 1 GHz, the skin effect is relatively

10

small in most instances since the metallic trace thickness is typically less than or equal to

the skin depth. For frequencies above 1 GHz, the resistance increases, so the skin effect

becomes a more dominant factor.

The skin effect is the tendency for high-frequency currents to flow on the surface of a

conductor. The proximity effect is the tendency for current to flow in undesirable patterns:

loops or concentrated distributions, due to the presence of magnetic fields generated by

nearby conductors. As can be seen, when frequencies increase, the penetration of currents

and magnetic fields onto the surface of conductors is governed by the skin effect. In

addition, eddy currents reduce the net current flow in the conductor and increase the ac

resistance. The distribution of eddy currents depends on the geometry of the conductor and

its orientation with respect to the impinging time-varying magnetic field. The most critical

parameter related to eddy current effects is the skin depth: is defined as

√

(2.1)

where ρ, μ, and ƒ represent the resistivity in Ω-m, permeability in H/m, and frequency

in Hz, respectively. The skin depth is also known as the “depth of penetration” which

describes the degree of penetration by the electric current and magnetic flux into the surface

of a conductor at high frequencies, depending on both the frequency and the properties of

conductive material, its conductivity or resistivity and its permeability. The ratio of skin

depth to the conductor thickness determines the eddy current effect. The eddy current effect

is negligible while the depth of penetration is much greater than the conductor thickness.

The proximity effect is basically dependent on the geometry of the inductor’s coils. It

plays a significant enough role that the design of these layouts should minimize the

degradation caused by the proximity effect. Even though the proximity effect has received

11

increased attention in recent years, most efforts spent in the past decade focused mainly on

how to decrease the substrate effects caused by electromagnetic fields getting through the

substrate. For on-chip spiral inductors fabricated by standard CMOS processes, and based

upon Yue’s [2.2] analysis, the following must be considered: as the space between the

metal and other metal is close with standard CMOS processes, the proximity effect between

turns of the spiral mentioned above that were set up in the same plane can be neglected at

high frequency.

The series resistance, Rs, can be expressed as:

(2.2a)

where teff is defined as an effective thickness:

(

⁄ ) (2.2b)

Based on the skin depth equation mentioned above, resistance can yield optimistic

estimates because the equation accounts only for skin loss associated with the surface of the

conductor that faces the substrate. It thus neglects skin loss associated with the other

surfaces and substrate losses involving lightly doped substrates. In general, most of the

standard CMOS processes using heavily doped substrates are about 10mΩ．cm, and losses

associated with eddy currents induced in the substrate become important or even dominant

at high frequencies. However, the effect of induced substrate currents on the inductance

value is small enough to be ignored in practical cases. As can be seen, when δ decreases

with frequency, R increases. Note that resistance due to eddy current loss in the substrate is

proportional to the square of frequency and to the square of the number of turns. Following

are descriptions of some of the most powerful effective equations.

12

The series capacitance, Cs, accounts for the feed-through path coupling effect between

the input and output ports of the inductor. Based on the inductor’s physical structure, both

the crosstalk between adjacent turns and the overlap between the spiral and underpass

contribute to Cs. In general, due to the larger potential difference between the spiral and the

oxide, the effect of overlap capacitance is more significant. Therefore, it is sufficient to

model Cs as a sum of all overlap capacitances, which is equal to:

(2.2c)

where n is the number of overlaps, w is the spiral line width, and tOXM1-M2 is the oxide

thickness between the spiral and the underpass.

Fig. 2.3: Model descriptions [2.2]

The line segments of on-chip spiral inductors can be treated as microstrip transmission

lines. For example, a CMOS microstrip structure can be represented as Cox, Rsub and Csub

13

(see Fig. 2.3). The Cox is the oxide capacitance, and Rsub and Csub represent resistance and

capacitance, respectively, of the silicon substrate. The conductivity of the Rsub is relevant to

the doped silicon substrate, and the Csub is capacitive effects occurring in the semiconductor

at high frequency. As a result, the substrate capacitance and resistance are approximately

proportional to the area occupied by the inductor and can be estimated by:

(2.2d)

(2.2e)

(2.2f)

where Csub and Gsub are capacitance and conductance per unit area for the silicon

substrates. ox and tox represent the dielectric constant and thickness of the oxide layer

between the inductor and the substrate, respectively. The area of the spiral is equal to the

product of the spiral length (l) and width (w). The factor of two in (2.2d)–(2.2f) accounts

for the parasitic of substrate assumed to be distributed equally at the two ends of the

inductor. Csub and Gsub are functions of the substrate doping and are extracted from the

measurement results. The substrate type is another important factor to be chosen and the

current model is suitable only for uniformly doped substrates. For non-uniform doping

substrates, parallel networks can be cascaded in series to predict the substrate behavior. For

inductors on epi substrates, the magnetic coupling between the spiral and the substrate can

induce eddy currents in the lower resistivity silicon. This effect is not accounted for in the

current model. However, substrate eddy currents could be neglected even in epi substrates

up to approximately 3 GHz [2.2].

In this model mentioned above, the Rs explains the skin effect of a conductor with

14

finite thickness, and the Cs represents the capacitance between the spiral and substrate. The

Cox is the oxide capacitance, and the Csi and Rsi are approximated as the substrate parasitic

and are proportional to the area covered by the spiral. At low frequency, the impedance of

1/jwCox is comparatively larger than the impedance of shunted Csi / Rsi, which means that

most of the voltage is distributed on the Cox instead of the shunted Csi / Rsi. In other words,

the electric field ends at the interface between silicon dioxide and silicon before reaching

the substrate. However, as the frequency increases, the electric field starts to get through

Cox and into the substrate (see Fig. 2.4), revealing the parasitic effects of Csi/Rsi [2.2]. The

appearance of Rsi becomes more effective with the increased frequency, as does the

degradation of its quality factor.

Fig. 2.4: Problems with solid ground shield [2.2]

Using metal conductor traces in the spiral, the resistance of an inductor can be lowered.

At high frequencies, the AC currents take the path of least impedance, as illustrated in the

15

current density plot of Fig. 2.1. The current flow is non-uniform and tends to flow along the

inner side, or lower inductance path.

Except when the electric field is effective, the magnetic field getting through the

silicon substrate can also contribute to substrate loss. As shown in Fig. 2.5, the magnetic

flux getting through the conductive substrate theoretically induces an eddy current in the

conductive substrate. An infinity resistive substrate, or an insulating substrate, is ideal but

not widely available in Si IC processes. On the other hand, due to the eddy currents a

magnetic flux is generated that opposes the inductor flux. An infinitely conductive substrate

is undesirable because the induced eddy currents would worsen the inductance. In practice,

for currents in the inner conductors with finite non-zero substrate resistivity and in

accordance with Lenze’s law, this eddy current produces an imaginary magnetic flux,

causing the original magnetic flux to flow in the opposite direction. The behavior of these

magnetic fluxes may produce a serious drawback by weakening the performance of the

inductor. We should strive to place our substrate contrasts in such a way as to move away

from the optimal substrate resistance value.

16

Fig. 2.5: Electric field and magnetic field penetration

Fig. 2.6: Patterned ground shield of a planar inductor [2.2]

17

In 1998, Dr. Yue [2.3] created a method to prevent the electromagnetic field from

getting through the substrate by reducing the two effects mentioned above. He set up a

layer of patterned metals under the inductor to shield the EM field (see Fig. 2.6) in the

multi-conductor structure. The metallic shield can effectively block the EM field,

preventing it from getting through the substrate. The approach is an attempt to move the

substrate resistance to zero by using a shield. However, the shield cannot be solid since

eddy currents would again reduce the inductance value. A patterned shield can minimize

the effect of eddy currents without disturbing the displacement current flow. The shield can

be set up with a metal layer and patterned in such a way as to minimize any spiral in the

shield. Moreover, the metal slots in the pattern are set up to be orthogonal to the direction

of the eddy current, effectively avoiding the problem mentioned above. In this case, the

eddy current, which was supposed to be distributed on the metallic shield, with no

patterned-metal under the inductor such as slots, will be disturbed and highly depressed.

The PGS method mentioned above could prevent the electromagnetic field from

getting through the substrate but there is still one serious drawback to using this method: it

reduces the self-resonance frequency. The distance between the inductor and PGS is small

enough to couple and produce a large amount of parasitic capacitance, which reduces the

self-resonance frequency and restricts the operation frequency range of this inductor.

The main drawback of the shield is that it increases the substrate capacitance of the

structure, leading to a lower self-resonant frequency. Furthermore, it cannot shield the

devices from magnetically-induced substrate losses. On the other hand, the shield can

potentially reduce the amount of energy that is injected into or captured from the substrate,

leading to better isolation.

Thanks to the fact that the substrate possesses conductive properties with doping, the

18

substrate coupling in an inductor introduces loss. The substrate resistance depends strongly

on the placement of substrate contacts at the substrate back plane set up as a ground

connection, and the frequency of operation. At low frequencies, the current extends to the

backside; however, at high frequencies, the current getting through the substrate contacts

dominates as the current decreases. The flow of capacitive substrate current is shown in Fig.

2.5. It is important to distinguish between the capacitive substrate currents flowing due to

the changing magnetic fields. This current flow induced by emf for the time-varying

magnetic field penetrates the substrate causing additional power loss and making the series

resistance of the spiral inductor increase to be an effective. For heavily conductive

substrates with ρ<0.01Ω-cm the loss can be a significant fraction of the overall losses.

Conversely, for moderately conductive substrates with ρ>1Ω-cm, the induced eddy currents

are small and can be neglected at moderately high frequencies (L<20nH, f<10GHz) [2.5].

Fig. 2.7: Prior methods to improve inductors (a) thickening dielectric (b) front-side etching

(c) proton-implementation/porous silicon

Besides the PGS method mentioned above, there are other techniques that have been

proposed to reduce substrate effects, as shown in Fig. 2.7. These include: setting up a thick

19

dielectric layer [2.6], etching the substrate from the pattern side [2.7], ion-implementation

[2.8] and porous silicon [2.9]. The dielectric layer under the inductor can be an ultra-thick

dielectric layer to prevent the EM field from getting through, and it can also make the

substrate loss low. However, the thickness of the dielectric leading to effective loss

reduction is so thick that it is not adopted (~30um). Instead of depositing a thick dielectric

upwards, front-side etching is processed downward on the chip, which defines a window on

the front-side of the chip with photolithography and uses wet etching to remove the silicon

substrate under the inductor in this window. However, the chemical etchant is liquid; it

requires more complex procedures in order to protect the devices from being damaged. Ion

implementation is aimed toward the substrate and allows the backside of the chips with

high energetic ions to neutralize the implanted silicon substrate in order to reduce

conductivity. The method needs more energy and is so powerful that it requires a metallic

sheet to act as a buffer layer between the targeted substrate and to avoid damage by ion

beams. It destroys the transistors at the same time the conductive silicon is being insulated.

Porous silicon is a silicon substrate that dense voids and empties. However, it is difficult to

etch the front side of the chip. The damage caused during the chemical etching process

poses a serious problem that needs to be considered. Even if these methods are effective

and capable of reducing substrate loss, they are rarely applied to standard active circuit

devices due to their poor reliability.

In 2006, Dr. Wang [2.5] proposed a method to remove the silicon substrate under the

designed circuit while overcoming the drawbacks mentioned above. He thought the

ultimate method to eliminate substrate loss was to remove it. By using inductively-coupled

plasma (ICP) deep trench technology, he achieved his goal by improving upon some

drawbacks of the PGS method invented and proposed by Yue. This approach is completely

20

compatible with current CMOS technology, and has been demonstrated with many RF

components. In this thesis, we use Wang’s method to remove the substrate under the

passive filters using standard CMOS technology. It is useful to improve the performance of

passive filters, effectively increasing the insert loss. In chapter 3, we introduce this process

step by step by using it on passive filters and then discuss in greater detail how the

performance of these filters might be improved.

2.2 Inductively-coupled Plasma Etching

Thanks to wet silicon etching (such as KOH or EDP) suffering from the disadvantages

of crystal orientation dependency, the need for thick masking and the surface tension

problems associated with close proximity high aspect ratio structures arise. Because silicon

has the advantage of anisotropic etching to obtain a high aspect ratio, it plays a vital role in

the microelectromechanical system (MEMS) industry. However, using the wet-etching

method incurs some extra costs such as calculating precise etching time to avoid damaging

active devices and causing circuit failure. In addition, the extra cost of wet etching

compared to dry-etching may be lower. However, to build high-aspect-ratio micro

machines with dry etching, high-density plasma sources are provided to achieve the goal.

For many applications, deep reactive ion etching (DRIE) presents an attractive MEMS

solution. Dry etching stations generate high plasma densities to achieve a high etching rate

while operating at low pressures. Ion-enhanced plasma etching has become increasingly

popular in today’s advanced technology. Traditional reactive ion etching (RIE) was first

utilized to achieve the high aspect ratio silicon feature. But its etching rate is small (less

than 1um/min) and the aspect ratio is never more than 10. Therefore, high density and low

21

pressure plasma etching systems like electron cyclotron resonance (ECR) and inductively

coupled plasma (ICP) were developed to meet the abovementioned requirements. In

particular, plasma is driven inductively with a power source operating at the standard 13.56

MHz in an ICP source. Such sources create high-density, low pressure, low-energy plasma

by coupling ion-producing electrons to the magnetic field arising from the RF voltage. In

addition to the etching system, process control is important to obtain the high aspect ratio

silicon method for determining the etching parameters in deep silicon trench fabrication. In

general, those systems could decompose specific gases, generating some plasma with the

desired reactants inside, while processing the chemical and physical reactions at the same

time or in turns. The inductively coupled plasma (ICP) etch tool has several advantages

compared with other plasma sources, such as the electron cyclotron resonance (ECR),

helicon and reactive ion etching (RIE). Because of its greater scalability and wider

operating range, silicon, polysilicon and dielectrics have a high etching rate. In this thesis,

we use the ICP made by the Surface Technology Systems (STS) to achieve the goals of our

study, including components such as: passive bandpass filters, drugbox delivery chips and

some active circuits like those which set up the above silicon substrate by the standard

CMOS process. An illustration of how plasma etching operates is shown in Fig. 2.8. An

alternating field is applied in the chamber to ionize the inlet gas, generating some plasma, a

mixture of ions, radicals and free electrons.

22

Fig. 2.8: Conventional plasma etching system (CCP)

As the alternating field is being applied, a steady-state potential (DC) conducting the

ions to accelerate and hit the substrate is also set up in the bottom electrode. By

manipulating the processes of the chemical etching by radicals and the physical etching by

directed ions, an efficient etching with a high aspect ratio will be realized; this is generally

referred to as ion-enhanced plasma etching.

23

Fig. 2.9: Illustration of alternating passive and etch cycles.

Each reaction cycle includes passivation and etching steps, respectively. These are

shown in Fig. 2.9. The etching and passivation gases were SF6 and C4F8, respectively, and

these changed during the process. First, the C4F8 gas is put into the chamber. While

applying an alternating field to the C4F8 gas, which is discharged and decomposed to CFx

radicals and electrons, some plasma is generated. After the generation of plasma, the CFx

radicals start to diffuse in the chamber and react with the silicon substrate, generating a

fluorocarbon polymer layer on all silicon substrate features. As the chamber does not have

the vertical RF source applied, the reaction is isotropic. After the passivation step, the inlet

gas is switched to SF6, generating F atoms and SFx+

ions. During the etching time, the

vertical RF source is applied, generating an averaged DC potential, used to directly guide

the SFx+ ions hitting and to remove the polymer layer formed by passivation. Once the

24

polymer of the etching window is removed, the F atoms acting as etchants start to etch the

silicon chemically. It is important that the SFx+ ions are directed by the vertical RF source,

so that the ions hitting the trench most powerfully are very directional, thus keeping the

polymer layers on the side wall from being etched and assuring that the F atoms can only

react vertically, not isotropically, which is the reason that the ion-enhanced plasma etching

method can achieve the goal of a high aspect ratio trench.

Since the ions are used to clean the passivation layer for radical reaction, the denser the

plasma, the faster the vertical etching can be. In general, there are two kinds of systems

designed to create higher density plasma in commercial systems: the capacitively-coupled

plasma system (CCP) and the inductively-coupled plasma (ICP) system.

Fig. 2.8 shows a conventional CCP etching system. In this system, a lower pressure gas

inlets into the chamber. While applying the electric field to electrodes being set up in the

chamber, the gas is ionized producing positive ions, high electrons and free radicals, while

creating plasma. The applied electric field is generated by a RF source at 13.56MHz.

Because the mobility of electrons is much less than that of ions, electrons are able to catch

up with the switching electric field, whereas the heavier ions do not. As a result, the

electrons are dynamically accumulated on both sides of the electrodes, creating a

quasi-static negative biased zone, and the space filled with ions becomes positive biased.

The average voltage potential in this system is also shown in Fig. 2.8. It is the potential

drops near the electrodes that cause the heavy positive ions to hit the targeted chips and

perform physical ion etching.

Due to the fact that CCP can be used for physical etching, the density of plasma is still

limited. This constitutes a reason why the density of plasma needs to be increased;

therefore, we may need to increase the signal power of the RF source. However, an increase

25

in the RF source power also means an increase of voltage drop near the electrodes. The

enlarged potential caused in this instance will make the ions accelerate so fast that serious

damage may be done to the chip as the ions impact it. The other method by which plasma

density can be increased is to raise the gas pressure in the chamber under the same RF

source power, aiming to induce more ions for etching the silicon substrate. The increased

gas pressure, however, may cause many more phase collisions. These extra collisions will

deteriorate the anisotropic etching. It is important to improve some of these

abovementioned problems. We need to examine other plasma-generated systems which can

operate at low pressure and produce low energetic ions at the same time.

Fig. 2.10: Inductively-coupled plasma etching system

26

The ICP etching system has been manufactured to solve the problems of CCP which

have been described above. Some differences between CCP and ICP systems exist. Instead

of the CCP system which takes the single RF source in the chamber, the ICP system is set

up using two separated RF sources. Those abovementioned RF sources were set up

respectively in etching systems, except for their RF sources which are all same at

13.56MHz; one is used to discharge the plasma, and the other is used to control the ion

bombardment. A sketch of this system is shown in Fig. 2.10, where the chamber wall is set

up with a coil to generate a strong magnetic field for plasma discharge. The RF source

(13.56MHz) is set up with a coil to create a circular electric field in the chamber. The

induced electric field is parallel to the chips, so the RF power used to discharge plasma can

be raised considerably without creating a voltage drop perpendicular to the chips and

without the corresponding damages. As for the source required to direct the ion impact,

another RF source (13.56MHz) is placed under the chip carrier, which is used to bias the

wafer and guide ions to impact the target. Setting up RF sources and the inductive coupling

method make ICP generated plasma extremely efficient. Its main advantage is to let ICP be

used extensively in the etching equipment due to its ability to obtain an ultra high aspect

ratio.

The ICP we used is STS, MESC Multiplex ICP, Ver. 2. The schematic of the Mutiplex

ICP process chamber is shown in Fig. 2.11. The etching parameters are depicted in Table

2.2.

27

Table 2.1: Etching parameters [2.5]

Etching Parameters

Substrate Silicon

Mask SiO2 / Photoresist

Selectivity Silicon : Photoresist>60:1

Silicon : SiO2>120:1

Etching rate 2um/min

Fig. 2.11: Schematic diagram of STS inductively coupled etch system used for ASETM

[2.10]

2.3 Deep Trench Technology

With the etching ability of ICP having the advantages described above, a novel deep

trench technology was presented with the detailed procedure shown in Fig. 2.12.

28

Fig. 2.12: Procedure of Deep Trench Technology

How does the ICP remove the silicon substrate under the circuit? First, the front side of

the fabricated die was attached to a carrier wafer with adhesive wax, followed by

mechanically clipping the thickness of the silicon substrate down to nearly 100um. Next,

heating softened the wax so that the glass substrate could be removed from the front side of

the die allowing it to be cleaned easily with acetone. The front side of the die with a 100um

thickness was then attached to a glass substrate with adhesive i.e. photoresist S1813. Next,

the back side of the die was spun on the photoresist AZP4620. As the photolithography

29

procedure on the back side of the die was completed, the ICP dry etching was used to

remove the silicon underneath the inductors of the circuits. The main gases used during the

ICP etching process of approximately 17 s were an alternate cycle of SF6 (for etching) and

C4F8 (for passivation). The ICP etching rate is about 2um/min, so the total etching time was

approximately 50 min. Finally, the adhesive and photoresist that covered the front and back

sides of the die were removed for test purposes.

Fig. 2.13: Result of substrate removal [2.5]

A back side photo of a micromachined inductor is shown as an example in Fig. 2.13.

As indicated, the silicon underneath the planar inductor is etched clearly, so a clear pattern

on the chip front side can be seen through the transparent silicon dioxide. This technology

allows us to remove the specific area of silicon defined by photolithograph without

damaging any transistors in the circuit during the etching sequences.

30


[2.1] Ali M. Niknejad, and Robert G. Meyer, "Analysis of Eddy-Current Losses Over

Conductive Substrates with Applications to Monolithic Inductors and Transformers,"

in Transection on Microwave Theory and Techniques, IEEE, vol. 49, no. 1 Jan 2001,

pp. 166-176.

[2.2] C. Patrick Yue, and S. S. Wong, “Physical Modeling of Spiral Inductors on Silicon” in

Transection on Electron Devices, IEEE, vol. 47, no.3, Mar 2000 pp.560-568.

[2.3] C. Patrick Yue, and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground

Shields for Si-Based RF IC’s” in Journal of Solid-State Circuits, IEEE, vol. 33, no. 5,

May 1998. pp. 743-752.

[2.4] Ali M Nikejad, “Electronmagnetics for High-Speed Analog and Digital

Communication Circuits", in Cambridge University Press 2007, pp. 138-140.

[2.5] Tao Wang, “Micromachined RFIC by CMOS-Compatible ICP Deep Trench

Technology”, Doctoral Dissertation of National Taiwan University, 2006.

[2.6] B. K. Kim, B. K. Ko, and K. Lee, “MonoliticPlannar RF Inductor and Waveguide

Structures on Silicon with Performance Comparable to Those in GaAs MMIC”, in

IEDM Tech. Dig., 1995, pp. 717-720.

[2.7] H. Lakdawala, X. Zhu, H. Luo, S. Santhanam, L. R. Carley, and G. K. Fedder,

“Micromachined High-Q Inductors in a 0.18um Copper Interconnect Low-K

Dielectric CMOS Process”, in Journal of Solid-State Circuits, IEEE, vol. 37, no. 3,

Mar 2002. pp. 394-403.

[2.8] C. Y. Lee, T. S. Chen, C. H. Kao, J. D. S. Deng, C. C. Yen, Y. K. Lee, J. C. Kuo, J. F.

Chang, G. W. Huang, K. M. Chen, and T. S. Duh, “A Simple Systematic

Procedure of Si-Based Spiral Inductor Design”, in Proc. RFIC Conference, IEEE,

pp. 619-622, June 2004.

[2.9] Y. H. Xie, M. R. Frei, A. J. Becker, C. A. King, D. Kossives, L. T. Gomez, and S. K.

Theiss, “An Approach for Fabricating High-Performance Inductors on

Low-Resistivity Substrates”, in Journal of Solid-State Circuits, IEEE, vol. 33, Sept.

1998. pp. 1433-1438.

[2.10] A. M. Hynes, H. Ashraf, J. K. Bhardwaj, J. Hopkins, I. Johnston, and J. N. Shepherd,

“Recent Advances in Silicon Etching for MEMS Using the ASETM

Process”, in

Sensors and Actuators 74, 1999, pp. 13-17.

31

Chapter 3

Microwave Passive Filters

3.1 Introduction

In the past, III-V semiconductor technologies were adopted in most of the applications

for frequencies around 60 GHz and above. Recently, thanks to the rapid development of

CMOS processes, the limitations, such as insufficient current-gain cut-off frequency (ft)

and maximum oscillation frequency (fmax), have been overcome [3.1]-[3.3]. It has become

possible to use them to implement 57~64 GHz ultra- wideband (UWB) transceivers for

wireless personal area network (WPAN) systems, 77~81 GHz UWB automotive radar for

automatic cruise control (ACC) and collision-avoidance systems [3.4]-[3.6], and 94 GHz

radar sensor for process control and imaging.

The burgeoning applications of millimeter-wave (MMW) CMOS technology bring

new challenges and opportunities for both the academia and the industry. Much attention

has been paid to the realization of high-quality on-chip bandpass filters. For example, [3.6]

demonstrate a lump-element based 77-GHz-band bandpass filter, and [3.7]-[3.10] report

micro-stripline (MSL) based 60-GHz-band bandpass filters. However, there are few

coplanar-waveguide (CPW) based bandpass filters mainly due to their large chip size and

poor immunity against silicon substrate loss. To demonstrate that small chip size and low

insertion loss can be achieved simultaneously for a CPW based bandpass filter, in this work,

we propose a novel CPW filter with small chip size and low insertion loss. The folded

short-stub technique is used to reduce the chip size of the filter. In addition, the

32

low-frequency transmission-zero (ωz1) and the high-frequency transmission-zero (ωz2) of

the bandpass filter can be tuned by adjusting the value of the series capacitor (Cs) and the

size of the built-in LC (electromagnetic bandgap) resonator, respectively. Furthermore, the

CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench

technology is used to selectively remove the silicon underneath the filter. This leads to a

significant reduction of the silicon substrate loss. The bandpass filter occupies a chip area

of 0.44×0.36 mm2 and achieves a minimum insertion-loss of -1.8 dB at 60 GHz, one of the

best results ever reported for a V-band CMOS bandpass filter in the literature.

In the end of this chapter, we demonstrate that the power gain (S21) and noise figure

(NF) performances of a SiGe HBT Ultra-Wideband Low-Noise Amplifier (UWB LNA) can

be remarkably improved by removing the silicon underneath the UWB LNA with

BiCMOS-process compatible backside inductively-coupled-plasma (ICP) deep trench

technology.

3.1.1 Deep-Trench Technology

The processing steps of our backside ICP deep-trench technology are shown in Fig.

3.1 and described as follows. First, for the ease of chip handling, the front side of the die

with the circuit or device was stuck to a glass substrate with adhesive S1813 followed by

dropping photoresist AZP4620 on the backside of the sample. Note that these process steps

can be omitted when applied in mass production because the wafer diameter is large. After

standard photolithography processes on the backside of the die, the ICP dry etching was

used to remove the silicon (400-um thick) underneath the circuit or device [i.e., the area

enclosed by the dash lines in Fig. 3.22(b) and 3.23(c)]. The main gases used during the ICP

33

etching process were alternate SF6 (for etching) and C4F8 (for passivation) with a 17s cycle.

With the ICP etching rate being about 2 um/min, the total etching time was about 200 min.

For long ICP etching, the thickness of the polymer formed on the sidewall was not

negligible, which in turn blocked the ICP etching. Therefore, after the first half ICP etching

was done (i.e., at around the 100th min), the sample was shifted to an O2 plasma chamber

for 30 min to remove the sidewall polymer.

Fig. 3.1: Processing steps of the backside ICP deep-trench etching technology.

After the sidewall polymer was removed, the sample was shifted to the ICP chamber

again to finish the second half ICP etching. Finally, the adhesive and photoresist, which

covered the front side and backside of the die, respectively, was removed for test purposes.

3.1.2 Transmission lines

To precisely calibrate the simulation circumstance, before the simulation of the filters,

a set of transmission lines (TLs) with various length (50-200 um) and width (5-20 um) was

fabricated, measured and modeled to obtain scalable TL parameters (both with and without

the backside ICP etching). The methodology used is as follows. According to the standard

(1) Chip Flipping

(2) Photolithography

(3) ICP Etching

(4) Cleaning

34

TL theory [3.22], the ABCD matrix of a TL can be expressed as a function of its

propagation constant γ (=α+ jβ, in which α and β are attenuation constant and phase

constant of the TL, respectively), characterization impedance ZC, and length l as follows:

[𝐴 𝐵 𝐷

] [𝑐𝑜𝑠ℎ(𝛾 ) 𝑍𝑐 𝑠𝑖 ℎ(𝛾 ) 𝑖𝑛ℎ(𝛾 )

𝑍𝑐𝑐𝑜𝑠ℎ(𝛾 )

] (3.1a)

in which

γ α + jβ √( + 𝑗𝜔𝐿)(𝐺 + 𝑗𝜔 ) (3.1b)

𝑍𝑐 √𝑅+𝑗𝜔𝐿

+𝑗𝜔𝐶 (3.1c)

In addition, the relationship between the ABCD matrix and the S-parameters is as

follows.

[𝐴 𝐵 𝐷

] [

( + ) ( )+

𝑍𝑜

( + ) ( + )

𝑍 ( ) ( )

( ) ( ∓)+

] (3.2)

in which ZO, which is usually equal to 50Ω, is the characteristic impedance of the

measurement system. Therefore, according to (3.1a)-(3.1c), α, β, and ZC (or γ and ZC) of a

TL can be obtained directly from the measured S-parameters as follows.

α Re(γ) Re {

(

+

±√

(

+ ) ( )

( ) )} (3.3a)

β Im(γ) Im {

(

+

±√

(

+ ) ( )

( ) )} (3.3b)

𝑍𝑐 𝑍𝑜 √( + )

( ) (3.3c)

Once γ and ZC of a TL are obtained from the measured S parameters, the

corresponding TL parameters R, L, G, and C can be determined by the following equations.

Re(γ𝑍𝑐) (3.4a)

35

𝐿 Im(γ𝑍𝑐)/ω (3.4b)

𝐺 Re(𝛾 𝑍𝑐⁄ ) (3.4c)

Im(𝛾 𝑍𝑐⁄ ) 𝜔⁄ (3.4d)

Fig. 3.2 shows the complete small-signal equivalent circuit model of a TL inductor

(including the test pads) on a silicon substrate [3.32], in which Ls1 and Rs1 represent the self

inductance and resistive loss of the metal TL, Lsk and Rsk model the skin effect of the metal

TL at high frequencies, Cox represents the oxide capacitance between the TL and the

substrate, and Rsub and Csub model the loss of the silicon substrate beneath the TL inductor.

The equivalent circuit parameters of the pads Cpad1, Cpad2, Rpad1, and Rpad2 can be extracted

by wideband modeling (2 to 60 GHz) of the dummy open device [3.41], so the effect of the

pads can be easily de-embedded from the measured S-parameters. The simplified

small-signal equivalent circuit model of a TL inductor (excluding the test pads) on a silicon

substrate, in which Reff and Leff represent the equivalent series resistance and equivalent

series inductance, respectively, is also shown in Fig. 3.2.

36

Fig. 3.2: Complete small-signal equivalent circuit model of a TL inductor, in which the

effect of test pads is included.

Based on the theory in [3.32], the expressions of the single-port (i.e., port-2 short)

quality factor (Q-factor) of a TL inductor in terms of its (de-embedded) measured Y

-parameters, which can be converted from the (de-embedded) measured S-parameters, can

be derived as follows [3.32]:

Q 𝜔𝐿

𝑅

Im( 𝑌 ⁄ )

𝑅 ( 𝑌 ⁄ )

𝜔𝐿

𝑅 ×

𝑅𝑝

𝑅𝑝+[(𝜔𝐿 𝑅 ⁄ ) + ]𝑅 × (

𝑅 𝐶𝑝

𝐿 𝜔 𝐿 𝑝) (3.5a)

in which

37

𝐿 𝐿 + 𝐿 𝑘 (𝑅 (𝑅 +𝑅 𝑘)⁄ )

+(𝜔𝐿 𝑘 (𝑅 +𝑅 𝑘)⁄ ) (3.5b)

𝑅 ∥𝑅 𝑘+(𝑅 (𝑅 +𝑅 𝑘)⁄ )

+(𝜔𝐿 𝑘 (𝑅 +𝑅 𝑘)⁄ ) (3.5c)

𝑃

𝜔 𝐶 𝑅

+𝑅 (𝐶 +𝐶 )

𝐶 (3.5d)

𝑝 𝑜𝑥 +𝜔 (𝐶 +𝐶 )𝐶 𝑅

+𝜔 (𝐶 +𝐶 ) 𝑅

(3.5e)

Removal of the silicon underneath the TL inductor will lead to the increase of Rsub and

the decrease of Csub. Clearly, from (3.5a)–(3.5e), at low frequencies, Q-factor is expected to

roughly keep the same value since it is nearly independent of the values of Rsub and Csub,

whereas at medium-to-high frequencies, Q-factor is expected to increase because of the

increase of Rp and the decrease of Cp (due to the increase of Rsub and the decrease of Csub).

In addition, the frequency corresponding to the maximum Q-factor (fmax) is expected to

increase also because of the increase of Rp and the decrease of Cp (due to the increase of

Rsub and the decrease of Csub).

Fig. 3.3: Measured S21 versus frequency characteristics of STD TL-IND1, ICP TL-IND1,

ICP TL- IND2, and ICP TL-IND3 and an equivalent circuit does to calculate the S21 of TL

inductors.

38

From the equivalent circuit shown in Fig. 3.3, the S21 of a TL inductor can be

expressed as follows [3.40]:

𝑆 2𝑉𝐿

𝑉 √

𝑅

𝑅𝐿

𝑅𝐿

(𝑅 +𝑅𝐿+𝑅 )+𝑗𝜔𝐿 √

𝑅

𝑅𝐿

00

( 00+𝑅 )+𝑗𝜔𝐿

if RS=RL=50Ω is specified (3.6)

where RS is the source impedance associated with the voltage source, RL is the load

impedance, and Reff + jωLeff represents the equivalent impedance of the intrinsic part of the

TL inductor (see Fig. 3.2), in which the parasitics resulting from capacitive and resistive

effects (Cox, Csub, and Rsub) are included [see (3.5a)–(3.5e)]. Fig. 3.3 shows the measured

forward gain (S21) of STD TL-IND1, ICP TL-IND1, ICP TL-IND2, and ICP TL-IND3.

Increases of 3.4% (from 0.924 to 0.955) and 1.8% (from 0.789 to 0.803) in S21 were

achieved at 30 and 60 GHz, respectively, for TL-IND1 after the backside ICP etching. This

is mainly attributed to the reduction of silicon substrate-related losses, i.e., the reduction of

Reff of the inductor. In addition, the phenomenon that the measured S21 of the ICP TL

inductors increases with the increase of metal width can be explained by the reduction of

both Leff and Reff , which is mainly due to the reduction of Ls1 and Rs1. To validate the TL

inductor passive model mentioned above, designed variety of 60 GHZ bandpass filter,

composed of series and shunt stubs of modeled CPW lines as the following.

39

3.2. E-band Bandpass Coplanar Filters

According to the Federal Communications Commission (FCC) of USA released

frequency bands from 71 to 76 GHz, 81 to 86 GHz and 92 to 95 GHz, collectively referred

to as E-band, for ultra-high-speed data communications in 2003, applications which exploit

this spectrum have been extensively studied [3.11]. Besides, due to the rapid advance of

process technology, CMOS millimeter-wave monolithic integrated circuits has become a

reality [3.11][3.12][3.2] and drawn a lot of attention because it is cost-effective and

compatible with the silicon-based system-on-a-chip (SOC) technology.

In [3.13], it has been demonstrated that for coplanar passive devices implemented in a

GaAs technology, the design methods used in centimeter-wave frequencies, such as the

analytical models based on quasi-TEM approximation, are also workable for

millimeter-wave frequencies up to W-band (75-110 GHz). To demonstrate that the design

methods in [3.13] can also be applied to the CMOS coplanar passive devices in the

millimeter-wave frequencies, two test third-order quarter-wavelength double-shorted-stubs

wideband bandpass coplanar filters in the E-band are implemented. The details of the filters

are described later in the next section. Besides, to study the substrate effects on the

performances of the filters, the CMOS-compatible inductively-coupled-plasma (ICP) deep

trench technology is used to selectively remove the silicon underneath the filters completely

[3.14].

3.2.1 Filter Structure

Two third-order quarter-wavelength double-shorted-stubs wideband bandpass coplanar

40

filters in the E-frequency bands are implemented. The first filter (i.e. filter-1 in this work,

see Figs. 3.4(a) and 3.4(b)) was implemented with a 0.18 um RF-CMOS technology on a

p-type silicon substrate with thickness of 300 um and resistivity of 20Ω-cm. The main

features of the backend processes are as follows. There are 6 metal layers, named M1 to M6

from bottom to top. The thickness of M6 and M1 is 2.06 um and 0.48 um, respectively, and

that of M2-M5 is 0.58 um. The oxide thickness between M6 and M5, between the other

adjacent metal layers, and between M1 and the silicon substrate is 1 um, 0.8 um, and 1 um,

respectively. Besides, to study the top-metal-thickness effects on the filter, another filter (i.e.

filter-2 in this work) was also implemented by a similar CMOS technology with thinner

top-metal thickness of 0.93 um. The other layout parameters of filter-1 and filter-2 are the

same.

41

Fig. 3.4: (a) Front-side die photo (before ICP etching) of filter-1. (b) top-view and 3D

schematic diagrams of filter-1. (c) backside die photo (after ICP etching) of filter-2.

Fig. 3.4(a) shows the front-side die photo of filter-1. Fig. 3.4(b) shows the top-view

and 3D schematic diagrams of filter-1, with detailed layout parameters labeled. After the

filters were fabricated, post-IC ICP processing was done on the backside of the die.

Specifically, the silicon substrate below the rectangular area surrounded by the dash line as

Silicon Subtrate

M5-Bridges

M6

Signal

M6

Ground

M6

Ground

(b)

(a)

Backside die photo of filter-2

(after ICP Etching)

(c)

Front-side die photo of filter-1

(before ICP Etching)

G

G

S

G

G

S

1570

VIA

M5

M6

Unit: m

260 300

990

3-D Plot

30

30

150

42

indicated in Fig. 3.4(a) was fully dry-etched away. The post-processing flow is shown in

Fig. 3.1. First, the photolithography was done on the backside. Then, ICP was used to etch

the open area from the backside. Finally, the photoresist on the backside was cleaned for

test purpose. Fig. 3.4(c) shows the backside die photo (after the backside ICP etching) of

filter-2. Clearly, the front-side pattern of the filter can be seen from the backside. That is,

the silicon underneath the filter has been fully dry etched away.

3.2.2 Measurement Results and Discussions

The frequency-dependent S-parameter measurements were performed from 2 to 110

GHz by an Agilent E7350A vector network analyzer. Fig. 3.5(a) shows the measured and

simulated S11 of filter-1 (top metal thickness of 2.06 um) after the backside ICP etching. Fig.

3.5(b) shows the measured and simulated S21 of filter-1 after the backside ICP etching. As

can be seen, the simulated results conform with the measured results well. Figs. 3.6(a) and

3.6(b) show the measured S11 and S21, respectively, of filter-1 both before and after the

backside ICP etching. The results show that the input matching bandwidth, i.e. S11 below

-10 dB, moved from lower 38.1-73.2 GHz-band (35.1-GHz-wide) to higher 49.4-84

GHz-band (34.6-GHz-wide), and the 3-dB bandwidth of S21 moved from lower 38.4-69.7

GHz-band (31.3-GHz-wide) to higher 47.1-83 GHz-band (35.9-GHz-wide) for filter-1 after

the backside ICP etching. In addition, a 4.58 dB improvement (from -8.38 dB (at 50.4 GHz)

to -3.8 dB (at 53.2 GHz)) in peak S21 was achieved for filter-1 after the backside ICP

etching. These results show that the backside ICP etching is effective to reduce the

substrate loss and parasitic capacitance in the millimeter-wave frequency bands, and hence

is very promising for millimeter-wave CMOS RFIC applications.

43

Figs. 3.7(a) and 3.7(b) show the measured S11 and S21, respectively, of filter-2 (top

metal thickness of 0.93 um) both before and after the backside ICP etching. The results

show that the input matching bandwidth moved from lower 39.8-81.4 GHz-band

(41.6-GHz-wide) to higher 55.9-94.1 GHz-band (38.2-GHz-wide), and the 3-dB bandwidth

of S21 moves from lower 43.5-76.3 GHz-band (32.8-GHz- wide) to higher 54.5-93.3

GHz-band (38.8-GHz-wide) for filter-2 after the backside ICP etching. In addition, a 4.67

dB improvement (from -8.86 dB (at 58.5 GHz) to -4.19 dB (at 74.5 GHz)) in peak S21 was

achieved for filter-2 after the backside ICP etching. Note that the top metal thickness of

filter-2 (0.93 um) is thinner than that (2.06 um) of filter-1, which in turn results in smaller

parasitic capacitance and larger resistive metal loss. This explains why compared with

filter-1, filter-2 exhibits higher operation-frequency-band and a little lower peak S21.

Fig. 3.5: Measure and simulated (a) S11 and (b) S21 of filter-1 after the backside ICP

etching.

44

Fig. 3.6: Measured (a) S11 and (b) S21 of filter-1 both before and after the backside ICP

etching.

Fig. 3.7: Measured (a) S11 and (b) S21 of filter-2 both before and after the backside ICP

etching.

45

Fig. 3.8: The lumped-element model of the filter

In order to gain more insights of the substrate effects on the filters, a lumped-element

model is built and the corresponding parameters are extracted from the measured data. The

schematic of the modeling network is shown in Fig. 3.8. Because the modeling is

performed from 2GHz up to 100GHz, the distributed effect has to be taken into account. In

the lumped-element model, Ls represents the inductance induced by via56 connected metal

6 to metal 5, Cpr represents the capacitance between the underpass and M6, Cs represents

the capacitive coupling between M5 and M6, and the other parameters represent the

substrate parasitics. Table 3.1 summarizes the value of each lumped element.

46

Table 3.1: Extracted small-signal equivalent circuit parameters of the E-band bandpass

filter both before and after the ICP etching

STD E-band bandpass filter ICP E-band bandpass filter

Cp(fF) 80 80

Cs(fF) 40 40

Cpr (fF) 80 56

Cox (fF) 20 18.5

Csub(fF) 200 17

Rsub(Ω) 266 1860

Lp(pH) 60 60

Ls(pH) 10 10

3.3 50 GHz/60 GHz Phi Filters

With the advance in semiconductor technology, RF CMOS processes have become

more and more popular for RF-ICs operated in the millimeter-wave frequency bands

[3.12],[3.2]. It has been envisioned that the ultimate performance-limiting factor of silicon

millimeter-wave system-on-a-chip may be the substrate loss. Various methods have been

proposed to reduce the substrate loss of RF passive devices, such as (wet etching based)

47

front-side and backside micromachining [3.16][3.17], porous silicon [3.18], proton

implantation [3.19], and substrate transfer [3.20], etc. However, since most of these

methods are not compatible with standard CMOS technology, there are few, if any, reports

on the integration of the passive components fabricated in these techniques together with

other active circuits on the same chip. In this section, we have demonstrated that the

CMOS-compatible inductively coupled-plasma (ICP) deep trench technology, which

selectively removes the silicon underneath the passive components, can significantly

improve the gain and noise figure performances of a CMOS bifilar transformer for 3.1–10.6

GHz ultra-wideband (UWB) system applications [3.21]. In this work, to study the silicon

substrate effects at the millimeterwave frequency bands, we further apply the proposed ICP

technique to 50 and 60 GHz bandpass filters.

3.3.1 Filter Design and Structure

The 50 and 60 GHz bandpass filters in the work were implemented in a standard 0.18

um 1P6M CMOS technology. Fig. 3.9(a) shows the front-side die photo of the 50 GHz

filter, with detailed layout parameters labeled. In the central part of the filter, metal strips in

the shape of φ(Phi), i.e., three inductors in parallel, were used to generate the small value of

inductance needed for LC resonance at 50 GHz. In this way, the equivalent inductance of

the filter is less sensitive to the dimension variation of the metal strips due to

photolithography and etching processes. That is, the φ-filter exhibits larger design margin.

Fig. 3.9(b) shows the 3D schematic diagram at the input port. As can be seen, the small

overlapping capacitance between M6 and M4 was connected in series with the φ-patterned

inductance. Consequently, a series LC resonator which exhibited a bandpass characteristic

48

was formed. Fig. 3.14 shows the small-signal equivalent circuit model of the proposed

bandpass filter. Ls represents the inductance induced by Via45 connected metal 4 to metal 5

and its surrounding metal strips. Cp represents the capacitance between the M4 underpass

and M6. Cs represents the coupling capacitance between M4 and M6. And the parameters

Cox, Csub, and Rsub model the pads for testing. In addition, the distributed network with

parameters Lt, Lm, C, and C1 models the φ-shaped metal strips in the central part of the

filters.

(a) (b)

Fig. 3.9: Layout of the proposed bandpass filter (a) the 50GHz filter and (b) 3D schematic

diagram at the input port of the proposed bandpass filter.

The structures were initially simulated by the EM simulator ANSYS HFSS™ and

taped out. After the filters were fabricated, the post-IC processing is applied to remove the

substrate selectively. Fig. 3.10 is the backside photo of the ICP chip. As we can see, the

49

sidewalls on the opening window are very sharp and the front-side strips can be seen

clearly without silicon remained.

Fig. 3.10: Backside chip photo

Fig. 3.11: S11 and S21 of the 50GHz filter.


The S parameters of the filters were measured by an Agilent E7350A vector network

analyzer from 1 to 80 GHz. To be compatible with the on-wafer measurement system, the

test pads were designed in the form of Ground-Signal-Ground coplanar waveguide. Fig.

50

3.11 shows the measured input return loss (S11) and power gain (S21) of the 50 GHz filter

both before and after the ICP etching. As can be seen, after the ICP etching, the S11 and S21

of the filter were slightly blue shifted due to the reduction of the parasitic capacitance, and

the peak value of S21 was improved by 1.6 dB (from -5.2 to -3.6 dB) due to the elimination

of substrate loss. Besides, a 1.9 dB improvement (from -11.1 to -13 dB) in S11 was also

achieved. The same results can be observed in the 60 GHz filter as illustrated in Fig. 3.12,

where a 2.6 dB (from -8.2 to -5.6 dB) improvement in S21, and a 3.2 dB (from -6.4 to -9.6

dB) improvement in S11 were achieved at 60 GHz. Note that the reflection effect must be

taken into account when the insertion losses of passive devices are compared. To exclude

the effect of interfacial impedance mismatch, maximum available power gain (GAmax) is

derived from the measured S parameters according to [3.7] and shown in Fig. 3.13. As can

be seen from Fig. 3.10, for the 50 GHz filter, a 1.5 dB (from -4 to -2.5 dB) improvement in

GAmax was achieved at 50 GHz. In addition, for the 60 GHz filter, a 2.1 dB (from -5.8 to

-3.7 dB) improvement in GAmax was achieved at 60 GHz.

Fig. 3.15 shows the measured and modeled S-parameters (from 2 to 50 GHz) of the 50

GHz filter both before and after the ICP etching. As can be seen, the modeled results

conformed with the measured results well, further verifying the reliability of the extracted

parameter values.

To study the silicon substrate effects on the millimeter-wave filters fabricated by a

foundry-provided standard RF-CMOS process (substrate resistivity≅20Ω． cm), the

small-signal equivalent circuit parameters of the 50 GHz and 60 GHz filters are extracted

based on the measured data. Table 3.2 is a summary of the extracted parameter values of

the 50 GHz filter. As can be seen, the proposed ICP process can effectively reduce the

51

substrate related parasitic capacitances, such as Csub and Cp, and the resistive substrate loss

Rsub. Besides, the quality factors of the inductors can be significantly improved after the

ICP etching. For example, a 295.8% (from 9.6 to 38) improvement in quality factor at 50

GHz was achieved for inductor Lt after the ICP etching. These results show that the

backside ICP etching is very promising for millimeter-wave RFIC applications.

Fig. 3.12: S11 and S21 of the 60GHz filter

Fig. 3.13: Maximum available power gain derived from the measured S parameters.

52






the lumped-element model the three branches in the middle represent the distributed

components of phi-patterned strips, Ls represents the inductance induced by via45, Cp

represents the capacitance between the underpass and M6, Cs represents the capacitive

coupling between M4 and M6, and the other parameters represent the substrate parasitics.

Table 3.2 summarizes the value of each lumped element. The modeling results is shown in

Fig. 3.15, which reveals that the quality factors (Qt)of the inductors are markedly improved

(9.6 to 38) after substrate removal and the parasitic capacitance like Csub, Cp and substrate

loss Rsub are all reduced by the proposed technique.

53

Table 3.2: Extracted small-signal equivalent circuit parameters of the 50 GHz filter both

before and after the ICP etching

STD 50GHz Filter ICP 50GHz Filter Improvement

Cp(fF) 8.6 4

Cs(fF) 54 26

C (fF) 34 26

Cox (fF) 18.5 18.5

Csub(fF) 180 17

Rsub(Ω) 276 2160

Lt(pH) 633 633

Lm(pH) 266 266

Ls(pH) 51 51

Qt(=Wt/Rt)@50GHz 9.6 38 295.8﹪

54

Fig. 3.15: Comparison between modeling and measurement results from smith chart.

55

3.4 V-band CMOS bandpass filter

The outband suppression of conventional second-order filters is usually not

satisfactory. Therefore, there have been some proposals to improve this problem. For

example, in [3.23], a shunt-feedback capacitor is added between the input and the output of

a traditional filter to generate two finite transmission zeros at opposite sides of the passband.

In [3.24], a series-feedback capacitor is added between the two parallel LC resonators of a

traditional filter and the ground to generate two finite transmission zeros at opposite sides

of the passband. The disadvantage of these filter architectures is that the two transmission

zeros cannot be tuned individually. In this section, a bandpass filter architecture with two

finite transmission zeros (at opposite sides of the passband), which can be tuned

individually, is proposed, as shown in Fig. 3.13(a). The filter architecture is equivalent to

the conventional filter architecture with transmission zeros at DC and infinite frequency

[3.23] if the series feedback capacitance Cs (for generating 𝜔 z1) =∞ and the

shunt-feedback capacitance Cp (for generating 𝜔z2) = 0.

3.4.1 Filter structure

The filter was implemented by a 0.13 um CMOS process. The interconnection lines as

well as the microstrip-line (MSL) inductors were placed on the 0.35 mm-thick topmost

metal (M8) to minimize the resistive loss. The pattern and density of the M1 ground-plane

was optimized to minimize both the substrate loss and the eddy current loss on the

ground-plane. The front-side die photo of the filter is shown in Fig. 3.16(b). Note that C3

and C4 were realised by the parasitic capacitance of inductors L1 and L2, respectively. After

the filter was fabricated, post-IC ICP processing (shown in Fig. 3.16(c)).

56

3.4.2 Measurement Results and Discussions:

The S-parameter measurements were performed from 2 to 110 GHz by an Agilent

E7350A VNA. Fig. 3.17(b) shows the measured and simulated S21 and S11 versus frequency

characteristics of the filter. As can be seen, the measured results are consistent with the

simulated results. This filter achieved insertion-loss (1/S21) lower than 3 dB over the

frequency range of 52.5-76.8 GHz. The minimum insertion-loss was -2 dB at 63.5 GHz.

Besides, the filter achieved S11 better than –10 dB over the frequency range of 51.2-78.8

GHz and the S21 of this filter (–2 dB at 63.5 GHz) is better than those (–2.7 dB ~ –4.9 dB)

of the CMOS filters in [3.25]-[3.27], that (–6.4 dB at 77.3 GHz) of the SiGe filter in [3.6],

and that (–3.4 dB (@40 GHz)) of the filter on insulated silicon substrate (achieved by

proton implantation) and that (–10 dB (@40 GHz)) of the filter on normal silicon substrate

with an additional 1.5-um-thick oxide isolation layer.

57

Fig. 3.16: Equivalent circuit (a), front-side die photo (b), and backside die photo (after ICP

etching) of fabricated V-band CMOS filter (c)

58

Fig. 3.17: Simulated and measured S21 and S11 against frequency characteristics of

proposed filter

59

3.5 CPW BandPass Filter Utilizing the LC Structure

3.5.1 Filter Structure

The bandpass filter was designed and implemented by a standard 0.18 um 1P6M (one

polysilicon and six metals) CMOS process (on a p-type silicon substrate with thickness of

300 um and resistivity of 8~12 cm) provided by a commercial foundry. This technology

offers n+ and p

+ poly-silicon resistor, MIM capacitor, and six metal layers, named M1 to

M6 from bottom to top. The thickness of M6 is 2.34 um, and that of M1~M5 is 0.53 um.

Fig. 3.18 shows the top view and cross-sectional schematic diagrams of the CMOS V-band

bandpass filter, with the important parameters labeled. The signal line, the ground plane,

and the top metal (M6) of the MIM capacitor are formed with the 2.34 um-thick topmost

metal to minimize the resistive loss. The bottom metal of the MIM capacitor is formed with

M5. Two parallel-connected quarter-wavelength (𝝀/4) short stubs are placed in 𝝀/4 distance

and are series-connected to the 𝝀/4 transmission line through a metal-insulator-metal (MIM)

capacitor Cs [3.13]. The center frequency of the filter is determined by the length of the

short stubs, whereas the lower 3-dB and the higher 3-dB frequency are determined by the

value of the series capacitor (Cs) and the shunt LC resonator, respectively. To reduce the

chip size of the filter, the short stubs of the filter are folded inward to the ground in the

middle of the filter. In addition to achieving a smaller chip size, this folding technique also

provides the needed ground plane for the LC resonator in the middle of the filter.

60

LC resonator

Cs

(a)

sLsC

pCpL

z2

short

1@ω

LC C

L

sL

pL pC

sC Port-2

LCZ

inZ

z1

p s

2open @ω

L C

50

50

SV

Port-1

(b)

Fig. 3.18: (a) Top view and cross-sectional schematic diagrams, and (b) small-signal

equivalent circuit model of the V-band CMOS bandpass filter.

61

Fig. 3.18(b) shows the small-signal equivalent circuit model of the filter for S11 and

S21 calculation. Lp and Cp are the equivalent parallel inductance and parallel capacitance,

respectively, of each of the parallel-connected short stubs. Ls is half of the equivalent series

inductance of the series-connected transmission line. Cs is the capacitance of the

series-connected MIM capacitor. L and C are the equivalent series inductance and series

capacitance, respectively, of the LC resonator. The mechanism of the filter operation can be

briefly described follows: The two Lp/Cp resonators can generate two poles supporting the

passband of the filter. Over the passband, the majority of the signal energy from the input

port is coupled through Ls/Cs to the output port. Since LC resonator forms a resonant

short-circuit path at the frequency of high-frequency transmission zero (z2), z2 can be

tuned individually by changing the structure of the LC resonator. In addition, at low

frequencies, the input impedance Zin of the filter is equivalent to a parallel Leff-Ceff network,

in which Leff ~ Lp and Ceff ~ Cs/2. This means there is a low-frequency transmission zero

(z1) at the frequency of about √𝟐/√𝑳𝑷𝑪𝑺. Clearly, z1 can be tuned individually by

changing the overlap length of the MIM capacitor Cs.

The 3D full-wave electromagnetic field simulation of the bandpass filter is done by

using the industry-standard simulation tool ANSYS HFSS™. Fig. 3.19(a) shows the

simulated S21 and S11 versus frequency characteristics of the bandpass filter at various MIM

capacitor dimensions. As can be seen, the high-frequency transmission zero (or the higher

3-dB frequency) remains the same, while the low-frequency transmission zero (or the lower

3-dB frequency) decreases with the increase of the overlap length between the top metal

(M6) and the bottom metal (M5) of the MIM capacitor.

62

(a)

(b)

Fig. 3.19: (a) Simulated S21 and S11 versus frequency characteristics of the bandpass filter at

various MIM capacitor dimensions. (b) Simulated S21 and S11 versus frequency

characteristics of the bandpass filter at various LC resonator gaps.

Fig. 3.19(b) shows the simulated S21 and S11 versus frequency characteristics of the

bandpass filter at various LC resonator gaps. As can be seen, the higher 3-dB frequency is

equal to 101 GHz, 85 GHz, and 75 GHz, respectively, for the case with LC resonator gap of

0um, 20um, and 40um. That is, the higher 3-dB frequency (or the high-frequency

transmission zero) decreases with the increase of the gap between the LC resonator and the

ground plane. Since the low-frequency transmission-zero (ωz1) and the high-frequency

63

transmission-zero (ωz2) can be tuned individually by adjusting the value of the series

capacitor (Cs) and the size of the built-in LC resonator, respectively, the design of the

proposed filter is more flexible than previous work.


Fig. 3.20(a) shows the front-side chip micrograph of the bandpass filter. The chip area

is only 0.44×0.36 mm2, i.e. 0.158 mm

2, excluding the test pads. After the filter was

fabricated, post-IC ICP processing (shown in Fig. 3.1) was done on the backside of the die.

First, the photolithography was done on the backside. Then, ICP was used to etch the open

area (i.e. the area enclosed by the dash lines in Figs. 3.20(a) and 3.20(b)) from the backside.

Finally, the photoresist on the backside was cleaned for test purpose. Fig. 3.20(b) shows the

backside chip micrograph of the filter. Clearly, the silicon underneath the filter is indeed

nearly fully dry etched away since the front-side pattern can be seen from the backside.

(a) (b) Fig. 3.20: (a) Front-side die photo, and (b) backside die photo (after ICP etching) of the

fabricated V-band CMOS filter.

On-wafer S-parameters measurement was performed by an Agilent E7350A Vector

Network Analyzer. Fig. 3.21 shows the measured and simulated S21 and S11 versus

Backside

64

frequency characteristics of the filter both with and without the substrate removal. The

simulation results agree reasonably well with the measurement results. After the substrate

removal, the filter achieves insertion-loss (1/S21) lower than 3 dB over the frequency range

of 46.5~85.5 GHz. Compared with the measured S21 of the filter without the substrate

removal, a gain enhancement of 2.5 dB is achieved at 80 GHz. The minimum

insertion-loss is -1.8 dB at 60 GHz, better than those reported in [3.6]-[3.10], [3.13]. To our

knowledge, this is one of the best results ever reported for a V-band CMOS bandpass filter

in the literature. In millimeter-wave applications, the substrate parasitics usually dominate

the performance of a circuit and obscure the resonance nature of its constituent

transmission lines and devices. As can be seen in Fig. 3.21, by removing the substrate

parasitics, the resonance property of the two-order filter is revealed again. That is, the two

S11 dips are explicit again and the rising/falling edges in the S21 curves become sharper. The

application of the substrate removal also leads to a wider impedance matching bandwidth

(50.5~90 GHz) and an expanded S21 bandwidth (from 46~82.5 GHz to 46.5~85.5 GHz).

65

0 20 40 60 80 100-60

-50

-40

-30

-20

-10

0

10

Measurement (w/o substrate removal)

Measurement (w/i substrate removal)

Simulation (w/i substrate removal)

10 dB

Frequency (GHz)

S1

1 (

dB

)

(a)

0 20 40 60 80 100-50

-40

-30

-20

-10

0

10

20 Measurement (w/o substrate removal)

Measurement (w/i substrate removal)

Simulation (w/i substrate removal)

Frequency (GHz)

S2

1 (

dB

)

(b)

Fig. 3.21: Measured and simulated S21 and S11 versus frequency characteristics of the

bandpass filter both with and without the silicon substrate removal.

66






the lumped-element model, Ls represents the inductance induced by via56 connected metal

5 to metal 6, Cpr represents the capacitance between the underpass and M6, Cs represents

the capacitive coupling between M5 and M6, and the other parameters represent the

substrate parasitics. Table 3.3 summarizes the value of each lumped element.

67

Table 3.3: Extracted small-signal equivalent circuit parameters of the V-band bandpass

filter both before and after the ICP etching

STD V-band bandpass Filter ICP V-band bandpass Filter

Cpr (fF) 8.6 4

Cs (fF) 820 820

C (fF) 90 90

Cp (fF) 100 100

Cox (fF) 20 20

Csub(fF) 260 20

Rsub(Ω) 276 3760

Ls(pH) 80 80

L (pH) 30 30

Lp(pH) 60 60

Fig. 3.23(a) shows the chip micrograph of a test filter with the series capacitor (Cs) but

without the LC resonator. Fig. 3.23(b) shows the measured S-parameters versus frequency

characteristics of the test filter. As can be seen, there is a low-frequency transmission zero

of S21 at 40 GHz because of Cs. Fig. 3.24(a) shows the chip micrograph of a test filter

68

without the series capacitor (Cs) but without the LC resonator. Fig. 3.24(b) shows the

measured S-parameters versus frequency characteristics of the test filter. As can be seen,

there is a high-frequency transmission zero of S21 at 71 GHz because of the LC resonator.

These results are consistent with those in Figs. 3.19 and 3.21.

(a)

0 20 40 60 80 100 120-80

-70

-60

-50

-40

-30

-20

-10

0

S2

1 (

dB

)

Frequency (GHz)

Measurement

-20

-15

-10

-5

0

5

10

15

20

25

30

-10 dB

S21

S1

1 (

dB

)

S11

(b)

Fig. 3.23: (a) Chip micrograph, and (b) measured S-parameters of a test filter with the

series capacitor (Cs) but without the LC resonator.

69

(a)

0 20 40 60 80 100 120-80

-70

-60

-50

-40

-30

-20

-10

0

S2

1 (

dB

)

Frequency (GHz)

Measurement

-10 dB

-40

-20

0

20

40

60

80

100

S21

S1

1 (

dB

)

S11

(b)

Fig. 3.24: (a) Chip micrograph, and (b) measured S-parameters of a test filter without the

series capacitor (Cs) but with the LC resonator.

Table 3.4 is a summary of the implemented V-band CMOS bandpass filter, and

recently reported state-of-the-art bandpass filters on silicon in [3.6], [3.7]-[3.9][3.27],

[3.15]. As can be seen, the proposed filter occupies small chip area and achieves good S11

and S22 (not shown here) performances. Besides, the S21 of our filter (–1.8 dB at 60 GHz) is

better than that (–6.4 dB at 77.3 GHz) of the SiGe filter in [3.6], those (–2.7 dB~ –4.9 dB)

of the CMOS filters in [3.7]-[3.9][3.27], and that (–3.4 dB at 40 GHz) of the filter on

insulated silicon substrate (achieved by proton implantation) and that (–10 dB at 40 GHz)

70

of the filter on normal silicon substrate with an additional 1.5-um-thick oxide isolation

layer in [3.15].

71

Table 3.4 Summary of the implemented V-band CMOS bandpass filter, and recently

reported state-of- the-art CMOS bandpass filters.

References Maximum S21

Center

Frequency

wo

3-dB Bandwidth S11 Chip

Area

Process

Technology

This Work –1.8 dB

(@60 GHz) 66 GHz

59.1%

(46.5~ 85.5 GHz) < –10 dB

0.158

mm2

0.18 um

CMOS

[3.6]

(2007-MWCL)

–6.4 dB

(@77.3 GHz) 77.3 GHz

15.5%

(71.3~ 83.3 GHz) ≦–6.2 dB

0.107

mm2

0.14 um

SiGe

[3.7]

(2008-EDL)

–4.9 dB

(@64 GHz) 64 GHz

18.75%

(58~ 70 GHz) < –10 dB

1.71

mm2

0.18 um

CMOS

[3.8]

(2008-EDL)

–2.8 dB

(@60 GHz) 62 GHz

25.8%

(54~ 70 GHz) < –10 dB

0.608

mm2

0.18 um

CMOS

[3.9]

(2008-MWCL)

–3.6 dB

(@70 GHz) 70 GHz

25.7%

(61~ 79 GHz) < –10 dB

0.436

mm2

0.13 um

CMOS

[3.27]

(2007-EDL)

(Filter at M5)

–3.9 dB

(@60 GHz) 60 GHz

51.8%

(44.46~ 75.54

GHz)

< –10 dB 0.254

mm2

0.18 um

CMOS

[3.27]

(2007-EDL)

(Filter at M6)

–2.7 dB

(@65 GHz) 65 GHz

51.3%

(43.33~ 76.67

GHz)

< –10 dB 0.254

mm2

0.18 um

CMOS

[3.15]

(2002-MWCL)

(w/i proton imp.)

–3.4 dB

(@40 GHz) 40 GHz

22.5%

(35.5~ 44.5 GHz) ≦–9.5 dB 0.4 mm

2 Si Substrate

[3.15]

(2002-MWCL)

(w/o proton imp.)

–10 dB

(@40 GHz) 40 GHz

22.5%

(35.5~ 44.5 GHz) <–10 dB 0.4 mm

2

Si Substrate

(w/i

1.5-um-thick

oxide

isolation)

72

3.6 SiGe HBT Ultrawideband Low-Noise Amplifier

Recently, SiGe HBT ultra-wideband (UWB) systems have attracted a lot of attention

because they are capable of high data-rate transmission with low power consumption

[3.28–3.31]. UWB LNA is a critical block in UWB receiver front-end design. To amplify

the small radio-signals received from the whole UWB band (3.1–10.6 GHz) with a good

signal-to-noise ratio property, high and flat power gain S21, good input impedance matching

(i.e. low input return loss S11), and good noise figure (NF) performances across the whole

UWB band are required. However, the performances of the inductors in the SiGe HBT

UWB LNAs, such as the quality factor (Q-factor) and the noise figure (NF), are usually not

satisfactory due to the effects of frequency-dependent substrate loss, such as the skin effect

and the eddy current loss in the silicon substrate [3.32]. As a result, the performances of the

SiGe HBT UWB LNAs are limited by the substrate loss.

Various methods have been proposed to reduce the substrate loss of RF passive

devices, such as (wet etching based) front-side and backside micromachining [3.33]–

[3.35][3.17], porous silicon [3.36][3.37], pro-ton implantation [3.19], and substrate transfer

[3.38], etc. However, most of the proposed methods are inherently non-standard BiCMOS

(or CMOS) processing steps. For example, all the classical micromachining techniques in

[3.6][3.33]–[3.35][3.17] include at least a wet-etching process step, which is not compatible

with the standard BiCMOS (or CMOS) technology. Fortunately, this problem can be

improved to a large extent by our proposed BiCMOS compatible backside

inductively-coupled-plasma (ICP) deep trench technology, which removes the silicon

underneath the inductors as a whole [3.21]. Though ICP etching has been used previously

for suspended CMOS RF passive devices [3.39], the silicon-substrate-etching is normally

73

partial and starts from the front-side rather than the backside. In contrast, the proposed

technology can achieve more improvement. Besides, compared with traditional backside

wet bulk micromachining in [3.17], dry backside ICP etching has the advantages of forming

vertical sidewalls and being fully BiCMOS process compatible since it is a standard

processing technique in modern BiCMOS technology.

In this section, the removal of the silicon underneath a SiGe HBT IC with on-chip

inductors based on ICP deep-trench technology is demonstrated by a SiGe HBT UWB LNA

fabricated on a 400-um-thick silicon substrate. Satisfactory improvement in power gain (S21)

and noise-figure (NF) performances are achieved.

3.6.1. UWB LNA Design

Fig. 3.25(a) shows the schematic of the proposed SiGe HBT UWB LNA. UWB input

impedance matching was achieved by the capacitive feedback technique [3.30]. That is, the

feedback capacitor CF of the first-stage amplifier could transfer its RC load, which

comprised the input impedance of the second stage amplifier in parallel with the load

resistance R1 of the first stage, to the necessary input resistance of 50Ω. Besides, the

proposed four-stage UWB LNA could also achieve high and flat UWB S21 characteristic,

which can be explained by the pole-zero cancellation theory as follows: The bandwidth of

the first two-stage amplifier was limited by its two low-frequency poles. Therefore, an

inductive-feedback third-stage was introduced to generate one low-frequency zero (to

cancel one of the two low-frequency poles of the first two-stage amplifier) and two

complex conjugate high-frequency poles (to enhance the bandwidth). In addition, an

inductive-degenerative common-drain fourth-stage was introduced to be a buffer stage and

74

to improve the linearity of the UWB LNA. As the bias resistor R5(=1000Ω) was negligible,

the transfer function of the fourth-stage can be derived as follows:

𝑉 𝑡4

𝑉𝑖𝑛4≈

𝐿3𝑅𝐿𝑔𝑚4

𝐿3( +𝑔𝑚4𝑅𝐿)+𝑅𝐿 (3.7)

in which gm4 is the transconductance of transistor Q4, and RL is the loading resistance.

From (3.7), it is clear that the another low-frequency pole of the first two-stage amplifier,

which is close to zero frequency, can be cancelled by the zero generated by the fourth stage.

In this way, a SiGe HBT UWB LNA with bandwidth decided by the poles of the

inductive-feedback third-stage is realized.

On the basis of the aforementioned circuit design principle, we designed a SiGe HBT

UWB LNA. The process adopted was a standard 0.35 um SiGe HBT process (on a p-type

silicon substrate with thickness of 400 um and resistivity of 10Ω．cm) provided by a

commercial foundry. The component parameters were as follows: L1 =L2 =L3 =0.6 nH, R1

=250Ω, R2 =150Ω, R3 =2000Ω, R4 =100Ω, R5 =1000Ω, CF=18 fF, and C1 =C2 =C3 =3 pF.

All transistors (Q1, Q2, Q3, and Q4) had the same emitter size of 0.3 um×20.3 um×1 emitter

finger.


Fig. 3.26(b) shows the front side (before the ICP etching) and the backside (after the

ICP etching) chip micrographs of the SiGe HBT UWB LNA. The chip area was only

600×400 um2

excluding the test pads. As can be seen from the backside chip micrograph,

the exposed front side on-chip inductors were visible to the naked eye, which means the

75

silicon underneath the UWB LNA indeed had been almost fully dry-etched away. The noise

and scattering parameters were measured on-wafer using an automated NP5 measurement

system from ATN Microwave, North Billerica, MA. The SiGe UWB LNA was biased at 4

mA and 1.9 V, 3.7 mA and 1.6 V, 1.1 mA and 1 V, and 8 mA and 1 V for the first, second,

third and fourth stages, respectively; i.e., the power consumption is 22.62 mW.

76

Fig. 3.25: (a) Schematic of the SiGe HBT UWB LNA. (b) Front side (before the etching)

and backside (after the etching) chip micrographs of the SiGe HBT UWB LNA. The LNA

occupied an area of 0.6×0.4 mm2, excluding the test pads.

77

Fig. 3.26: (a) shows the measured input return loss (S11) versus frequency characteristics of

the SiGe HBT UWB LNA both before and after the backside ICP etching.

For the LNA before the ICP etching, S11 below -10 dB was achieved for frequencies

2.5–14.2 GHz. For the LNA after the ICP etching, S11 below -10 dB was achieved for

frequencies 2–13.7 GHz. The broadband input matching performance of the LNA was

attributed to the small input inductance (L1 =0.6 nH) due to the adoption of the capacitive

78

feedback technique, which used the Miller effect to enlarge the input capacitance. For an

inductor on silicon, its effective inductance Leff, and effective series resistance Reff can be

represented as follows [3.5]:

𝐿 ≈ 𝐿𝑑𝑐 𝐿 (𝜔𝑀 )

𝑅 +(𝜔𝐿 )

(3.8a)

≈ 𝑑𝑐 +𝑅 (𝜔𝑀 )

𝑅 +(𝜔𝐿 )

(3.8b)

Ldc and Rdc represent the self-inductance and resistive loss of the inductor. The

transformer loop, including resistance Rs1, inductance Ls1, and mutual inductance Ms1, takes

into account the effects of frequency-dependent substrate loss, such as the skin effect and

the eddy current loss in the silicon substrate. The removal of the silicon underneath the

inductor would lead to an increase of Rs1 (to close to infinity) and a decrease of Ls1 and Ms1

(to close to zero). This in turn resulted in an increase of Leff and a reduction of Reff, i.e., an

increase of the quality factor of the inductor. Clearly, the “shift” of the frequency band, i.e.,

the decrease of the valley frequency of the measured S11 from 10 GHz (before the etching)

to 8.5 GHz (after the etching), can be attributed to the increase of Leff of the input inductor

L1.

What is also shown in Fig. 3.26(a) is the measured S21 versus frequency characteristics

of the SiGe HBT UWB LNA both before and after the backside ICP etching. The peak S21

of the UWB LNA after the ICP etching was 13.7 dB (at 11.5 GHz), which was 2.4 dB

higher than that (11.3 dB at 10.5 GHz) of the UWB LNA before the ICP etching. The

significant improvement in S21 of the UWB LNA after the backside ICP etching was

attributed to the increase of the quality factors (or the reduction of the silicon substrate loss)

79

of the inductors in the UWB LNA.

Fig. 3.26(b) shows the measured noise figure (NF) versus frequency characteristics of

the SiGe HBT UWB LNA both before and after the backside ICP etching. Over the

frequency range of 1.8–13 GHz, NF of 1.12–6.43 dB was achieved for the UWB LNA

before the ICP etching, and excellent NF of 0.9–5.93 dB was achieved for the UWB LNA

after the ICP etching. A significant improvement of 0.59 dB and 0.74 dB in NF was

achieved at 10 GHz and 13 GHz, respectively, for the UWB LNA after the backside ICP

etching. This is also attributed to the increase of the quality factors (or the reduction of the

silicon substrate loss) of the inductors in the UWB LNA.

3.7 Summary

In this section, transmission line theory is utilized to analyze measurement results in

the previous sections to gain more insights of the substrate effects on the bandpass filter.

Fig. 3.27 is the lumped model of the first-order bandpass filter. The ABCD matrix can

be derived as follows.

Fig. 3.27: The lumped model of the first-order bandpass filter.

80

[𝐴 𝐵 𝐷

] [ 0𝑌

] [ 𝑍 0

] [ 0𝑌𝑃

] [ 𝑍 0

] [ 0𝑌

]

[ 0𝑌

] [ + 𝑍 𝑌𝑃 𝑍

𝑌𝑃(2 + 𝑍 𝑌𝑃) + 𝑍 𝑌𝑃] [

0𝑌

]

[ + 𝑍 𝑌𝑃 + 𝑍 𝑌 𝑍

𝑌 ( + 𝑍 𝑌𝑃 + 𝑍 𝑌 )+𝑌𝑃(2 + 𝑍 𝑌𝑃) + 𝑌 ( + 𝑍 𝑌𝑃) + 𝑍 𝑌𝑃 + 𝑍 𝑌 ](3.9)

Where,

𝑍 𝑠 𝐿 (3.10a)

𝑌𝑃 (𝑠 𝑃 +

𝐿𝑃) (3.10b)

𝑌 𝐶 ( + 𝑅 𝐶 )

( + 𝑅 𝐶 ) (3.10c)

s jω (3.10d)

The derivation results are

A + 𝑍 𝑌𝑃 + 𝑍 𝑌 (3.11a)

B 𝑍 (3.11b)

C 𝑌 ( + 𝑍 𝑌𝑃 + 𝑍 𝑌 )+𝑌𝑃(2 + 𝑍 𝑌𝑃) + 𝑌 ( + 𝑍 𝑌𝑃) (3.11c)

D + 𝑍 𝑌𝑃 + 𝑍 𝑌 (3.11d)

According to the ABCD matrix, one can calculate the S11 and S21 values [3.22] as

𝑆 𝐴+𝐵 𝑍0

⁄ 𝐶𝑍0 𝐷

𝐴+𝐵 𝑍0⁄ +𝐶𝑍0+𝐷

(3.12a)

and

𝑆

𝐴+𝐵 𝑍0⁄ +𝐶𝑍0+𝐷

(3.12b)

Therefore, by substituting Eqn. (3.11a) to (3.11d) into Eqn. (3.12a) and (3.12b), we

can obtain S11 and S21 as the following.

81

𝑆 𝐵𝑍0⁄ 𝐶𝑍0

𝐴+𝐵 𝑍0⁄ +𝐶𝑍0

𝑍𝑆

𝑍0⁄ 𝑍0( 𝑌 + 𝑍𝑆𝑌𝑃𝑌 + 𝑌𝑃+𝑍𝑆𝑌

+𝑍𝑆𝑌𝑃 )

+𝑍𝑆𝑌𝑃+𝑍𝑆𝑌 +𝑍𝑆

𝑍0⁄ +𝑍0( 𝑌 + 𝑍𝑆𝑌𝑃𝑌 + 𝑌𝑃+𝑍𝑆𝑌

+𝑍𝑆𝑌𝑃 )

(3.13a)

𝑆

𝐴+𝐵 𝑍0⁄ +𝐶𝑍0

+𝑍𝑆𝑌𝑃+𝑍𝑆𝑌 +𝑍𝑆

𝑍0⁄ +𝑍0( 𝑌 + 𝑍𝑆𝑌𝑃𝑌 + 𝑌𝑃+𝑍𝑆𝑌

+𝑍𝑆𝑌𝑃 )

(3.13b)

The insertion-loss is usually defined as S21 value in decibel.

IL 20log|𝑆 | (3.14)

The S11 and S21 of a TL bandpass filter can be expressed as (3.10c), (3.13a) and

(3.13b), where Rsub and 1/jωCsub are the impedance associated with the silicon substrate

conductivity, represents the equivalent impedance of the intrinsic part of the TL bandpass

filter, in which the parasitics resulting from capacitive and resistive effects (Cox, Csub, and

Rsub) are included and the substrate capacitance increase with the substrate. Removal of the

silicon underneath the TL bandpass filter will lead to the increase of Rsub and the decrease

of Csub. Obviously, from (3.13a)–(3.13b), at low frequencies, S-parameter is expected to

roughly keep the same value since it is nearly independent of the values of Rsub and Csub,

whereas at medium-to-high frequencies, S-parameter is expected to change because of the

increase of S11 and the decrease of S21. Notice that Ysub is one factor that dominates the S11

and S21 values (due to the increase of Rsub and the decrease of Csub).

According to the center frequency expression (3.15), the resonant frequency of the

bandpass filter is shifted to a higher frequency, since the silicon substrate is removed and

the capacitance is decreased.

𝜔 𝑖 𝑟

√𝐿𝐶 (3.15)

82

in which,

𝑖 𝑟 + (3.16)

Apart from the above effects on S11 and S21, the frequency with the maximum

Q-factor (fmax) is expected to shift to a higher value just as the ICP inductor reported in the

previous work [2.2].

As mentioned in section 3.5 where a low-insertion-loss V-band CMOS bandpass

filter is proposed, the low-frequency transmission-zero (ωz1) and the high-frequency

transmission-zero (ωz2) of the filter can be tuned individually by adjusting the value of the

series capacitor (Cs) and the size of the built-in LC resonator, respectively. Nice results

from this work demonstrate the potential of using the proposed filter architecture in

conjunction with the developed backside ICP deep trench technology in the implementation

of V-band (or even higher frequency-band) high-performance and low-cost CMOS filter.

The measured S21 with ICP technology removed silicon substrate verifies the validity of our

proposed TL theory, gains improvement.

A CMOS-compatible backside ICP deep-trench technology has been developed to

enhance the performance of TL passive filters for 2–110-GHz microwave applications.

Significant improvements in both Q-factor and insert loss were achieved for a set of TL

passive filters after the ICP etching.

83


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89

Chapter 4

A Controlled-release Drug Delivery System

on a Chip Using Electrolysis

4.1Introduction

Biomedical electronics that combine the biological and electronic knowledge have

made appreciable technological progress in recent years [4.1-4.3]. For instance, implantable

devices for bionic systems based on microchip technologies, such as cochlear [4.4] and

retina [4.5] implants, have shown remarkable advances in size reductions and system

integrity, enabling potential sensation recovery in patients. Furthermore, the use of

bio-electronics in neurology and biochemical analysis [4.6-8] is believed to make possible

changes in diagnostic and therapeutic behaviors in the next generation. Although the

combination of medical devices and electronics has experienced significant breakthroughs,

its potential for drug delivery applications remains unrealized.

In this chapter, a system on chip (SOC) for drug release in which the drug reservoirs

and active circuits are integrated on a single chip is demonstrated. Through wireless

commands, the quantity and timing of the drug release can be precisely controlled. This

technology appears to have broad application in both the pharmacology and environmental

industries.

Historically, drugs were delivered by pills, ointments, eye drops, and injections, all

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essentially descendants of ancient practices [4.9]. In 1964, Folkman first demonstrated that

silicone rubber can be used as a drug carrier for low molecular weight compounds in

animal tissues [4.10]. This concept was developed by Langer [4.11], who succeeded in

using polymers capable of carrying various kinds of macromolecules, such as proteins,

polysaccharides, and polynucleotides, as drug carriers. As a result, more complex agents,

such as chimeric antibodies and gene-based drugs, can be delivered to the human body.

Today, the synthesis and use of polymers has become the dominant approach in drug

delivery research. The degradability and biocompatibility of different kinds of polymers are

also investigated because of their versatility [4.12].

Generally, drugs contained in the carriers may be released by diffusion or package

erosion in the digestive system. These kinds of systems possess a stable release rate, but the

release rate is limited and requires additional chemicals, such as enzymes, for release rate

enhancement [4.13]. Another drug release approach is a stimuli-released drug delivery

system. Instead of diffusion or erosion, this kind of release scheme is triggered by specific

stimuli including electric fields [4.14-15], magnetic fields [4.16], enzymes [4.17-18], PH

value [4.19], and temperature change [4.20]. Because stimuli controlled drug release does

not depend on the dissolving procedure of the package, drugs can be preserved before the

stimulus occurs, enabling more efficient absorption. Stimuli controlled release is important

especially for drugs made of protein, since the effectiveness of protein-based drugs can be

seriously reduced by the proteases existing in the human digestive system. Stimuli

controlled drug release prevents proteins from being released too early in the digestive

process, maintaining their efficiency. Although taking drugs through the digestive process

may seem less efficient than obtaining them via injection, it is impractical to ask patients to

receive shots repeatedly or visit a clinic every day.

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To resolve the above issues, an alternative treatment method, implanting a drug release

system in the targeted area on a human body and triggering the drug carrier to release on

demand, has drawn significant attention. The idea of a released-on-demand drug delivery

silicon chip was first proposed by Santini Jr. in MIT [4.21], who filled the drug into a

silicon reservoir array and sealed the reservoirs with a capping membrane made of gold.

When the appropriate voltage value is applied to the membrane, the membrane begins to

dissolve and finally opens to release the contents. This idea was developed further by Smith

[4.22], who connected the drug reservoir array with integrated circuits including a system

control component and a wireless power circuit. Through these active circuits, the

reservoirs may be opened by wireless command, enabling the number of reservoirs opened

to be precisely controlled. Unfortunately, the integration level of this idea is restricted by

the incompatibility between the process for manufacturing the reservoirs and the CMOS IC

manufacturing technology, which results in a requirement for on-board connections and a

large volume. To achieve higher levels of integration, it is necessary to fabricate the drug

reservoirs directly on the chip with the integrated circuits. This goal is achievable with

CMOS-compatible deep trench technology and is demonstrated in this chapter.

In addition to the electrochemical approach, the electrothermal approach may also be

used as the opening force for the membrane [4.23]. In our previous work [4.24], the

capping metal of the reservoirs is removed electrothermally. However In this chapter, cap

removal is not performed by joule heating but by the gas pressure of microbubbles that are

generated electrolytically. The proposed reservoir structure does not use an alloy as its

capping membrane but instead uses the passivation layer already present as a result of the

standard CMOS process, which simplifies the post-IC processing procedure. Furthermore,

because no joule heating is required, the current applied to the reservoirs may also be

92

reduced.

4.2 System Architecture

The architecture of the proposed drug delivery SOC is illustrated in Fig. 4.1. An

RS-232 formatted data stream is modulated by OOK and launched by a transmitter outside

the body. After the OOK receiver detects this wireless signal, it begins to demodulate it

using an envelope detector. Demodulation by envelope detection requires no frequency

translation, which profoundly simplifies the system architecture and reduces the power

consumption. The demodulated signal is further sent to a micro-control unit (MCU) for

decoding. The decoded information contains the address of the reservoir to be opened, so

that the MCU can direct current into the electrodes of the appointed reservoir. When the

current enters them, the electrodes begin to generate micro-bubbles in the solution, which

accumulate inside the sealed reservoir until the capping membrane is broken by the gas

pressure. Additional circuit components, including a power-on-reset, regulator, and clock

generator, are incorporated for system robustness. The power-on-reset resets the voltages of

the registers of the MCU at the system start-up before the residual voltages result in

incorrect system behaviors. The regulator generates a stable supply voltage for the receiver,

while the clock generator is used to provide two different clocks for the MCU.

The proposed drug delivery system in package is illustrated in Fig. 4.2, with the inset

showing a cross-section view of the reservoir array. A passivation layer formed by stand

CMOS process is used as the membrane capping for the reservoirs. It is opened by the

electrolysis approach described above. The drug delivery chip is mounted on a board. The

board is further stacked on an Li-ion nanowire battery [4.25]-[4.26], which possesses high

93

density charge storage and is rechargeable. A planar inductor on the bottom of the package

is used to receive the command signal and the wireless power from a transmitter outside the

body [4.27]-[4.28]. The received power can be stored in the Li-ion battery, for a longer

device lifetime. The drug delivery device is expected to be implanted subcutaneously, due

to the signal attenuation in the human body and the limited size of the coupling inductor.

Fig. 4.1: Architecture of SOC for drug delivery

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4.3 On-Chip Electrolysis

The releasing mechanism of the proposed system is based on electrolysis, which

creates micro-bubbles of oxygen and hydrogen by directing electric currents into water

[4.29]-[4.30]. The generated bubbles are then used as the force that opens the sealed

reservoirs. The reaction of electrolysis may be expressed by the chemical reaction formulas

given in Eqs. (4.1)-(4.2) [4.31].

Anode: 2 + + + ( ) (4.1)

Cathode: 2 + 2 2 + ( ) (4.2)

To realize this reaction, the electrodes have to be exposed and inserted into the

solution. Therefore, on-chip electrodes immersed in a solution are implemented inside the

drug reservoirs. The procedure of reservoir opening is shown in Fig. 4.3. In Fig. 4.3(a) the

drug is filled into a tank that is shaped by the post-IC processing. On the walls of this tank,

layers from metal 1 to metal 4 are stacked and connected by vias to form the vertical

electrodes for electrolysis. In Fig. 4.3(b), by injecting currents into the electrodes,

micro-bubbles are generated from the electrode surfaces. The gas pressure accumulates

against the capping membrane until it exceeds the affordable stress of the membrane (~95

KPa) and the membrane begins to rupture. Once the membrane ruptures, the drug will be

released. Note that a slight difference in PH value may occur in the local area due to the

generated gas. However, this phenomenon is only temporary since the human body is a

large natural buffer in which a tiny imbalance may be easily neutralized. It is known that air

bubbles of less than 30 uL dissolve harmlessly into the circulation [4.32]. Even a larger

95

volume of air bubbles will be trapped by the lungs unless there is a shunting into the heart.

The lethal volume of air in an adult human is estimated to range from 200 to 300 mL [4.33].

Since the volume of the micro-bubbles generated by our device, ~120 nL, is much smaller

than 30 uL, the released bubbles will not cause a health risk to the patient.

4.4 Drug Reservoir Design and Fabrication

The drug delivery SOC is fabricated by standard 0.35 um CMOS process followed by

post-IC processing. After receiving the standard chips from the foundry, post-IC

micromachining is applied to etch the structure of the reservoir. Processing can be divided

to two basic steps, reservoir etching and drug filling. The post-IC processing steps are

shown in detail in Fig. 4.4. First, the standard chip is thinned by mechanical lapping (Fig.

4.4(a)-(b)) to reduce the substrate thickness of the chip. After the substrate thickness is

thinned to 100 um, photolithography is performed on the back-side of the chip to define the

positions and sizes of the reservoirs (Fig. 4.4(c)). After hard baking the photoresist as the

etching blocking layer, the unblocked area is trenched by inductively-coupled ion-enhanced

plasma etching (ICP etching) (Fig. 4.4(d)). With its high aspect-ratio etching ability, ICP

etching is capable of drilling holes for the reservoirs with the desired sizes and sharp

sidewalls. Once the unwanted silicon in the reservoir is etched off, another omnidirectional

wet-etching, the silox vapox wet-etching, is performed to remove the silicon dioxide filled

between the electrodes (Fig. 4.4(e)).

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Fig. 4.2: Proposed drug delivery system in package

(a) (b)

Fig. 4.3: Opening of the integrated reservoir: (a) microbubbles generated on the surface of

electrodes by electrolysis, (b) membrane ruptured by gas pressure.

97

Because of the omindirectional characteristics of the wet-etching, electrodes formed

by the stacked M1-M4 and vias can be exposed for electrolysis. The above steps are

processed on the backside of the chip. After backside processing, post-IC processing is

continued on the front side by chip flipping. Passivation etching is then carried out to create

a thinner capping layer by reactive-ion enhanced etching (RIE). In this way, the thickness

of the passivation can be reduced to nearly 200 nm (Fig. 4.4(f)) in order to decrease the

stiffness of the membrane. After this step, the reservoir complete with a membrane and

electrodes is formed and ready for drug filling.

The dimensions of each reservoir are 210um in length and 110um in width. In order to

increase the reservoirs’ volume capacity, a PDMS layer, fabricated by the soft-lithography

process, is bonded to the die (Fig. 4.4(g)) on the backside of the chip. After PDMS bonding,

the reservoirs are filled with the desired drug by an automatic dispenser (Fig. 4.4(h)) and

finally sealed by another PDMS film (Fig. 4.4(i)). Even though the volume of the reservoir

is limited by its front-side area and the thinned silicon substrate (Fig. 4.4(f)), it can be

increased by widening and thickening the PDMS reservoir bonding layer (Fig. 4.4(g)). A

die photo of the drug delivery SOC is shown in Fig. 4.5 (a), where a total of 8 reservoirs

may be found with a total die size of 1.77mm×1.4mm. The dose of the drug may be

adjusted by controlling the number of opened reservoirs. The reservoirs are designed to be

opened one at a time according to the received command.

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Fig. 4.4: Post-IC processing steps

99

4.5. SUB-Blocks

The sub-block includes OOK, an MCU, power on reset circuit and regulator. The

structures about sub-block circuits could refer to [4.24] have more detail description.

4.6 Experiment Results

The front-side and backside chip photos of the bare die after reservoir etching are

shown in Fig. 4.5. On the front-side, the sub-circuits, drug reservoirs and test keys of

reservoirs can be seen. On the back side, reservoirs with front-side patterns may be clearly

observed due to the transparency of the silicon dioxide and the passivation layer.

(a)

100

(b)

Fig. 4.5: Die photos:(a) front-side (b) back-side

The final result of the drug delivery SOC is shown in Fig. 4.6. As mentioned earlier,

the silicon chip is bonded with a PDMS reservoir layer to increase the capacity of the drug

reservoirs from 5 nL to 200 nL. Another PDMS film is used to seal the bottom of the

reservoir after the PDMS reservoir layer is bonded. The total thickness of the drug delivery

SOC is 0.7 mm, including the silicon chip and PDMS substrate.

Fig. 4.6: Drug delivery SOC.

101

To characterize the sensitivity of this system to the wireless signal, a bit-error-rate-test

(BERT) is performed on the on-board OOK receiver. The tested pattern is a 216

-1

Pseudo-random-binary-sequence (PRBS) at 5Kbps, modulated by the OOK modulation

facility of a vector signal generator (VSG), an Agilent E4438C. The OOK modulated signal

is sent to the OOK receiver through bonding wires and demodulated by the OOK receiver.

The demodulated signal is then fed back to the VSG and compared with the original test

pattern for error detection. As a result, we can vary the carrier signal power and know the

sensibility of this receiver. The minimum detectable signal power with a reasonable BERT

result (bit error rate < 10-3

) is recorded and shown in Fig. 4.7. It shows that at 403 MHz, the

sensitivity of this receiver is -61dBm, which is satisfactory for short-distance applications.

This system consumes 7.57 mW in total, 7.2 mW by the receiver and 0.37 mW by the other

circuits including the MCU, power-on-reset, clock generator and regulator.

The in vitro measurement is performed by the setup shown in Fig. 4.8. The drug

delivery SOC with fluorescent dye sealed inside is wire-boned to a PCB and immersed in a

dish of deionized water. A fluorescence microscope is used to detect the fluorescent dye

(Rhodamine B) diffusing out from the reservoirs after the membrane ruptures. In addition,

based on the contrast of the observed image, we can calculate the normalized concentration

of the drug.

102

Fig. 4.7: Measured sensitivity of the OOK receiver.

Fig. 4.8: In-Vitro measurement setup.

The results of the drug release experiment are shown in Fig. 4.9. At the drug release

activation, a DC voltage of 3V is applied to the electrodes, which then conduct a 2mA

current into the solution. After activation, micro-bubbles occur and diffuse from the rupture

of the membrane. The normalized concentration versus reaction time shown in Fig. 4.10

reveals a quick response in the drug release. Only 1.5 seconds are needed to open the

reservoir after the opening command is given. After a sudden increase, the concentration

decreases with time because of the dilution in the water.

103

(a) (b)

Fig. 4.9: Measured drug release results: (a) before electrolysis (b) after electrolysis

Fig. 4.10: In vitro measurement results of the concentration of the fluorescent dye versus

time after an opening command is given.

For implantable applications, power consumption is a critical issue. A comparison of

the maximum instant power (PMAX) and energy dissipation (E) required by different

techniques to open a single reservoir is given in Table 4.1.

104

Table 4.1: Power and energy in different activation techniques

Activation Technique PMAX E

Electrochemical [4.22] 90μW 300μJ

Electrothermal [4.23] 2.5W 25μJ

*Electrothermal [4.24] 67.5mW 6.75mJ

*Electrolysis (This work) 6mW 9mJ

*: system-on-a-chip

4.7 Practical Issues

The proposed system confronts several practical issues. The first issue is the lifetime

of the device. Using the aforementioned Li-ion nanowire battery with an assumed energy

density of 7 mAh/mm3, a button cell 4.5 mm in diameter and 2 mm in height (a volume of

~32 mm3) can provide a total energy of ~ 403 mWhr, enabling the device to power the drug

device tracking signal for 53 hours. Continuous powering of the receiver appears to be an

inefficient power strategy, since the drug delivery timing is usually regular. Instead, turning

on the receiver periodically through the MCU is a better approach (turning on the receiver

for one microsecond every half second), one that is commonly seen and should be adopted

in real-world applications.

Biocompatibility of a drug is a vital requirement [4.34], since it prevents the implant

from inducing inflammatory responses or immune system reactions. The surfaces of the

proposed device include silicon and silicon nitride, which are biocompatible [4.35]. As for

the packaging material, Titanium (Ti) is suitable, since it is known to be a good

biocompatible material and is already in use in industry. Moreover, the heat generated by

105

the bio-implant is expected to be dissipated uniformly because of the high thermal

conductivity of the metallic packaging. The surface area of the drug device is estimated to

be ~88 mm2. As a result, the heat flux generated by the drug device is ~0.09 mW/mm

2,

which causes a temperature increase of less than 1°C [4.36].

This study represents a proof of concept. Using electrolysis as an opening force has a

number of important limitations, including the liquid forms of the drug and the chemicals

produced in this approach. These issues mainly results from the mixture of the drug and

water during electrolysis. A practical way to improve the system would be to fabricate

another chamber on top of the device and form a two-chamber device, so that the drug and

water can be separated in different chambers during electrolysis. Such two-chamber designs

have been implemented in regular medical devices [4.37]. In addition to the limitations of

chemical reactions, the direct contact between the device surface and human tissue may

cause the extra pressure required to burst the cavity within the body. Therefore, an

additional PDMS layer on top of this device will be needed to form a gap between the

membrane and nearby tissue. Other concerns, such as blood pressure, the pressure of

interstitial fluid, effects of biofouling and immune/inflammatory response, should be also

considered in the design of the device structure for practical use.

106


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111

Chapter 5

Conclusions

This dissertation has proposed the new MEMS application using Deep Trench

Technology and applied to microwave passive devices such as filters and biomedical device,

including active circuits. To further exam the compatibility of the proposed technique,

active circuits such as LNA and microwave passive filter were also given the same process.

All these components mentioned above were fabricated using standard CMOS processes.

No modification during the foundry processing is enforced, which we regard as a truly

CMOS compatible technology compared with the former arts. It is especially appropriate

for use in designing compact passive circuits using microwave CPW and MSL.

Comparisons between performances of the passive devices before and after trenching

were given to quantify the effectiveness of the proposed technique in substrate loss

reduction. It was found that the analytical models based on quasi-TEM approximation can

be used for the design of CMOS passive coplanar devices in the E-frequency band. As a

result, a low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed

filter architecture has the following features: the low-frequency transmission-zero (ωz1) and

the high-frequency transmission-zero (ωz2) that can be tuned by adjusting the value of the

series capacitor (Cs) and the size of the built-in LC resonator, respectively. The folded

short-stub technique is used to reduce the chip size of the filter. To reduce the silicon

substrate loss, the CMOS-process-compatible backside inductively-coupled-plasma (ICP)

deep trench technology is used to selectively remove the silicon underneath the filter. After

112

the ICP etching, the filter achieves insertion-loss (1/S21) lower than 3 dB over the frequency

range of 46.5~85.5 GHz. The minimum insertion-loss is −1.8 dB at 60 GHz. To our

knowledge, as mentioned above, this is one of the best results ever reported for a V-band

CMOS bandpass filter in this thesis. The ability of substrate removal to improve the

performance of these microwave passive bandpass filters is quantified for the first time.

The effectiveness of which should be more impressive at millimeter frequency range, since

the substrate effects dominate the loss mechanism as the device operates at high frequency

region. MEMS technologies applied to microwave and millimeter-wave applications for

parasitic removal have also shown large performance benefits without increasing the cost.

The second part of this thesis presents a novel, reliability wireless circuits applied in

biomedical device such as drug delivery system. Before this thesis provides new method to

cave drug reservoirs effective integrated control circuit on single chip, Santini et al. [4.21]

and Smith et al. [4.22] connected the off-chip drug reservoir array with integrated circuits

including a system control component and a wireless power circuit, in board level. Both

used wet-etching to cave drug reservoirs, which is the main reason why they could not

effectively shrink the size of their products.

With CMOS-compatible deep trench technology (post-IC processing), we can achieve

higher levels of integration, which is necessary in fabricating the drug reservoirs directly on

the chip with the integrated circuits easy. Also, this Deep Trench Technology anisotropic

dry-etching is a new way to integrate the circuit on a chip to overcome problems of

damaging the device when traditional wet-etching is used. Therefore, this approach

possesses significant advantages of MEMS mentioned above make the system on chip

small to coincide with our main idea which achieved the goal of circuit design.

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In conclusion, the newly developed ICP technology provides a device-scale, CMOS

compatible, low cost, and high-integrated process for biomedical and microwave filters

applications. By taking advantages of this post-IC technology, a variety of microstructures

and biomedical system could be realized in an easy way that is promising to the future of

microwave devices. Moreover, it places value on biomedical electronics with integrating

biomedical device into system-on-chip in popular applications.

graduate institute of electronics engineering college of

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