grid · 2008-04-29 · front-ends in deep sub-micron cmos - front-end ... [more] ... from the...

M a y 2 0 0 8 V i s i t u s a t w w w . e - G R I D . n e t P a g e 1

GRID.pdf

May 2008 CHAPTER MEETINGS

SF-EMB - 4/29 | Graph Theoretical Methods for Network-level Connectivity Analysis of Brain Networks - using MRI ... [more]

SCV-Rel - 4/30 | Reliability Performance and Measures of Repairable Systems - case studies, conclusions, performance ... [more]

SCV-TMC - 5/1 | Risk Analysis as Decision Support - taking pro-active measures, plus directed networking ... [more]

SCV-LEOS - 5/6 | Photovoltaics - Challenges and Opportunities in Materials, Machines and Manufacturing - status, benchmarks [more]

SCV-RAS - 5/7 | Team AnnieWAY's Autonomous System for DARPA Urban Challenge 2007 - driving urban scenarios ... [more]

SCV-SPS - 5/12 | Content-Adaptive Efficient Resource Allocation for Packet-Based Video Transmission - lossy channels, QoS ... [more]

SCV-EMC - 5/13 | Measuring Structural Resonances - useful equipment/methods to aid EMC troubleshooting, with demos ... [more]

OEB-DeVry Student Chap - 5/13 | Academic and Industrial Research: Using the Internet and IEEE's XPLORE Database - search ... [more]

SCV-CPMT - 5/14 | High Performance Modules on Copper Sub-strates - using build-up layers, photolithographic processing ... [more]

SCV-ComSoc - 5/14 | Extending the Concept of Femtocells to the Outdoor Enterprise - architecture, implementation ... [more]

SCV-SSC - 5/15 | An 802.11n 2x2 MIMO Radio in 0.13um CMOS and A Bluetooth v2.1 radio in 0.13um CMOS - design ... [more]

SCV-CAS+MTT+SCC - 5/19 | Highly Integrated Re-configurable RF Front-ends in Deep Sub-micron CMOS - front-end ... [more]

SCV-CNSV - 5/20 | Surveying the Landscape of Established and Emerging Patent Monetization Models - new opportunities ... [more]

SCV-GOLD - 5/20 | Building the Foundation for your Engineering Career - early stage issues, your first layoff, your reputation ... [more]

OEB-PES - 5/21 | 1,000 kW PV Solar System Design-Build Projects - technical aspects for three community colleges ... [more]

OEB-IMS - 5/21 | Advancements in Noise Measurement - noise wave measurement, full mismatch corrected noise figure ... [more]

OEB-ComSoc- 5/22 | 802.11n and Outdoor Mesh Wi-Fi: Market and Standards Update – industrial/municipal applications today ... [more]

SF-GOLD - 5/22 | Financial Advising Seminar for Engineers - your options for confidence, control for your financial goals ... [more]

SCV-Mag - 5/27 | Spintronic Biochips for Biomolecular Recognition - detecting geometries, limits using spin valve, tunnel sensors ... [more]

SCV-PSES - 5/27 | 'Leading Indicators' for More Effective Life Testing - anticipating field failures with only a few units to test ... [more]

SF-IAS - 5/27 | Advances in Power System Protection and Auto-mation – microprocessor technology in protective relaying ... [more]

Professional Skills Courses [more]- Budgeting Essentials - Mastering Your

Presentation Skills - Agile Project Management

Technical Skills Courses/Seminars [more]- Design of RF Integrated Circuits and more

Conference Calendar

May 11-16: Photovoltaic Specialists Conference - San Diego Manchester Grand Hyatt [more]

June 2-4: IEEE Conference on System of Systems Engineering - Portola Plaza Hotel, Monterey [more]

June 5-6: The Industrial Electronics Industry Forum - Santa Clara Marriott [more]

June 8-13: Design Automation Conference (DAC) - Anaheim Convention Center - Register by May 19 [more]

June 16-20: Conf on Sensor, Mesh and Ad Hoc Communications and Networks (SECON 2008) - Crowne Plaza Hotel, Burlingame Deadline: June 1 [more]

June 18-20: ASME Frontiers in Biomedical Devices Conference - Hyatt Regency, Irvine [more]

CALLS FOR PAPERS: Oct. 26-29: Asilomar Conference on Signals, Systems, and Computers – Due June 1 [more]

Aug 25-28: Int'l Conference on Plastic Optical Fibers - Santa Clara - Abstracts due June 1 [more]

UC-Santa Cruz Extension Courses [more]Digital Video Compression - Chip Design Flow from Netlist to GDS-II - Packet Capture and Analysis more

Santa Clara University: Info Sessions [more]Open University summer courses – a chance to try it out

Nanotech: Driver of Electronics, Photonics, Energy, and Bio/Med - 1-day seminar [more]

SCV-SPS - 6/2 | Enhancing Image Fidelity through Spatio-Spectral Design for Image Acquisition, and Display ... [more]

SCV-TMC - 6/5 | The Year of Living Dangerously: Extraordinary Results for an Agile Revolution ... [more]

SCV-Mag - 6/10 | Integrated On-Chip Inductors Using Magnetic Material - CoZrTa alloy up to 9.8 GHz ... [more]

SCV-CPMT - 6/11 | Thermal Stress Modeling in Electronic and Photonic Engineering: Is FEA the Only Tool? ... [more]

SCV-PACE - 6/11 | Congressional Insights & Senior Member Upgrade Information Session - innovation issues ... [more]

http://www.asmeconferences.org/BioMed08


Your Networking Partner

® May 2008 • Volume 55 • Number 5

IEEE-SFBAC ©2008

IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs. IEEE GRID is published as the GRID Online Edition

residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.

Editor: Paul Wesling IEEE GRID PO Box 2110 Cupertino CA 95015-2110 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net

From the Editor’s Desk … Many readers of the GRID are focused on the

technical aspects of their jobs and careers. For those who are IEEE members, I have another aspect of advancing your career – establishing yourself as a Senior Member of the IEEE. So (you ask) is this difficult to do? I assure you that it’s quite simple, for any engineer/developer or other technical professional who has been working for 8 or more years beyond your undergraduate degree!

The steps are pretty straight-forward, and most can be carried out on-line (at www.ieee.org/web/membership/senior-members). You’ll need three other IEEE Senior members or Fellows who can recommend you. Ah, there’s the rub (you say)! But these others don’t need to have a full working knowledge of what you’ve been doing; they only need to review your work (to date) in your assignments and to write a short statement in support of the nomination. This can be done, for example, at the upgrade workshop organized by SCV PACE on June 11 (see meeting information).

Here are some of the advantages of becoming a Senior Member:

Recognition: The professional recognition of your peers for technical and professional excellence.

Senior Member Plaque: All newly elevated Senior Members receive an engraved Senior Member plaque to be proudly displayed for colleagues, clients and employers to see. The plaque, an attractive fine wood with bronze engraving, is sent within six to eight weeks after elevation.

$25 Coupon: IEEE will recognize all newly elevated Senior Members with a coupon worth up to $25. This coupon can be used to join one new IEEE Society. The coupon expires on 31 December of the year in which it is received.

Letter of Commendation: A letter of commendation will be sent to your employer on the achievement of Senior member grade (upon the request of the newly elected Senior Member).

Announcements: Announcement of elevation can be made in Section/Society and/or local newsletters, newspapers and notices.

Do it now! Paul

NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net

DIRECTORS

Santa Clara Valley Ram Sivaraman Tom Coughlin

Oakland East Bay Victor Stepanians Rosanna Lerma

San Francisco Sandra Ellis Dan Sparks

OFFICERS Chair: Victor Stepanians Secretary: Dan Sparks

Treasurer: Ram Sivaraman

IEEE-SFBAC PO Box 2110

Cupertino, CA 95015-2110

IEEE GRID

http://www.ieee.org/web/membership/senior-members/


Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

[email protected]

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835

Do you provide a service? Would you like more inquiries?

• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available

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GRID.pdf

e-GRID

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Professional Services Marketplace – [email protected] for information

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MET Laboratories

EMC – Product Safety

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• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)

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- System Engineering - Test & Measurement - Schematic Capture & PCB layout - Expert Witness

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Fifth Annual IEEE Communications Society

June 16-20, 2008

Crowne Plaza SFO Airport, Burlingame

IEEE SECON provides a forum for the exchange of ideas, techniques, and applications, for discussion of best practices, to raise awareness, and to share experiences among researchers, practitioners, standards developers and policy makers working in sensor, ad hoc, and mesh networks and systems.

Original technical papers are presented on the communications, networking, applications, systems and algorithmic aspects of mesh and sensor networks, as well as on practical deployment and implementation experiences.

Corporate Sponsors:

Co-Sponsor: Santa Clara Valley Section, IEEE

Design of Radio Frequency Integrated Circuits 12 week course, M/W 6:00PM-9:00PM (Starts: May 19) A balance of communications, physics and IC design. Includes high-speed amplifiers, LNA, Mixer, VCO, PA, PLL and other RF blocks.

Design for Testability Fundamentals 12 week course, M/W 6:00PM-9:00PM (Starts July 15) For engineers or managers who want learn basics of DFT techniques and theory: Fault Models, Levels of Abstraction, Test Approaches, Scan Design Rules, Test Generation Methods, BIST, Analog and Mixed Signal Testing, more.

MATLAB & Simulink for Design & Digital Signal Processing 12 week course, T/TH 6:00PM-9:00PM (Starts August 25) Hands-on, from basic concepts in discrete time systems, filter design and implementation all the way to advanced concepts of multi-rate systems; balanced mix of theory and practice.

Discount of $40 for IEEE Members on 12-week courses.

Keynote: “Reuniting Wireless Sensor Networks with the IP Architecture,” David E. Culler, UC-Berkeley

Technical Sessions: (Tues-Thurs, June 17-19) - Localization and Location Management - Routing and Topology Management I & II - Energy Efficient Protocols - Software and Hardware - Medium Access Control - Theoretical Foundations - Transport Layer Issues - Sensor Coverage - Data Fusion and Processing - Time Synchronization and Cooperative Protocols - Vehicular Networks, Emerging Areas and Novel Applications - System Deployment and Experiences - Analytical Models - Security and Privacy - Cross Layer Design

Workshops: (held on Monday, June 16) - Third IEEE Workshop on Wireless Mesh Networks - Third IEEE Workshop on Networking Technologies for

Software Defined Radio (SDR) Networks - First IEEE Int’l Workshop on Wireless Network Coding

Earlybird rates through June 1

For more information and to register:

www.ieee-secon.org Upcoming 1- and 2-day Seminars:

May 2: Global IP Protection through Patents: Processes and Procedures for Engineers and Managers

May 22: Antennas: Principles, Technologies, and Applications

Sept 4: Biomedical Technologies - Opportunities & Challenges

Sept. 5: Device & Interconnect Reliability in Advanced CMOS

Discount of $30 for IEEE Members on Seminars.

Get more information on all upcoming classes:

www.svtii.com/SVTI-calendar.htm

Review all SVTI offerings: www.svti.org

SILICON VALLEY TECHNICAL INSTITUTE

Upcoming Courses with labs

Conference on Sensor, Mesh and Ad Hoc Communications and Networks (SECON 2008)

http://www.ieee-secon.org/

http://www.svtii.com/SVTI-calendar.htm

http://www.svti.org/


MK2 Engineering, Inc. has an excellent opportunity for an experienced electrical engineer to join our growing electrical team. Located in the world-famous Napa Valley, we are a consulting engineers firm specializing in innovative, energy-efficient design of HVAC, plumbing, electrical and fire protection systems.

MK2 is currently searching for a Senior Electrical Engineer to provide leadership for our growing electrical department. This is an outstanding opportunity to work for a stable company that offers a chance to grow with a firm that has continued to expand during the last nine years.

As a Senior Electrical Engineer, you will be expected to effectively coordinate projects, review quality of the design product, design electrical systems and organize staff supporting your efforts. Responsibilities include managing all aspects of electrical design projects including: load calculations, lighting and power system design, short-circuit calculations, system selection, equipment selection, specifications, design, layout, field visits and construction administration. You will be responsible for oversight of profitability and timeliness of production; support of the design and engineering of electrical systems for new installations, system retrofits, system replacement, and system upgrades. As an Electrical Engineer you must have a thorough familiarity and understanding of emergency generators, UPS, fire alarm design, and co-generation systems. Westinghouse is a feature-length documentary about the life and times of George Westinghouse, his companies, legacy, personality and achievements. George Westinghouse is considered America’s greatest industrialist and the only man who would go up against Thomas Edison, and win. His victory over Edison during the Battle of the Currents set the stage for the entire future of electric power. Automobile shock absorbers, railroad signaling and the modern-day weekend all owe their existence to the man who Andrew Carnegie called "A genius who can't be downed." His spirit lived on for decades when his former companies created the golden age of American-made appliances, machines and technologies. Westinghouse Electric dominated the 1939 World’s Fair with Elektro, the talking robot, and the Battle of the Centuries dishwashing contest.

As a department leader you will be in charge of the quality and the quantity of electrical engineering design products. The engineering staff under your charge will provide engineering solutions and project management for our projects in wineries, schools, commercial, institutional and health care facilities.

Technical Qualifications: Minimum 10 years of Electrical Engineering experience with a

US consulting engineering firm(s) BSEE degree from accredited university California PE license required Minimum 3 years of project management and staff supervision Knowledge of California, Title 24 Energy Standards Thorough knowledge of NEC and NFPA LEEP AP or the ability to become accredited Excellent written and verbal communication Proficient in Microsoft Office (Word, Excel…)

How to apply: Send cover letter and resume to [email protected]

In subject line please note “re: Sr.Electrical Engineer” or fax to (707) 307-1550.

For a profile of our company, please visit

www.mk2eng.com

For further information, contact Jason Mueller,

[email protected] Westinghouse was filmed in cooperation with the George Westinghouse Museum and features rare and never before seen footage, industrial films and photos previously buried deep within the Westinghouse archives. Released to stores in early April, you can get a sneak preview on Amazon. More information, and a preview trailer, are available on the web:

www.inecom.com

Position: Senior Electrical Engineer

Walk on the WINE side – come work and play in Napa Valley.

DVD Released for the Film WESTINGHOUSE

mailto:[email protected]?subject=GRID_Inquiry:_Sr_Electrical_Engineer

mailto:[email protected]?subject=GRID_Inquiry:_Sr_Electrical_Engineer

http://www.mk2eng.com/

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A. Communications Systems: 1. Error Control Coding, 2. CDMA, 3. Modulation and Detection, 4. Performance Bounds, 5. Synchronization, 6. Ultra Wideband, 7. OFDM / Multicarrier, 8. Wireless Communications, 9. Optical Communications.

B. MIMO Communications and Signal Processing: 1. Space-Time Coding and Decoding, 2. Channel Estimation and Equalization, 3. Multi-User and Multi-Access Methods, 4. Cooperative Diversity.

C. Networks: 1. Transmission Techniques for Ad Hoc Networks, 2. Wireless Sensor Networks, 3. Network Information Theory, 4. Optical Networks.

D. Adaptive Systems and Processing: 1. Adaptive Filtering, 2. Fast Algorithms for Adaptive Filtering, 3. Frequency -Domain and Subband Adaptive Filtering.

E. Array Processing and Statistical Signal Processing: 1. Array Processing and Beamforming, 2. Sonar and Acoustical Array Processing, 3. Radar Array Processing, 4. Remote Sensing, 5. Signal Separation, 6. Estimation and Detection, 7. Non-Gaussian and Nonlinear Methods, 8. Identification.

F. Biomedical Signal and Image Processing: 1. Medical Image Analysis, 2. Imaging Modalities, 3. Advances in Medical Imaging, 4. Biomedical Signal Processing, 5. Biomedical Applications, 6. Bioinformatics, 7. Image Registration and Multi-modal Imaging, 8. Image Reconstruction, 9. Computer Aided Diagnosis, 10. Functional Imaging, 11. Visualization.

G. Multi-rate and Digital Signal Processing: 1. Filter Design, Theory, and Implementation, 2. Wavelets, 3. Quantization, 4. Sampling, 5. Signal Representations and Spectral Analysis.

H. Architecture and Implementation: 1. Programmable and Reconfigurable Architectures, 2. SOC Architectures, 3. Low-power methods, 4. Compilers and Tools, 5. Integrated Algorithm and Architecture Implementation, 6. Computer Arithmetic, 7. Numerical Processing.

I. Speech, Image and Video Processing: 1. Speech Processing, 2. Speech Coding, 3. Speech Recognition, 4. Narrowband / Wideband Speech and Audio Coding, 5. Document Processing, 6. Models for Signal and Image Processing, 7. Image and Video Coding, 8. Image and Video Segmentation, 9. Image and Video Analysis, 10. Image / Video Security, Retrieval and Watermarking, 11. Image and Video Enhancement / Filtering, 12. Biometrics and Security.

CALL FOR PAPERS 42nd Annual Asilomar Conference on

Signals, Systems, and Computers

Asilomar Hotel and Conference Grounds, Pacific Grove, California October 26 – 29, 2008

www.asilomarssc.org

Authors are invited to submit abstracts before June 1, 2008, in the following areas:

Prospective authors are invited to submit a 50 to 100 word abstract and an extended summary (500 to 1000 words, plus figures). Submissions must include the title of the paper, each author's name and affiliation, and the technical area(s) in which the paper falls with letters(s) and number(s) from the above list. Please visit the conference website (www.asilomarssc.org) for specific information on the electronic submission process. No more than FOUR submissions are allowed per contributor, as author or co-author. All submissions must be received by June 1, 2008. Notifications of acceptance will be mailed by mid August 2008, and author information will be available on the conference website by late August 2008. Full papers will be due shortly after the conference and published in early 2009. All technical questions should be directed to the Technical Program Chair, Dr. Linda DeBrunner, e-mail: [email protected] , or the General Chair, Dr. Michael Schulte, e-mail: [email protected].

CONFERENCE COMMITTEE General Chair: Michael Schulte, University of Wisconsin Technical Program Chair: Linda DeBrunner, Florida State University Conference Coordinator: Monique P. Fargues, Naval Postgraduate School Publication Chair: Michael Matthews, ATK Mission Research Publicity Chair: Murali Tummala, Naval Postgraduate School Finance Chair: Frank Kragh, Naval Postgraduate School

The site for the 2008 Conference is at the Asilomar Conference Grounds, in Pacific Grove, CA. The grounds border the Pacific Ocean and are close to Monterey, Carmel, and the scenic Seventeen Mile Drive in Pebble Beach.

The Conference is organized in cooperation with the Naval Postgraduate School, Monterey, CA, and ATK Mission Research, Monterey, CA. The IEEE Signal Processing Society is a technical co-sponsor of the conference.

http://www.asilomarssc.org/

http://www.asilomarssc.org/




August 25 - 28, 2008 Santa Clara Convention Center - Tutorials - Exhibits - Sessions

The main conference program for POF2008 will be held from Tuesday, August 26th, to Thursday, August 28th, with exhibits open during the conference. Tutorials covering a wide range of POF topics are on Monday, August 25th.

A three-day summer POF workshop the week before offers the US audience a chance to learn from Europe's POF know-how.

Organized by

Have you ever wanted to continue your education in engineering while you continued working? Santa Clara University’s School of Engineering offers graduate degree and non-degree programs to both full-time students and working professionals. Simplified registration for the Summer Open University. Graduate-level instruction. Up to 12 units may be transferred to a graduate-degree program. Early-morning classes: - Linear Algebra - Operating Systems Case Study - Applied Mathematics - Parallel Programming - Logic Design Using HDL (and more)

Evening classes: - Global Technology Development - Hardware Formal Verification - Logic Design Using HDL - IC Fabrication Process - Nanoelectronics (and more)

Saturday classes: - Global Software Management - Next Level Leadership - Advanced Project Management - Law, Technology, IP Email Wan Chen with inquiries: [email protected]

Call for Papers: Abstracts are solicited through June 1, in the following areas:

Technology: * Cables * Connectors * Couplers * Detectors * Environmental Testing * Fiber Bragg Gratings * Hardware * High-Temperature Components * Illumination * Materials * Multimode GI Fibers * Microstructured Fibers * Sensors * Standards * Step index Fibers * Transceivers * Test and Measurements * Tools * WDM Components

Applications: * Aircraft & Aerospace * Automotive * Building Wiring * Consumer Electronics * Data Centers/Servers Farms * Embedded Woven in Fabrics * Home Networks * Industrial Controls * Interconnects * IPTV * Local Area Networks (LAN) * Medical * Military * Sensor Applications * Signs & Illumination * Storage Area Networks (SAN) * Supercomputer Interconnects * Surveillance Systems * Wireless Backbones Submit online at

www.POF2008.com

Save $100 through August 1! Group discounts.

Prepare for that next project or assignment! Register by June 8 Students may continue to register until June 16. Located in the heart of Silicon Valley, with easy parking.

Choice of three Sessions: - Session I - 10-week classes (June 16 - August 22) - Session II - 5-week classes (June 16 - July 18) - Session III - 5-week classes (July 28 - August 29) … plus a number of one-day Saturday classes

To learn more, attend a Wednesday early-evening information session on May 7 or June 4: Visit

www.scu.edu/engineering/graduate/event_rsvps.cfm Review summer Open University courses:

www.scu.edu/engineering/graduate

Santa Clara University School of Engineering Graduate Programs

SCU Summer Open University

17th International Conference on Plastic Optical Fibers

http://www.POF2008.com/

http://www.scu.edu/engineering/graduate/event_rsvps.cfm

http://www.scu.edu/engineering/graduate/courses_registration/summerschedule2.cfm


Packet Capture and Analysis May 1 - May 29, Thu 6:30 to 9:30PM, Sunnyvale Campus Analyzing node statistics, testing methods, analyzing protocols for specific conversations, verifying data-link and network-layer interactions, understanding alarm features Earlybird rate through April 2nd – save 10%

Optical Networks Essentials Jul 09-Aug 20, Wed 6:30PM - 9:30PM, Cupertino Campus Earlybird rate through June 25 – save 10%

Engineering & Technology certificate programs: Database and Internet Programming Embedded Systems Enterprise Java Programming Linux/Unix Programming & Administration Network and System Security Software Engineering and Quality VLSI Engineering Our courses are organized under Certificate Programs. Within a program you will find courses from the basic (for career changers) to the cutting-edge (to help you stay at the fore-front of the profession).

The IES Industry Forum

5-6 June 2008 Marriott Hotel, Santa Clara

Industrial and embedded technologies are expanding in industry settings, and in other markets such as robots in the home, sensors in the car, etc. The Internet has allowed devices to advance from isolated objects to being remotely controlled. This combination makes exciting discussions among computing, communications and industrial technologies experts. This Forum focuses on elements to build and use Industry Systems, the business directions for industry technologies, security requirements, and industry research.

Session 1: Trusting Industry Computing Led by a keynote from Victoria Stavridou-Coleman, Samsung Computer Science Laboratory VP, this session looks at the security and reliability requirements for Industry Computing. Speakers: Jean-Pierre Seifert, Samsung; Michael Condry, Intel. A look at three outcomes: must have it, it’s a pain but maybe needed, and finally forget it – it’s nonsense.

Session 2: Building for Industry Computing Doug Davis, Intel VP for Embedded and Communications, sets the direction for industrial and embedded technologies building blocks. Speakers: Pranav Mehta, Intel; Jeff Meisel, National Instruments; Kim Hartman,TenAsys. Speakers present different product aspects of computing, communications, and systems.

Evening Reception: networking with colleagues, speakers.

UPCOMING CLASSES FOR ENGINEERS – IN SUNNYVALE,

CUPERTINO Intrusion Detection May 10-Jun 14, Sat 9:00AM to 4:00PM, Sunnyvale Campus

AJAX, Intermediate May 20-Jul 01, Tue 6:00PM to 9:00PM, Sunnyvale Campus Earlybird rate through May 6 – save 10%

Digital Video Codec Design Jun 25-Jul 23, Wed 6:00PM to 9:00PM, Cupertino Campus Earlybird rate through June 11th – save 10%

Configuring Linux Firewalls Jul 17-Aug 14, Thu 6:30PM to 9:30PM, Sunnyvale Campus Earlybird rate through July 3rd – save 10%

Plus many other courses – see the website “Real-time" courses, and "real-world" instructors

– Take one course or a whole certificate.

Find out more:

www.ucsc-extension.edu/EngTech

Session 3: Use and Markets for Industry Computing A keynote panel with partners from Morgenthaler Investments and Core Capital, and using market analysis, reviews the directions of financial investments in the industry computing area. Speakers include market experts from iSuppi; Victor Huang from Skipper Wireless; and Pat Fasang from Altera. See how products and technologies will evolve with these market and financial directives.

Session 4: Research for Industry Computing A keynote from Hubert Wo, COO/GM of ARRIS Technology, who has many years experience with research and industry environments. Then many industry research directives are examined, including from IES research leaders. The sessions are organized as a single plenary track to promote discussions in the fields addressed.

IEEE members: $120; Non-members: $150 (thru May 22)

For more, visit www.iesforum.com

http://www.ucsc-extension.edu/EngTech

http://www.iesforum.com/


The Photovoltaic Specialists Conference presents groundbreaking research papers on all aspects of PV-relevant materials, devices, systems and applications. We once again have a very strong Technical Program that will encompass seven programmatic areas covering topics from novel materials and devices, thin-film cells made from CIGS and CdTe and emerging semiconductors, crystalline and amorphous silicon, III-V cells, concentrator devices and systems, and module and system experience including reliability studies.

Tutorials: ● Nanostructures in Photovoltaics ● Silicon Solar Cell Technology ● Polycrystalline Thin Film Solar Cells ● High-Concentration Photovoltaics: Cells, Optics, and Systems ● Productive Buildings - the integration of architecture and solar electric systems ● Materials, Defects, and Characterization Methods for Photovoltaics

Exhibits: visit GT Solar, EMCORE, Spectrolab, Trina Solar, SunPower, HelioVolt, Despatch, Motech, SDG&E and many others

IEEE Professional Skills Courses

Budgeting Essentials – Date/Time: Fri, May 9, 8:30AM – 12:30PM – Location: – Cypress Semiconductor, San Jose

Fee: $300 for IEEE Members; $350 non-members

Transitioning from Individual Contributor to Manager

– Date/Time: Thurs, May 13, 8:30AM – 4:30PM – Location: – TIBCO Software, Palo Alto


Mastering Your Presentation Skills – Date/Time: W/Th, May 21-22, 9:00AM – 5:00PM – Location: – TIBCO Software, Palo Alto


Influential Communication – Date/Time: Tues, June 10, 8:30AM – 4:30PM – Location: – TIBCO Software, Palo Alto


Improve your skills – register for one of these classes, or for others coming up this spring. Bring a team!

Sessions: (partial listing) ● Space Photovoltaic Devices ● Materials and Theory ● TCOs and Contacts ● Inorganic Nanostructures ● III-V Cells and Characterization ● Silicon Solar Cells ● CPV Technology ● Concentrator Technology ● CdTe and CIGS Deposition ● Contacts and Novel Concepts ● Innovations in PV ● Modules and Manufacturing ● Optical Enhancement in Amorphous and Thin Film Si ● Standards and Codes ● PV Modules ● Devices and Defects

Earlybird discount through April 11th.

More information and registration:

www.33pvsc.org

For more information on booths and sponsorships, contact Jamie Price, [email protected] SCV Chapters, Engineering Management & Components, Packaging and Manufacturing Technology Societies

NEW! Agile Project Management – Date/Time: Tues, June 17, 8:30AM – 4:30PM – Location: – TIBCO Software, Palo Alto


This workshop teaches the fundamentals of agile project management, and is recommended for everyone who will be involved in an agile software project. We will explore the key roles, responsibilities, interactions, and processes that make a successful agile project happen. The workshop focuses on practical 'how to' skill development, while providing enough theory so that participants will understand why the techniques work. See also the June 5th TMC meeting LINK

For complete course information, schedule, and registration form, see our website:

www.EffectiveTraining.com

33rd IEEE Photovoltaic Specialists Conference Manchester Grand Hyatt Hotel, San Diego May 11–16, 2008

http://www.33pvsc.org/


http://www.effectivetraining.com/calendar.php?loc=local


DAC is the premier event for the electronic design community. It offers the industry’s most prestigious technical conference in combination with the biggest exhibition, and brings together design, design automation and manufacturing market influencers. Industry leaders, market leaders, technical leaders, business leaders and thought leaders all converge at DAC. The DAC technical program is made up of 14 tutorials, 7 workshops, 8 topical panels, a slate of Pavilion panels and 36 technical sessions divided into 12 Topical Areas, plus keynotes and exhibits. Management Day: (all-day Tuesday) Providing managers with timely information to help make decisions where business and technology intersect. The day is comprised of three sessions featuring presentations by managers representing key independent device manufacturers (IDMs) and major fabless companies. Keynote Speakers: EDA for Digital, Programmable, Multi-Radios Justin R. Rattner, Chief Technology Officer, Intel Corp. Challenges on Design Complexities for Advanced Wireless Silicon Systems Sanjay K. Jha, President, Qualcomm CDMA Technologies Idea to Implementation: A Different Perspective on System Design Jack Little, President, The Mathworks Colocated Events:

June 5-7: IEEE/ACM Conference on Formal Methods and Models for Codesign (MEMOCODE 2008)

June 8-9: IEEE Symposium on Application Specific Processors (SASP 2008)

June 8-9: IEEE Symposium on Application-Specific Processors

June 9: IEEE Int’l Workshop on Hardware-Oriented Security and Trust (HOST-2008)

June 12-13: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH ’08)

Sponsors Special Topical Areas: • Synthesis and FPGAs • Interconnect and Reliability • DFM & the Mfg Interface • Analog/RF/Mixed Signal & Simulation • Verification & Test • Physical Design • Low-Power Design • New/Emerging Technologies • Wireless • Strictly Design • System-level and Embedded • Business 45th DAC Workshops (Sunday and Monday) • High-level Synthesis: Back to the Future • UML for SoC Design Workshop • Biochips to Interface and Monitor Human Biological Functions • System and SoC Debug Workshop • Design and Verification of Low Power SoCs: An Application Oriented Approach • Low Power Coalition Workshop - Advances in Low Power Design for Circuits and Systems • Cross-layer Power and Thermal Management • Diagnostic Services in Network-on-Chips (DSNOC) • Introduction to Chips and EDA for a Non-technical Audience • Women in Design Automation: Achieving Career Balance in an Unbalanced World • OpenAccess: A Platform for Continuous Evolution and Innovation • Integrated Design Systems Workshop • Diagnostic Services in Network-on-Chips (DSNOC) • Beyond Syntax and Semantics: Industry Experiences with OVL/SVA/PSL Tutorials: Bridging a Verification Gap: C++ to RTL for Practical Design • Programming Massively Parallel Processors: the NVIDIA Experience • Robust Analog/Mixed-signal Design • DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction • Low Power Techniques for SoC Design • System Level Design for Embedded Systems

Plus 6 Hands-on Tutorials with the theme “Embedding intellectual property in your design: challenges & solutions” Advance Registration rates through May 19

Substantial discount for IEEE and ACM members, students

Access the Advance Program on the website:

www.DAC.com

45th Design Automation ConferenceAnaheim Convention Center June 8-13, 2008

Technical Theme: Wireless Design & Applications

http://www.DAC.com/


June 2-4, 2008 Portola Plaza Hotel and Spa

at Monterey Bay

Conference Theme: SoSE in service of Energy and Security

SoSE 2008 provides a world-class forum for all aspects of systems engineering, human-machine systems and emerging cybernetics, with their vast ramifications in numerous engineering fields such as control, computing, communications, information technology and applications to manufacturing, defense, national and homeland security, aerospace, aeronautics, energy, and the environment.

2008 Workshop: International Consortium on

System of Systems (ICSOS) June 5, 2008

Workshop Theme: SoS and SoSE in service of Security, Energy and Environment

www.icsos.org/2008workshop

Tuesday May 20, 2008

7:30 AM - 5:00 PM

National Semiconductor, Santa Clara Keynote: Dr. Paolo Gargini, Director of Technology Strategy, Intel

Lunch Speaker: "Nano-Photonic Silicon Circuits as a Commercial Technology," Professor Eli Yablonovitch, Department of EE & CS, UC-Berkeley

Panel Session: "Nanotechnology: Show Me the Money" Early Registration (by May 12) IEEE Members $80, Non-Members $95, Students $40.

Add $15 after May 12

Keynote Talks: - Challenges in Undersea Warfare Systems of Systems - Systems Engineering & Management of System Families - System of Rovers and their Application - OMG Systems Modeling Language - Global Earth Observation System of Systems – Is the

Palnet Earth ready for the Next Tsunomi? - Extending B-787 E-Enabling SoS to Other Means of

Transportation - IEEE-INCOSE Relations on SoSE

Sessions: Over 100 short presentations

Plus exhibits

For additional information:

www.ieeesose2008.org

Sponsored by the IEEE Systems, Man, and Cybernetics Society and the IEEE Systems Council

Point of contact: Mo Jamshidi, [email protected] Sessions: Nanodevice Materials and Processes below 32nm “Lithography Beyond 32nm,” “The Future of Nanoscale Devices,” “Design for Manufacturability for Nanometer Nodes: Challenges and Opportunities” Photonics “Semiconductor Nanowire Based Nanophotonics,” “3D Imaging Using 20nm X-ray Microscopy,” “Carbon Nanotubes for Optoelectronics” Alternative Energy and Storage “Supercapacitors using CNTs,” “Synthesis of Copper Sulfide Nanocrystals for Photovoltaic Applications,” “Vacuum Ultraviolet Tolerance of Nanostructured Polymer/Ceramic Hybrids Coatings for PV Cells” Nano and Bio Sensors “A Carbon Nanotube Enabled Nano ChemiSensor Unit,” “Virotronics: New Bionanotechnology Enabled Solutions” More information and to register:

www.ieee.org/nano

2008 IEEE International Conference on System of Systems Engineering (SoSE)

IEEE San Francisco Bay Area Nanotechnology Council

Nanotech: Driver for Electronics, Photonics, Energy, and Bio-Med

http://www.ieeesose2008.org/


http://www.icsos.org/2008workshop

http://www.ieee.org/nano/


Graph Theoretical Methods for Network-level Connectivity Analysis of Brain Networks

Speaker: Dr. Ashish Raj, Department of Radiology,

UCSF Time: Social at 6:00 PM, dinner at 7:00 PM,

presentation at 7:30 PM Cost: $15 for IEEE members, $25 for non-

members, $10 for students Place: Sinbad’s Restaurant, Pier 2 Embarcadero

St., San Francisco RSVP: by April 25th to Bob Giebeler,

[email protected], 415-252-7214 Web: www.e-grid.net/docs/0804-sf-emb.pdf

Dr. Raj earned Bachelors in Electrical Engineering from the University of Auckland, New Zealand, and Ph.D. in Electrical and Computer Engineering from Cornell University. At Cornell he specialized in signal processing and wrote his dissertation on new computational algorithms for MR imaging, working closely with the department of radiology at Weill-Cornell Medical College in New York. This work led to the development of new techniques for reconstructing and processing MR images using prior or redundant information. After graduating in December 2004, he joined the Centre for Imaging of Neurodegenerative Diseases and the Department of Radiology at UCSF, where he is Assistant Professor.

Our presenter, Dr. Ashish Raj will discuss new

advances in brain MRI that provide the ability to non-invasively probe the structural connectivity of the brain. This talk will describe several ways of obtaining the connectivity network of the human brain using MRI data. Networks from MRI structural (MPRAGE) as well as diffusion (DTI, HARDI) data will be described. Additionally, several graph-theoretic methods for analyzing this data will be presented. Preliminary data from Raj’s lab and other examples from recent literature will be presented. Presented evidence indicates the promise of network-level analysis for diagnosis and classification of brain disease states.

TUESDAY April 29SF Engineering in Medicine and Biology


Reliability Performance and Measures of Repairable Systems

Speaker: Dr. Wendai Wang, Applied Materials Time: Refreshments at 6:30 PM, presentation at

7:00 PM Cost: none Place: HP Oak Room, Bldg 48 (Hwy 280 at Wolfe

Rd), Cupertino RSVP: not required Web: www.ewh.ieee.org/r6/scv/rl

Dr. Wendai Wang is a senior member of technical staff of Applied Materials, where he is leading design-for-reliability for new product development. Prior to this position, he was the Reliability Technical Leader at General Electric, where he had successfully led many innovative “design-for-reliability” projects and the GE Reliability Council as well. He received his B.S. and M.S. in electro-mechanical engineering from Shanghai Jiaotong University and his Ph.D. in reliability engineering from the University of Arizona. He has about 20-years of industry and research experience in Reliability Engineering. He is the author of over 30 publications and invention disclosures and his work and research area includes DFR methodology and process, reliability modeling and analysis, reliability testing, mechanical and electronics reliability, physics of failure, and reliability training. Wendai is also an active member of the RAMS Management Committee and is currently the Society of Reliability Engineers (SRE) Silicon Valley Chapter Vice President.

Many multi-component systems such as automobiles, computer servers, production & industrial equipment, appliances, engines, and power systems are generally repairable in service. It is also known that reliability performance metrics and analysis methodologies for non-repairable systems versus repairable systems are quite different. You would be surprised that the reliability theory for repairable systems is so underutilized. Most reliability engineering practices for repairable systems were directly adapted from methodologies for non-repairable systems, which are “well” developed. Many assumptions are commonly used, consciously or unconsciously, in engineering practices, such as exponential distribution for the “time between failures” (TBF) and even for the “time to restore” (TTR).

Traditional reliability theory (which primarily applies to non-repairable systems) is built upon the fundamental (random) variable of the time to failure (TTF). The TTF distribution defines all reliability metrics mathematically and practically. Similarly, should the behavior of both time between failures (TBF) and time to restore (TTR) together describe the reliability performance of a repairable system?

Because of the complexities associated with modeling of repairable system reliability, most research studies have only focused on evaluating the limiting statistical values such as steady-state system Availability, steady-state system MTBF, and etc. These limited evaluations, in turn, are typically based on one of the stationary Stochastic Point Processes such as Homogeneous Poisson Process, Non-Homogeneous Poisson Process, Renewal Process, Markov Process, and Regeneration Process - basically a certain level of “renewal” at the system level. In reality, maintenance activities, such as repairing, refurbishing and replacing, are really taking place at the module level. Reliability performance of a multi-component repairable system is actual an assembly of realizations for of all components.

This seminar will start with some case studies on the behavior of both TBF and TTR of simple repairable systems and of multi-component repairable systems, from which some simple conclusions are drawn and should be applied directly in engineering practice. Reliability performance and measures for repairable systems are then presented and discussed.

WEDNESDAY April 30SCV Reliability


Risk Analysis as Decision Support, plus

Directed Networking Speaker: Dr. Elisabeth Pate-Cornell, Professor and

Chair, Management Science and Engineering, Stanford University

Time: Social at 6:00 PM, Directed Networking at 6:30 PM, Dinner at 7:00 PM, Presentation at 7:45 PM

Cost: $25 for IEEE member, $30 non member ($5 more at door)

Place: Ramada Inn, 1217 Wildwood Ave (near 101 and Lawrence Expy), Sunnyvale

RSVP: through the website Web: www.ieee-scv-ems.org

Dr. M. Elisabeth Paté-Cornell, elected to the National Academy of Engineering in 1995, and currently a member of its Council, has served on the President’s Foreign Intelligence Advisory Board, and is currently a member of the Advisory Council of NASA’s Jet Propulsion Laboratory, and the Aerospace Corporation. Dr. Paté-Cornell is a world leader in research related to engineering risk analysis, risk management, decision analysis under uncertainty, and more generally, the use of Bayesian probability to process incomplete information. In recent years, her research has focused on the inclusion of both technical and organizational factors in probabilistic risk analysis models. These models have been applied to a wide variety of topics, ranging from the risk management of the NASA shuttle tiles to that of offshore oil platforms and medical systems such as anesthesia during surgery. She is currently working on risk management processes for complex projects and programs, with application to space, industrial and medical systems.

Dr. Paté-Cornell’s undergraduate degree is in mathematics and physics (BS, Marseilles, France), and her first graduate degrees are in applied mathematics and computer science (MS and Engineer Degree, Institut Polytechnique de Grenoble, France). She received a Masters degree in Operations Research (OR) and a Ph.D. in Engineering-Economic Systems (EES), both from Stanford University. She joined the Stanford faculty in 1981, where she became Professor and then Chair of the Department of Industrial Engineering and Engineering Management (IEEM). She is presently Professor and Chair of the Department of Management Science and Engineering, as well as a Senior Fellow.

Engineering risk analysis allows identifying the

weak points in a complex system and taking pro-active risk management measures. Dr. M. Elisabeth Paté-Cornell will describe the method and the use of the results to support lifecycle risk management and to set resource constraints (schedule and budget) anticipating their effects on the success of operations.

Networking Exercise

For our before-dinner networking, from 6:30 - 7:00, Richard Stallkamp will facilitate a networking and collaboration exercise for our management club.

THURSDAY May 1SCV Technology Management Council

MET Laboratories

EMC – Product Safety

US & Canada

• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)

Facilities in Union City and Santa Clara

www.metlabs.com [email protected] 510-489-6300


Photovoltaics – Challenges and Opportunities in Materials,

Machines and Manufacturing Speaker: K.V. Ravi, PhD, Director of Solar Business

Group, Applied Materials Time: Networking and Pizza Social: 6:00 PM,

Presentation: 7:00 PM Cost: none Place: National Semiconductor Building E

Auditorium, 2900 Semiconductor Drive, Santa Clara

RSVP: at ieee-scv-leos-may2008.eventbrite.com Web: ewh.ieee.org/r6/scv/leos/

Dr. KV Ravi is responsible for Business

Development for the Solar Business Group at Applied Materials. Prior to Applied Materials he was with Intel Corporation for over 10 years working primarily in the Materials Organization where his responsibilities have included the development of new silicon in support of Intel process technologies, developing low cost approaches for manufacturing silicon and the development of advanced substrates for future technologies. He has also worked in the Photovoltaics field for over 13 years at Mobil Solar Energy Corporation, leading the development of silicon ribbon based technologies. Ravi's other prior affiliations include Lockheed-Martin Corporation, Crystallume, Motorola Inc. and Texas Instruments Inc. He is the author of over 100 technical publications in the fields of metals, semiconductors, photovoltaics and CVD diamond technology and the author of the book "Imperfections and Impurities in Semiconductor Silicon". He has a Ph.D in Materials Science from Case Western University, an M.S. in Materials Science from the University of California, Berkeley, a B.S in Metallurgy from the Indian Institute of Science and a B.Sc in Chemistry from the University of Madras, India.

The photovoltaics industry and markets have been

growing at a very high rate in the last few years. Shipments grew by an extraordinary 56% in 2007, and the five-year compound annual growth rate for the industry from 2002 to 2007 has been 44% with the industry capacity increasing by 69% in 2007. In this presentation the current status of photovoltaic technology and markets will be discussed. Benchmarking with the semiconductor (integrated circuit) industry will be discussed to determine what aspects of semiconductor technology and manufacturing practices could be profitably copied by the photovoltaic industry. Future directions of the technology, with specific focus on silicon based products and the challenges and opportunities in scale manufacture, efficiency enhancements and cost reductions will be discussed.

TUESDAY May 6SCV Lasers and Electro Optics


Team AnnieWAY's Autonomous System for

DARPA Urban Challenge 2007 Speakers: Ben Pitzer, Annie Lien, for Team

AnnieWAY Time: Presentation at 7:00 PM Cost: none Place: Carnegie-Mellon West, Mountain View RSVP: by email to

IEEE_RAS_SCV_Chapter_Committee @yahoogroups.com

Web: ewh.ieee.org/r6/scv/ras

Annie Lien earned a B.A. summa cum laude in Classics (1998), a B.A. summa cum laude in History (1998), and a M.A. summa cum laude in Museum Studies-User Interaction (2005). Ms. Lien worked as User Experience Researcher and Speech Technology Linguist at Robert Bosch, Research and Technology Center, Palo Alto, where she was involved in a speech technology project sponsored by National Institute of Standards and Technology (NIST). It was during this time at Bosch when Ms. Lien joined Team AnnieWAY as team leader and worked on the DARPA Urban Challenge project on a part-time voluntary basis. Currently, Ms. Lien is User Experience & Usability Research Consultant to the Volkswagen Electronics Research Laboratory, Palo Alto. Ms. Lien focuses on social-psychological experimental studies of human-computer interaction, human factors research, and usability testing.

Ben Pitzer received a Diploma degree in Electrical

Engineering from the RTWH Aachen University in 2005. Mr. Pitzer is currently a Ph.D. student at the University of Karlsruhe in Germany and Robert Bosch LLC in Palo Alto. Mr. Pitzer’s research interests are autonomous systems, probabilistic reasoning, machine learning, and computer graphics. As a co-founder and member of Team AnnieWAY, Mr. Pitzer was responsible for system design, environment perception, and vehicle behavior.

This talk reports on AnnieWAY, an autonomous

vehicle that is capable of driving through urban scenarios and that successfully entered the finals of the DARPA Urban Challenge 2007 competition. We describe the main challenges imposed and the major hardware components. We outline the underlying software structure and focus on selected algorithms. Environmental perception mainly relies on a recent laser scanner, which delivers both range and reflectivity measurements. While range measurements are used to provide 3D scene geometry, measuring reflectivity allows for robust lane marker detection. Mission and maneuver planning is conducted via a concurrent hierarchical state machine that generates behavior in accordance with California traffic laws. We conclude with a report of the results achieved during the competition.

(Continued, next page)

WEDNESDAY May 7SCV Robotics and Automation


Team AnnieWAY was one of four international

teams chosen to participate in the DARPA Urban Challenge National Qualifying Event, October 2007. In the end, Team AnnieWAY was one of eleven finalists chosen for the final race on November 3, 2007. Team AnnieWAY began as a spin-off of the Collaborative Research Center on Cognitive Automobiles, started January 1, 2006 by the German Research Foundation (DFG). Research professionals and graduate students from the University of Karlsruhe, the Technical University of Munich, the Fraunhofer Gesellschaft (IITB in Karlsruhe), and the Universitaet der Bundeswehr Munich work together in this research center. The scope of Team AnnieWAY is to extract early research results from the Cognitive Automobiles project that would allow real-time operation of the vehicle under the restricted traffic environment in the Urban Challenge. Its team members are professionals in the fields of image processing, 3D perception, knowledge representation, reasoning, real time system design, driver assistance systems, autonomous driving, and usability/human factors research.


Content-Adaptive Efficient Resource Allocation for Packet-

Based Video Transmission

Speaker: Aggelos K. Katsaggelos, Dept. of Electrical and Computer Engineering, Northwestern University, and Signal Processing Society Distinguished Lecturer

Time: Fast food and drinks at 6:30 PM; Presentation at 7:00 PM

Cost: $2 donation for refreshments Place: National Semiconductor, north end of

Building E, 2900 Semiconductor Dr., Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/sps

Aggelos K. Katsaggelos (F) received the

Diploma degree in Electrical and Mechanical Engineering from the Aristotelian University of Thessaloniki, Greece, in 1979 and the M.S. and Ph.D. degrees both in Electrical Engineering from the Georgia Institute of Technology, in 1981 and 1985, respectively. In 1985, he joined the Department of Electrical and Computer Engineering at Northwestern University, where he is currently professor. He was the holder of the Ameritech Chair of Information Technology (1997-2003). He is also the Director of the Motorola Center for Seamless Communications and a member of the Academic Affiliate Staff, Department of Medicine, at Evanston Hospital.

Prof. Katsaggelos has extensive IEEE involvement. He is a Member, IEEE Proceedings Publication Board, IEEE Circuits and Systems Society Visual Signal Processing and Communications Technical Committee and Editorial Board, Academic Press, Marcel Dekker: Signal Processing Series, Applied Signal Processing, Computer Journal, EURASIP Journal on Image and Video Processing, and Advances in Multimedia.

He has served as Editor-in-Chief, IEEE Signal Processing Magazine; Member, SPS Publications Board and IEEE TAB Magazine Committee (1997-2002); Associate Editor, IEEE Transactions on Signal Processing (1990-1992); Area Editor, Elsevier Graphical Models and Image Processing (1992-1995); Steering Committees Member, IEEE Transactions on Image Processing (1992-1997) and IEEE Transactions on Medical Imaging (1990-1999);

Supporting video communication over lossy

channels such as wireless networks and the Internet is a challenging task due to the stringent quality of service (QoS) required by video applications and the many channel impairments. Two important QoS characteristics for video are the degree of signal distortion and the transmission delay. Another important consideration is the cost associated with transmission – for example, the energy consumption in the wireless channel case and the cost for differentiated services in the Internet (with DiffServ) case.

In this presentation we consider the joint adaptation of the source coding parameters, such as the quantization step-size and prediction mode, along with the physical layer resources, such as the transmission rate and power. Our goal is to provide acceptable QoS while taking into account system constraints such as the energy utilization. We discuss a general framework that allows a number of "resource/distortion" optimal formulations for balancing the requirements of different applications. We conclude the presentation with some of the grand opportunities and challenges in designing and developing video communication systems.

(biography, continued) Member, SPS Image and Multidimensional Signal Processing Technical Committee (1992-1998) and SPS Multimedia Signal Processing Technical Committee (1997-2001); and Member, SPS Board of Governors (1999-2001). He is the Editor, Digital Image Restoration (Springer-Verlag 1991); co-author, Rate-Distortion Based Video Compression (Kluwer 1997); co-editor, Recovery Techniques for Image and Video Compression and Transmission (Kluwer 1998); and co-author, Super-Resolution for Images and Video (Claypool, 2006) and Joint Source-Channel Video Transmission (Claypool, 2006). He is the co-inventor of twelve international patents and a Fellow of the IEEE. He is the recipient of the IEEE Third Millennium Medal (2000), SPS Meritorious Service Award (2001), SPS Best Paper Award (2001), and the IEEE International Conference on Multimedia and Expo Paper Award (2006).

MONDAY May 12SCV Signal Processing


Measuring Structural Resonances

Speaker: Doug Smith, Consultant Time: Social at 5:30 PM; Presentation at 6:30 PM Cost: none Place: Applied Materials Bowers Cafeteria,

3090 Bowers Ave., Santa Clara RSVP: not required Web: www.scvemc.org

Mr. Doug Smith held an FCC First Class Radiotelephone license by age 16 and a General Class amateur radio license at age 12. He received a B.E.E.E. degree from Vanderbilt University in 1969 and an M.S.E.E. degree from the California Institute of Technology in 1970. In 1970, he joined AT&T Bell Laboratories as a Member of Technical Staff. He retired in 1996 as a Distinguished Member of Technical Staff. Recently, he was Manager of EMC Development and Test at Auspex Systems in Santa Clara, and is now an independent consultant. Mr. Smith is a Senior Member of the IEEE and a member of the IEEE EMC Society Board of Directors.

His technical interests include high frequency effects in electronic circuit design, including topics such as signal integrity, design reliability, Electromagnetic Compatibility (EMC), Electrostatic Discharge (ESD), Electrical Fast Transients (EFT), and other forms of pulsed electromagnetic interference. He also has been involved with FCC Part 68 testing and design, telephone system analog and digital design, IC design, and computer simulation of circuits. He has been granted over 15 patents, several on measurement apparatus.

Mr. Smith has lectured at Oxford University, the University of California at Berkeley, Vanderbilt University, AT&T Bell Labs, and at many public and private seminars on high frequency circuit design, troubleshooting, measurements, ESD, and EMC. He is author of the book High Frequency Measurements and Noise in Electronic Circuits. He maintains a practical engineering website at www.dsmith.org containing nearly 100 useful technical articles.

Measuring structural resonances in equipment can

be a valuable aid to EMC troubleshooting. This talk builds on the original method of Scott Roleson of HP to today's frequencies as well as a few new methods. There will be several demonstrations along with lots of fun. No heavy math.

TUESDAY May 13SCV Electromagnetic Compatibility

ANSYS Channel Partner

• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

[email protected] www.ozeninc.com


Academic and Industrial Research: Using the Internet and

IEEE's XPLORE Database Speaker: Paul Wesling, CPMT Society Distinguished

Lecturer & SF Bay Area Council Communi-cations Director and GRID editor

Time: Social/Pizza at 4:00 PM; Presentation at 4:30 PM, Q&A at 5:30 PM

Cost: $5 donation for pizza (free, for students) Place: DeVry University Room 101, 6600

Dumbarton Circle, Fremont RSVP: not required; for additional information:

Mostafa Mortezaie, [email protected] (510) 574-1132

Web: www.e-grid.net/docs/0805-oeb-devry.pdf

Paul Wesling received his BS in electrical engineering and his MS in materials science from Stanford University. Following assignments at GTE/Lenkurt Electric (component engineering), ISS/Sperry Univac (bubble memory development, reliability, manufacturing engineering), Datapoint Peripheral Products (VP - Product Integrity), and Amdahl (design analysis, mainframe testing, console peripherals), he joined Tandem Computers (now HP's NonStop Enterprise Division) in 1985. As a member of the development team for advanced IC packaging, he designed several multi-chip module prototypes. In Tandem's Education Group from 1993-2002, he developed courses on reliability, managed Tandem's Distinguished Lectures series, and was on education's Technology Initiative team. He organized a number of advanced technology and professional skills development courses for his Division and also for the IEEE. He managed a grant from the National Science Foundation for the development of multimedia educational modules in the field of IC packaging. Now retired, he is communications director for the IEEE’s SF Bay Area Council and editor of its GRID Magazine.

As CPMT's vice president of publications for 22 years, he supervised four archival journals and a newsletter, and oversaw authors for IEEE Press books. He now serves as CPMT Society webmaster. He is a Fellow of the IEEE, and received the IEEE Centennial Medal, the CPMT Board's Distinguished Service award, the Society Contribution Award, and the IEEE's Third Millennium Medal. He has organized over 500 courses for the local IEEE chapter in the Santa Clara Valley.

ABSTRACT: IEEE is the largest publisher of electrotechnology literature in the world, and most results in our fields are extensively reported there. After a brief overview of IEEE's journals in computing, communications, packaging and other technical areas, the presentation will demonstrate methods for using the IEEE's on-line database of journal and conference papers for analysis of published results that can affect and influence the direction of development activities. This includes how to access the 1.6 million items using XPLORE, some search and selection strategies, full-text versus abstracts searches, storing searches for re-use, and using Google Scholar and Scitopia. Specific recommendations for accessing the full papers will be made. Both slides and actual online searches will be used to demonstrate various approaches that can be explored to find relevant papers, determine which labs/companies have teams working on specific aspects of the field, and the names of key researchers who might be contacted for assistance

and information. Accessing a portfolio of

relevant citations can make a great difference in a university’s research project or in a company’s development directions. It can help inform decisions that must be made about allocating resources, and help reveal development directions that have already been tried, issues to be

considered, experimental methods that have worked, etc. Maintaining access to IEEE's literature can be a key differentiating factor for your career as an engineer, developer or manager.

Both students and working engineers/managers are welcome to attend this talk, on the DeVry campus.

TUESDAY May 13OEB - DeVry University Student Chapter


High Performance Modules on Copper Substrates

Speaker: Peter Salmon, VP, Salmon Technologies,

LLC Time: Seated dinner at 6:30 PM, Presentation (no

cost) at 7:30 PM Cost: $25 for dinner Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road, near Lawrence Expy), Sunnyvale

RSVP: by email to Janis Karklins, [email protected]

Web: www.cpmt.org/scv

Peter Salmon is a systems engineer and inventor. He has authored over 25 patents in the areas of electronic packaging, high-speed digital printers, and electrostatic motors and generators. His packaging patents include novel solutions to flip chip manufacture and assembly, advanced socket assemblies, a new functional test method at the board level, parallel testing of microprocessor wafers at full speed and full power, advanced copper substrates, and automated assembly test and rework at the wafer level. He holds a bachelor’s degree from Auckland University, New Zealand, and two graduate degrees from Northeastern University, all in Electrical Engineering.

A concept for a high-performance module using build-up layers on copper is presented. Copper provides mechanical support, an electrical backplane, good thermal conductivity, and is impervious to water. Photolithographic processing can be performed on wafer-sized copper substrates using coaters and aligners (from Suss Microtec, for example). Stacked module configurations can be well-cooled, and have good test and rework capabilities.

The ability to make compact assemblies with high silicon content spurs parallel development in the areas of cooling, testing, and rework. New test and cooling concepts will be described, looking towards automated assembly, test, and rework at the wafer level. Potential innovations in socketing and optical interfaces will also be briefly described.

The packaging strategies are supported by 12 new patent applications, some of which have issued.

WEDNESDAY May 14SCV Components, Packaging and Manufacturing Technology

M E S OIn t eg r at io n

Let us help you integrate your product and get it into production • MEMS & Sensors Experts • Product Design ▪ R&D ▪ Failure Analysis • Medical Devices ▪ High-Volume Manufacturing • Experienced Consultants www.MesoIntegration.com

[email protected] TEL: 949.278.0275


Extending the Concept of Femtocells to the Outdoor Enterprise

Speaker: Francis daCosta, MeshDynamics Time: Presentation at 6:00 PM Cost: none Place: National Semiconductor, Building E,

Conference Room, 2900 Semiconductor Dr, Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/comsoc

Francis daCosta founded MeshDynamics to develop high performance wireless mesh networks for wide area coverage of voice, video and data. Francis has been a research scientist for Northrop and MITRE. Francis has a Masters from Stanford University and a Bachelors from Indian Institute of Technology, Delhi. He is a member of IEEE.

Mesh nodes supporting SIP registries can provide VOIP communication infrastructure in scenarios where traditional forms of wireless communication either do not exist or provide inadequate coverage. Scenarios include underground mining, coverage in rural areas and active military deployments. This presentation describes core architecture and implementation specifics related to efficient transmission of latency sensitive packets -- e.g. Voice and Video -- over multiple hops.

WEDNESDAY May 14SCV Communications

Valon Technology, LLC

valontechnology.com

[email protected]

RF and Wireless Product Design & Development

- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness

Redwood City (650) 369-0575


An 802.11n 2x2 MIMO Radio in 0.13um CMOS and

A Bluetooth v2.1 radio in 0.13um CMOS

Speakers: Dave Weber and Sotirios Limotyrakis, Atheros Communications, Inc

Time: Refreshments at 6:00 PM; Presentation at 6:30 PM

Cost: small donation for food Place: National Semiconductor, Building E,

Auditorium, 2900 Semiconductor Dr, Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/ssc

Sotirios Limotyrakis was born in Athens, Greece, in 1971. He received the B.S. degree in electrical engineering from the National Technical University of Athens in 1995 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1997 and 2005. In the summer of 1993, he worked at K.D.D. Corporation, Saitama R&D Labs, Japan, on the design of communication protocols. During the summers of 1996 and 1997, he worked with the RF design group at the Texas Instruments Inc. R&D center in Dallas, Texas. He focused on LNA, low phase noise oscillator design, and GSM mobile unit transmit path architectures. In 2004 he joined Atheros Communications as a Member of Technical Staff. His current research interests include the design of mixed-signal and RF circuits for high speed data conversion and broadband communications.

In 1995, Dr. Limotyrakis was awarded the W. Burgess Dempster Memorial Fellowship by the School of Engineering at Stanford University. He is the corecipient of the 2004 IEEE Beatrice Winner award for editorial excellence and the recipient of the 2004 Analog Devices outstanding student designer award.

David Weber is a manager in the analog design group at Atheros Communications. He received a B.S.E.E. degree from the University of New Hampshire in 1995, and in 1996 he received an M.S.E.E. degree from Stanford University. From 1996 to 1999 he worked at Hewlett Packard as a hardware design engineer, designing RF power modules for digital cellular phones. In 2000, he joined Atheros Communications as an analog design engineer, where he designed a variety of circuits for wireless LAN SoCs, including power amplifiers, frequency synthesizers, and data converters. In 2004 he descended into management, and now leads the development of CMOS radios for WLAN, Bluetooth, and other technologies. He has been a member of the IEEE since 1993.

Talk #1 – An 802.11n-draft-compliant 2x2 2-stream MIMO

radio SoC incorporates two dual-band RF transceivers, analog baseband filters, data converters, digital PHY and MAC, and a PCI Express interface. Implemented in a 0.13-um CMOS, it occupies 36mm2. For 2.4GHz/5GHz, the receive chain NF is 4dB/6dB, and the transmit EVM is -34dB/ -30dB at -5dBm output power. Details will be presented on the RF and baseband sections of the chip.

Talk #2 –

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13-um CMOS technology. Radio architectures have been chosen that minimize the area of the analog and RF circuits. This design features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500kHz IF receiver with first order low-pass analog filtering, and a ∆Σ ADC. The total SoC die area is 9.2mm2 with only 3.0mm2 used for analog and RF circuits. The basic-rate radio power consumption is 28mA in receive and 30mA in transmit.

THURSDAY May 15SCV Solid State Circuits

Bernie Siegal

650-961-5900

[email protected] www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures


Highly Integrated Re-configurable RF Front-ends in Deep

Sub-micron CMOS Speaker: Naveen Yanduru, Design Manager, Texas

Instruments Inc. and IEEE/CAS Distinguished Lecturer

Time: Fast food and drinks at 6:30 PM, Presentation at 7:00 PM

Cost: none Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose RSVP: not required Web: ewh.ieee.org/r6/scv/cas

Naveen Yanduru is currently a Design Manager at

Texas Instruments Inc., and a Member Grade Technical Staff. While at Texas Instruments he has led design teams in the design of various RF receivers including GSM/EDGE, WCDMA, TDSCDMA, GPS and multi-mode receivers. He is currently involved in the design of DRP™ chips, which are highly integrated ICs in deep sub-micron CMOS processes for mobile phones.

Various RF bands, standards, modulation

schemes, duplex mechanisms and signal bandwidths needed for the mobile terminal call for a highly adaptable and reconfigurable RF receiver. The biggest bottleneck in achieving this goal lies with the RF pre-select filter at the antenna, which is band specific and creates a bottleneck in being able to share the hardware.

Solving this multi band programmability is the biggest challenge in achieving aN RF receiver for software defined radio. A few of the possible architectures and their limitations are presented. However, designing a multi mode RF receiver for a given RF band with highly reconfigurable performance is an achievable goal.

A WCDMA/EDGE receiver without inter-stage SAW filter in 90nm digital CMOS is used as an example in illustrating the architecture, circuit and system considerations for such a receiver.

MONDAY May 19

SCV Circuits and Systems, with Solid State Circuits, Microwave Theory and Techniques


Surveying the Landscape of Established and Emerging Patent

Monetization Models: New Opportunities for Technical

and Patent Experts Speaker: Ron Laurie, Inflexion Point Strategy, LLC Time: Presentation at 7:00 PM Cost: none Place: KeyPoint Credit Union, 2805 Bowers Ave.,

Santa Clara RSVP: not required Web: www.CaliforniaConsultants.org

Ron Laurie has worked in

Silicon Valley for over forty years, initially as a computer programmer and systems engineer, and then as an intellectual property lawyer. In 2004, he co-founded Inflexion Point Strategy, LLC, an intellectual property investment bank. This company advises technology companies and institutional investors in acquiring, divesting, and investing in IP-rich companies and business units, as well as in strategic IP assets in the form of patent portfolios, exclusive field-of-use license rights and related know-how.

The last couple of years has brought about rapid and dramatic changes in patent law. The impetus for this change has come not only from the usual sources - the U.S. Court of Appeals for the Federal Circuit and the U.S. Patent and Trademark Office - but also as a result of an unprecedented combination of increasing attention on patent cases by the U.S. Supreme Court as well as the patent reform debate in Congress. Against the backdrop of what many see as a constricting legal environment, the market for buying, selling and investing in IP - and patents in particular - has exploded. This has created a broad range of new opportunities for technical and patent experts.

Ron will present an overview of the new patent monetization ecosystem, including brokers, auctions,

exchanges, aggregators, enforcers, financiers, investors and defensive alliances/pools. He will also highlight the areas in which domain expert support is needed, and will discuss the effect of the current legal and economic environments on the growth and adaptation of the various business models.

TUESDAY May 20SCV Consultants' Network of Silicon Valley



[email protected]



Expert Roundtable on Common Career Issues

Speakers: Cynthia Shapiro (author of "What Does

Somebody Have To Do To Get A Job Around Here?"); Irene Koehler - HR consultant ("First Thing Tomorrow"); Jonathan David (IEEE Region 6 Professional Activities Coordinator); Stephen P. McInerney (IEEE GOLD volunteer)

Time: 6:00 PM Cost: none (dinner and books will be available for

purchase) Place: To be determined -- see website link below RSVP: by email by May 16 to Jonathan David,

[email protected] Web: ieee-scv-pace.blogspot.com/2008/04/building-

foundation-for-your.html

Cynthia Shapiro, International Best Selling Author - Speaker - Career Expert

A former human resources executive turned employee advocate and career advisor, Cynthia Shapiro has 18 years experience in human resource, personnel, labor relations, employee and executive coaching, recruiting, and hiring. She has worked with employees, mangement teams, and executives at: Microsoft, Lowes, Washington Mutual, IBM, Federal Express, United Airlines, Warner Brothers, Disney, Jet Blue, American Express, Cicso, BellSouth/AT&T, Sirius, Quest, Intel, Hewlett-Packard, Boeing, and many more.

Irene S. M. Koehler, Principal, First

Thing Tomorrow Human Resources Consultants

With over twenty years in the Human Resources field, Irene Koehler’s professional experience has included work in the public and private sectors, union and non-union environments, and in organizations employing from 15 to 70,000 people. Providing guidance to senior leaders in times of change is a key area of expertise.

IEEE GOLD is hosting a panel of career experts to

address common career issues arising in your first few years of a technical career. Bring your questions to the panel, or submit them by email in advance.

Topics include starting your first job, working with people, recognition, building your reputation, advancement, networking, working with recruiters, the interview process, resumes, negotiating compensation. The Panelists will address common issues, and take questions from the Audience.

Our Career Experts include Cynthia Shapiro (author of "What Does Somebody Have To Do To Get A Job Around Here?" ) and Irene Koehler - HR consultant ("First Thing Tomorrow"). Also represented will be the Startup community and a recruiter. Moderated by Jonathan David (IEEE Region 6 Professional Activities Coordinator), & Stephen P. McInerney (IEEE GOLD volunteer).

TUESDAY May 20SCV GOLD - Grads of the Last Decade, with SCV-PACE



[email protected]



1,000 kW PV Solar System Design-Build Projects

Speaker: Diep Nguyen, P.E., President, DTN

Engineers Inc. Time: Social/snacks at 5:30,

Presentation at 6:00 PM Cost: $10 for IEEE members and $15 for guests Place: Cutler-Hammer, 20923 Cabot Blvd.,

Hayward RSVP: by email to Carole Pharr,

[email protected], (408) 282-1500 x213

Web: www.e-grid.net/docs/0805-oeb-pes.pdf

Diep Nguyen, P.E., President of DTN Engineers Inc. Diep is an electrical engineer with more than 32 years hands-on practice. He holds BSEE, MSEE degrees and California Professional Engineer Licenses in electrical, control systems and fire protection engineering. Diep has been a long-time active senior member of NFPA, ISA, IEEE, and AEE certified CCP and DGCP

The operational costs of conventional power plants have been sky-rocketing due to increasingly high fuel costs, and thus more attention now has been paid to the renewable energy sources such as solar, wind, fuel cells etc.. Because of Federal Tax Credits and other favorable factors such as visible State and local public and political supports, various PV Solar Projects have been recently possible in the San Francisco Bay Area. This presentation will discuss the technical aspect of recent 1,000 kW PV Solar Design-Build Projects for three community colleges located in the East Bay.

WEDNESDAY May 21OEB Power Engineering


Advancements in Noise Measurement

Speaker: Ken Wong, Agilent Technology Time: Social/refreshments at 6:30, Presentation

at 6:45 PM Cost: none Place: Board Room, Cogswell College, (1175

Bordeaux Dr, Sunnyvale RSVP: by email to Brian Lee,

[email protected] Web: ewh.ieee.org/r6/scv/ims

Ken Wong has been with HP/Agilent for over 35 years. His experience at HP/Agilent includes product design, manufacturing process development, and test process development of microwave hybrid microcircuits and instruments.

Currently, he is the principal engineer responsible for the development, modeling, and measurement of precision microwave calibration and verification standards. He is also responsible for the development of VNA calibration methodology.

He has published and presented many papers on VNA calibration and standards. He had been granted many patents on connector design and VNA calibration. He is an officer of the ARFTG (Automatic Radio Frequency Techniques Group) Executive Committee and a senior member of the IEEE.

Noise measurements were developed since the

beginning of telecommunication. The Y-factor method was introduced back in the 1930's. The cold source method was also mentioned at the same time. Noise parameters were defined in the late 1950's and at about the same time, the noise wave concept was also introduced as an alternative amplifier noise model. The significance of noise wave wasn't noticed until the mid 1960's for amplifier network analysis. Since then, numerous measurement methods of noise parameters and noise wave were proposed. Refinements to the Y-factor methods were also made. However, no commercial noise wave measurement system was available until recently.

This presentation will present an overview of the noise measurement methods and show their relationships. The new noise wave measurement system, that provides full mismatch corrected noise figure measurements, will be discussed.

WEDNESDAY May 21SCV Instrumentation and Measurement


802.11n and Outdoor Mesh Wi-Fi: Market and Standards Update

Speaker: Dr. Malik Audeh, Sr. RF Systems Engineer,

Tropos Networks Time: 7:00 PM Cost: none Place: 6101 Bollinger Canyon Road, San Ramon RSVP: by May 21st by email to Bill Kaminsky,

[email protected], Web: www.comsoc.org/oeb

Malik Audeh is a senior RF Systems Engineer at Tropos Networks, where he is involved in the development and deployment of outdoor mesh Wi-Fi systems. He is a voting member of the IEEE 802.11 working group and a past member of IEEE 802.16. He previously held product management and systems engineering roles at Trapeze Networks, Hybrid Networks, and Telesis Technologies Lab. He received the Ph.D. degree from UC Berkeley specializing in the area of wireless communications.

The demise of outdoor Wi-Fi has been greatly exaggerated. Numerous beneficial industrial and municipal applications are running today over outdoor mesh Wi-Fi networks using 802.11a, b, and g. We will provide an update illustrating some of the operational and life-changing applications running over these networks.

We will also describe and discuss the ongoing 802.11n standards work in the IEEE, and the true technological leaps being placed into the standard through this amendment. There are different benefits from 802.11n for different use cases. Lastly we will describe specific benefits 802.11n will and will not have in the outdoor Wi-Fi environment.

THURSDAY May 22OEB Communications


Financial Advising Seminar for Engineers:

Options for Confidence, Control for your Financial Goals

Speaker: Kathie Chappell, Ameriprise Financial Time: Presentation and discussion at 6:30 PM Cost: none Place: 180 Montgomery St, Suite 2480, San

Francisco RSVP: by May 21st by email to Alex Goldhammer,

[email protected] Info: Alex Goldhammer, [email protected]

Ameriprise Financial Services, Inc. offers financial advisory services, investments, insurance and annuity products. RiverSource products are offered by affiliates of Ameriprise Financial Services, Inc., Member FINRA and SIPC.

The GOLD Chapter is looking for someone with

basic web skills to be our webmaster. We provide the server space (on IEEE’s server) and give you FTP access – or you can host it in other ways. Help us publicize our meetings and events by serving in this critical capacity! Contact Alex (above).

Do you have a clear picture of your financial

goals? Saving and investing to achieve those goals can be confusing when you are just starting out. We'll help you explore your options for feeling more confident, in control and on track with your financial goals – and help you develop a strategy that's right for you.

This is an educational seminar, and there's no cost or obligation to attend. Ameriprise Financial is committed to helping you learn more about your options in managing your financial resources and giving you straightforward guidance on personal money management and investment strategies.

In addition, you will receive an informational workbook that you can use to assess your current financial situation.

We'll explore issues like: * Saving for short- medium- and long-term goals * Understanding debt and credit issues * Maximizing employer-sponsored savings plans * Savings plans with tax-free earnings * Diversifying your assets and asset allocation * Protecting your assets Seating is limited. Please make reservations for

you and up to three guests.

THURSDAY May 22SF GOLD - Grads of the Last Decade


Spintronic Biochips for Biomolecular Recognition

Speaker: Prof. Paulo P. Freitas, INESC MN and

Phys. Dept, Inst. Superior Tecnico, Lisbon, Portugal

Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM

Cost: none Place: Western Digital, 1710 Automation Parkway,

San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Paulo Freitas is a Full Professor of Physics at the Instituto Superior Tecnico (IST) in Lisbon, and the Director of INESC Microsystems and Nanotechnologies. Current research topics include MRAMS, read heads for ultra high density recording, magnetoresistive biochips, and sensors for biomedical applications. He has been involved in research in the area of magnetoresistive materials and devices since he received his Ph.D in Solid State Physics from Carnegie Mellon University in 1986. His PhD thesis was on the subject of anisotropic magnetoresistance of ferromagnetic thin films and alloys. He then joined IBM Research at Yorktown Heights as a post doctoral fellow working on high-TC superconductivity and transport properties of ferromagnetic thin films. In 1988 he joined INESC in Lisbon, where he started the Solid State Technology Group.

In 1989 he became Professor of Physics at the Instituto Superior Tecnico in Lisbon. From 1992 to 1996, he was responsible for the start up and operation of INESC´s ASIC back-end of the line microfabrication facility. From 1996 till now, his research areas expanded to magnetoresistive read elements for magnetic data storage, magnetoresistive sensors, MRAMS, and biomedical applications including magnetoresistive biochips. He became director of INESC Microsystems and Nanotechnologies in 2001, and Full Professor of Physics at IST in 2002. Over this period, he co-authored over 200 technical papers and several chapter books. Professional activities include membership in IEEE, participation in several Publication/Program/Advisory Committees of MMM and Intermag Conferences.

Integrated spintronic biochip platforms are being

developed for portable, point-of-care diagnostic applications. The platforms consist of a microfluidic unit where the bioassay takes place, an arraying and detector chip consisting of target arraying current lines and integrated magnetoresistive sensors, and electronic control and readout boards. Probe biomolecules are immobilized by microspotting over sensor sites, and target biomolecules, labeled with magnetic nanoparticles, are arrayed over the probe sites (magnetically assisted hybridization). After proper washing, hybridized targets are recognized by the fringe fields created by the magnetic beads, (and) detected by the incorporated magnetoresistive sensors. Detecting geometries will be reviewed, using either out-of-plane or in-plane bead excitation, and dc or ac detection/excitation. Detection limits using spin valve and tunnel junction sensors will be presented, depending ultimately on platform electronic noise, and sensor noise characteristics. Applications to gene expression chips (Cystic Fibrosis gene mutation detection) and imuno assay chips (anti-body-antigen recognition, e-Coli, Salmonella detection) will be presented. Spintronic biochips are also being integrated into multi-module lab-on-chip platforms including

1. biomolecule extraction from biological fluids (magnetophoresis),

2. PCR modules (if required), and 3. the biomolecular recognition module.

Alternative spintronic biochip geometries will also be presented (lateral flow biosensors), where a magnetoresistive reader scans the surface of a porous strip, where labeled target biomolecules bind to immobilized probes. Finally, a brief review of other biomedical applications of magnetoresistive sensors will be given, from hybrid sensors targeted at biomedical imaging,

to magnetic tweezers/sensors for DNA translocation monitoring.

TUESDAY May 27SCV Magnetics


'Leading Indicators' for More Effective Life Testing

Speakers: Arthur Zingher & Mike Silverman, Ops a la

Carte Time: Optional dinner, 5:45 PM; Presentation at

7:00 PM Cost: none for presentation Place: dinner El Torito Mexican Restaurant, 2950

Lakeside Drive, Santa Clara; talk at Applied Materials, Bowers Café, 3090 Bowers Ave, Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/pses

Arthur Zingher, Senior Reliability Consultant at Ops a la Carte, has over 25 years experience in physics and reliability. Arthur holds 33 issued patents with 19 more pending. Arthur was a Distinguished Engineer at Sun Microsystems, focused on HW Research. He was also a Staff Member at IBM Research, Yorktown NY, focused mainly on HW. Arthur holds a Ph.D. in Physics from U.C. Berkeley and a B.A. in Physics & Math from Columbia.

Mike Silverman, Managing Partner at Ops a la Carte, has over 20 years experience in reliability engineering, management, training and improvement. Mike has tested over 300 products and consulted for over 200 companies in a variety of industries, including medical, telecommunications, networking, semiconductor equipment and consumer electronics. He has a BS in Electrical and Computer Engineering from the University of Colorado at Boulder and is a Certified Reliability Engineer through ASQ. Mike is a member of many professional societies and currently the IEEE Reliability Society Santa Clara Valley Chapter Chair.

The recent grounding of flights by American

Airlines shows that operational maintenance and potential equipment failures are a serious “real-world” safety concern. Safety standards for power tools also look at failure modes. One way to anticipate field failures is to run life tests.

This presentation describes a new approach to life testing, using "Leading Indicators", that can help overcome common challenges and constraints, such as: - Too few specimens and too little time available for

life testing. - Life testing results too late to improve product

development. - Maintenance based on the average status of a

population of similar units in similar operation, instead of the real-time status of each specific unit.

Failures are expensive, failures irritate customers, and failures can KILL you … How can you anticipate dangerous field failures with only a few units to test?

TUESDAY May 27SCV Product Safety Engineering


Advances in Power System Protection and Automation

Speaker: Ron Y. Beltran, P.E., Field Application

Engineer, GE Multilin Time: Social at 5:30 PM; Presentation at 6:00

PM; Dinner at 7:00 PM Cost: $25 ($10 for first 5 reserved IEEE Student

Members) Place: Sinbad’s Restaurant, Pier 2 The

Embarcadero, San Francisco RSVP: by email to Jack Lin, [email protected] to

qualify for our drawing of an IEEE Color Book at dinner.

Web: www.e-grid.net/docs/0805-sf-ias.pdf

Our speaker is Ron Beltran, a Field Application Engineer for GE Multilin. His responsibilities include product and applications support in power system relaying and automation for utility and industrial customers in the Western U.S.A. Ron has nearly 20 years of experience in Power System Engineering with past work experience at Mobil Oil, Pacific Gas and Electric, and ABB. He is also a Senior Member of the IEEE (PES and IAS) and a Registered Professional Electrical Engineer in the State of California.

The development of microprocessor-based

technology in protective relaying has enabled users to employ these devices in a variety of ways. The “protective relay” has evolved into an “intelligent electronic device” with enhanced functionality in protection and control. The key is for the user to understand the capabilities of these devices so that they can be utilized in ways that maximize return to the organization. We will discuss applications that show these capabilities. These applications may include automation and protection methods to mitigate Arc Flash requirements; innovative control methods that reduce engineering and commissioning requirements; and the enhanced use of tools and information to enhance the troubleshooting of both electrical system and equipment events.

Please join us in welcoming our speaker to San Francisco for what is sure to be an interesting and productive session.

TUESDAY May 27SF Industry Applications


Enhancing Image Fidelity through Spatio-Spectral Design for Color

Image Acquisition, Reconstruction, and Display

Speaker: Keigo Hirakawa, Postdoctoral Research

Associate, Harvard University, Department of Statistics

Time: Fast food and drinks at 6:30 PM; Presentation at 7:00 PM

Cost: $2 donation for refreshments Place: National Semiconductor, north end of

Building E, 2900 Semiconductor Dr., Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/sps

Dr. Keigo Hirakawa is currently a postdoctoral research associate at Harvard University, working under Prof. Xiao-Li Meng in the Statistics Department. His current research generalizes image processing techniques to the case when the given image has missing data.

The majority of the image processing algorithms proposed today present engineering solutions to imaging problems. Keigo Hirakawa's multidisciplinary research in model-based signal processing, however, is motivated by mathematical, statistical, psychological, and real-world models. In particular, he is interested in bridging the noticeable disconnect between the current engineering solutions to imaging problems and areas of studies that include statistics, human visual system, color science, and device-specific noise models.

Hirakawa graduated magna cum laude from Princeton University with B.S.E. in electrical engineering, a minor in computer science, and another minor in music performance. He became interested in image processing while interning at NEC Corporation in Japan in 1998, and he helped design digital camera hardware for Hewlett-Packard in 1999.

After graduating from Princeton, Hirakawa began the M.S./Ph.D program at Cornell University. He worked extensively in model-based image processing, including image denoising, methods to combine demosaicing and denoising, and color science. He has been an imaging consultant, lecturer, and research engineer at Texas Instruments,

In the first part of the talk, we consider extending

an image denoising problem to the problem of missing or incomplete pixel values --- either due to mechanical designs or distortions. In the context of wavelet-based image processing, missing or incomplete pixels pose a particularly difficult challenge because none of the wavelet coefficients can be observed. In this talk, a unified framework for coupling the EM algorithm with the Bayesian hierarchical modeling of transform coefficients is presented. This empirical-Bayes strategy offers a statistically principled and extremely flexible approach to a wide range of pixel estimation problems including image denoising, image interpolation, super resolution, demosaicing.

In the second part of the talk, we consider the "throughput" of color imaging systems. Pixel values are typically sensed or displayed via a spatial subsampling procedure implemented as a color filter array --- a physical construction whereby only a single color value is measured or displayed at each pixel location. Owing to the growing ubiquity of acquisition and display devices, much of recent work has focused on the implications of such arrays for subsequent digital processing, including in particular the canonical demosaicking task of reconstructing a full color image from spatially subsampled and incomplete color data acquired under a particular choice of array pattern. In contrast to the majority of the acquisition and display literature, we consider here the problem of color filter array design and its implications for spatial reconstruction quality. We prove the sub-optimality of a wide class of existing array patterns, and provide a constructive method for its solution that yields robust, new panchromatic designs implementable as subtractive colors.

(Biography, continued) Hewlett Packard, Agilent Technologies, and Sony. He has also written a complete MPEG-4 simple profile encoder in Matlab and a complete H.261 codec in assembly language. He completed his M.S. in 2003, and Ph.D in 2005.

Hirakawa maintains an active second career as a jazz pianist. He was educated at Eastman School of Music and in 2006, completed his M.M. degree in jazz studies at New England Conservatory of Music in Boston. He is currently seeking a tenure-track assistant professor position.

MONDAY June 2SCV Signal Processing


The Year of Living Dangerously:

Extraordinary Results for an Enterprise Agile Revolution

and Globalization and Why it Works

Speakers: Steve Greene and Chris Fry; Kevin Walsh Time: Social at 6:00 PM, Pre-dinner Presentation

at 6:30 PM, Dinner at 7:15 PM, Presentation at 7:45 PM

Cost: $25 for IEEE member, $30 non member ($5 more at door)

Place: Ramada Inn, 1217 Wildwood Ave (near 101 and Lawrence Expy), Sunnyvale

RSVP: through the website Web: www.ieee-scv-ems.org

Chris Fry is a Senior Director at Salesforce.com

responsible for platform software development. He specializes in Software as a Service and creating and leading agile teams. He is the author of JSR-173 (Streaming API for XML) and has led the implementation and deployment of massively scalable Web Services at Salesforce.com and BEA. He received his Ph. D. in Cognitive Science from UCSD and was a post-doctoral fellow at UC Berkeley.

Steve Greene is the Director of Tools & Process at Salesforce.com and is responsible for the implementation and evolution of agile methodologies and supporting tools for the Technology organization. He has held numerous senior management positions at On-demand startup and large enterprise software companies including DigitalThink, Hyperion, PeopleSoft/Oracle, SPC and AOL. He brings a wealth of expertise and experience in productivity, process and product delivery. He holds a BS in Computer Engineering from San Jose State University and is a board member of the BayAPLN.

Kevin Walsh is a general partner at Ridge Partners LLC, an investment and buy-out company focused in the high technology sector. He is also the Dean's Executive Professor of Management at the Leavey School of Business and was previously Vice President of Corporate Planning and Worldwide Financial Operations at Sun Microsystems. Prior to joining Sun, Kevin was COO at Spatial Technology and held Vice President positions at Schlumberger and Fairchild Semiconductor in both Europe and the USA. He is a graduate of the London School of Economics, a member of the Institute of Management Consultants and Certified Chartered Accountant (UK).

The Year of Living Dangerously: Extraordinary Results for an Enterprise Agile Revolution

Many software organizations today ask "How do we make an agile transformation and what benefit will we get?" Should you transition your organization to agile all at once or proceed more iteratively, team by team? This talk describes Salesforce.com's year of living dangerously, where we moved our entire R&D organization to an agile model. The key difference in our approach was to throw the switch on 30 teams all at once. Most agile experts thought this was a crazy approach; however, in the end our transition became one of the fastest and largest agile transitions. In just 3 short months we moved our entire team from a waterfall-based approach to an iterative, Scrum based methodology we've named ADM (Adaptive Development Methodology). Over the course of the year we have refined and measured our progress and learned many lessons. This approach was a great risk for the organization that has ultimately delivered dramatic results and extraordinary business value.

Globalization and why it works!

The talk will focus on how Globalization is impacting the world and the US economy and what it means for the future of a skill-based society.

THURSDAY June 5SCV Technology Management Council


Integrated On-Chip Inductors Using Magnetic Material

Speaker: Don Gardner, Intel Corporation Time: Cookies & Conversation at 7:30 PM,

Presentation at 8:00 PM Cost: none Place: Western Digital, 1710 Automation

Parkway, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Don Gardner has been with Intel Corporation since 1991 and is currently a principal engineer in Intel Research and a visiting scientist at Stanford University. Don received his PhD in Electrical Engineering from Stanford University. He has had appointments as a visiting research scientist at Hitachi Research Labs in Japan and as an instructor at Stanford University. He is the inventor or co-inventor of 56 patents including for inductors using high-frequency magnetic materials, Al-Ti layered metal for interconnections, reflow of copper metal, and embedded ground planes. Don has published and/or presented over 200 electrical engineering, materials science and computer science papers. He has received 3 Best Paper and Poster awards at international conferences and his paper on inductors was judged the best at the IEEE IITC conference. He enjoys bringing new life to old technologies by blending them with different technologies or recent science and new materials. His current interests include magnetic materials for high-frequency inductors, nanostructure design and devices, silicon-based optoelectronic devices, and new process technology.

On-chip inductors with magnetic material are

integrated into both advanced 130 nm and 90 nm CMOS processes. The inductors use copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28× were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability (>250°C), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The

CoZrTa alloy can operate at frequencies up to 9.8 GHz, but tradeoffs exists between frequency, inductance, and quality factor. The effects of increasing the magnetic film thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract and examine the effects of magnetic vias on the inductor structures. The inductors with thick copper and thicker magnetic films have inductance densities of up to 1.3 mH/mm2, resistances as low as 0.04 W, and quality factors of 8 at 50 MHz.

TUESDAY June 10SCV Magnetics


Thermal Stress Modeling in Electronic and

Photonic Engineering: Is FEA the Only Tool?

Speaker: Dr. Ephraim Suhir, CPMT Society

Distinguished Lecturer; Bell Laboratories (ret); Dept of Electrical Engineering, UC-Santa Cruz; Dept of Mechanical Engineering, Univ of Maryland

Time: Seated dinner at 6:30 PM, Presentation (no cost) at 7:30 PM

Cost: $25 for dinner Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road, near Lawrence Expy), Sunnyvale

RSVP: by email to Janis Karklins, [email protected]

Web: www.cpmt.org/scv Dr. Ephraim Suhir is a Fellow of the IEEE, the

American Physical Society (APS), the American Society of Mechanical Engineers (ASME), the Institute of Physics (IoP), UK, and the Society of Plastics Engineers (SPE). He has formed, and is chairing, the IEEE TAB NTDC Group on Portable Information Devices (PIDs), and the IEEE Vehicular Technology Society (VTS) Technical Committee on PIDs, and is co-founder of the ASME Journal of Electronic Packaging and served as its Technical Editor (Editor-in-Chief) for eight years (1993-2001). Ephraim holds 20 US patents and has authored about 300 technical publications (papers, book chapters, books). He is currently a BoG Member and Distinguished Lecturer of the IEEE CPMT Society and is Associate Editor of the IEEE CPMT Transactions on Advanced Packaging. He has organized many successful conferences and symposia in the USA, Europe and Asia, and presented numerous keynote and invited talks worldwide.

Some major awards: 2004 ASME Worcester Read Warner Medal for outstanding contributions to the permanent literature of engineering through a series of papers in Mechanical, Microelectronic, and Optoelectronic Engineering, which established a new discipline known as the Structural Analysis of Microelectronic and Photonic Systems; (cont.)

This talk addresses the role and attributes of, as

well as the state-of-the art and major findings in, the field of analytical thermal stress modeling in electronic and photonic engineering. The emphasis is on simple and practical models that can be and have been used in the physical design and reliability evaluations of electronic and photonic assemblies, structures and packages.

It covers the role, attributes, merits and shortcomings of analytical thermal stress modeling, and its interaction with numerical (primarily finite-element) and experimental techniques. The topics addressed include Timoshenko's bi-metal thermostat theory and its extension; thermally matched assemblies and assemblies bonded at the ends; design recommendations; thin film structures; polymeric materials and plastic packages of IC devices; photonic (primarily fiber optic) structures; and application of probabilistic approaches. Thermal stress modeling in nano-materials and nano-structures is also briefly discussed.

A review paper "Analytical Thermal Stress Modeling in Electronic and Photonic Systems" is available upon request. It will be published later on this year in the ASME Applied Mechanics Reviews. Biography (continued)

… 2001 IMAPS John A. Wagnon Technical Achievement Award for outstanding contributions to the technical knowledge of the microelectronics, optoelectronics, and packaging industry; 2000 IEEE-CPMT Outstanding Sustained Technical Contribution Award for outstanding, sustained and continuing contributions to the technologies in fields encompassed by the CPMT Society; 2000 SPE International Engineering/Technology (Fred O. Conley) Award for outstanding pioneering and continuing contributions to plastics engineering; 1999 ASME and Pi-Tau-Sigma Charles Russ Richards Memorial Award for outstanding contributions to mechanical engineering, and 1996 Bell Laboratories Distinguished Member of Technical Staff Award for developing extremely accurate and robust engineering mechanics methods for predicting the reliability, performance, and mechanical behavior of complex structures used in manufacturing Lucent Technologies products.

WEDNESDAY June 11SCV Components, Packaging and Manufacturing Technology


Congressional Insights and Senior Member Upgrade

Information Session Speaker: George Hanover, 2007 IEEE-USA

Congressional Fellow Time: Dinner and networking 6:00 PM, Senior

Member Upgrade Information session at 6:45 PM, Presentation 7:00 PM

Cost: none (food, beverages can be purchased on-site)

Place: Grand Indian Buffet, 1214 Apollo Way, Sunnyvale

RSVP: not required Web: www.ewh.ieee.org/r6/scv/PACE

The IEEE PACE will have the honor of having

George Hanover, 2007 IEEE-USA Congressional Fellow. He addressed innovation and competitiveness issues as a staffer for the Environment, Technology and Standards Subcommittee of the House Science Committee. George also served on the personal staff of Rep. Dana Rohrabacher (R-Calif.), a member of the House Science Committee. George will discuss an Engineer’s perspective on the "Government Process" and the IEEE-USA's involvement in that process.

If you’ve wondered how the legislative process works in Washington, and how IEEE-USA is influencing it, then put this meeting on your calendar.

We will also be having a Senior member

Upgrade Information session prior to the talk. If you’ve been putting off applying for Senior member grade, then bring your resume and we’ll get you going – painlessly!

WEDNESDAY June 11SCV PACE - Professional Activities Committee for Engineers

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