g ü r t a ç y e m i ş c i o ğ l u

l e c t u r e r , r e s e a r c h e r a n d A S I C d e s i g n e n g i n e e r

educa t i o n

gurtac.y@gmail.com / gurtac.yemiscioglu@emu.edu.tr

(+90) (533) 869 00 39 / (+90) (392) 630 1583

1

/gurtacyemiscioglu /gurtach /gurtach /gurtach /gurtac /gurtachy

abou t me

s t u d i e d : Canterbury, UKl i v e : Famagusta, CY

As a young researcher and lecturer, I am passionate about

exploring new ideas, and encourage young people to be more

innovative and creative; this is my first objective in my career to

spend my energy for. As an engineer, I have a clear and logical

mind with a practical approach to a problem solving. I am eager to

learn and be a creative, adaptable individual with an excellent eye

for detail. I have a 6 years part-time teaching and 1 year industrial

experience.

Born

1986

KösçklüçiftlikNicosia, CY

Primary school1992-1997

GeliboluNicosia, CY

Secondary and high school1997-2003

EMCFamagusta, CY

PhD in Electronics Engineering2009-2015

University of KentCanterbury, UK

BEng (Hons) Computer Systems Engineering with a year in industry2004-2009

University of KentCanterbury, UK

in t e re s t sadiabatic logic techniques

& reversible logic

low-power VLSI design

& low-power computing,

full-custom ASIC designFPGAs, VHDL & Verilog

logarithmic signal processors

quantum cellular automata

2

Thesis title

Supervisor

Abstract

Outcome

Research interests

Research plans

Graduated

Modules

PhD in Electronics Engineering

VLSI Implementation of Low-Power Arithmetic Circuits Based on Adiabatic Logic and Logarithmic Signal Processing.”

Dr. Peter Lee

Thesis describes the design and implementation of a new ultra-low-power digital signal processor, built using a combination of hybrid logarithmic arithmetic and adiabatic logic circuit techniques.

First chip tape-out: 16-bit Clocked Adiabatic Logic Logarithmic Signal Processor. A synopsis of the work undertaken is attached.

Build on the foundations of my PhD to further investigate the fundamental properties of reversible computing and adiabatic logic with beyond CMOS techniques such as quantum cellular automata to build ultra-low-power signal processors.

Beng (Hons) Computer Systems Engineering with a year in industry

First Class Honours

Ÿ digital system realisationŸ digital implementationŸ embedded computer systemsŸ digital signal processingŸ microcomputer engineeringŸ digital control

English College

7 IGCSE

Mathematics, Physics, Chemistry, Computing, Biology, English and French

Exams

Modules

low-power computing

ASIC design

adiabatic logic & reversible logic

QCA

educa t i o n

work

3

Eastern Mediterranean University10/2015 - Present

University of Kent09/2009 - 04/2014

University of Bedfordshire03/2014 - 04/2014

University of Kent05/2013 - 06/2014

teaching

part-time lecturerTeaching first year modules, -Introduction to Logic Design (EENG115)-Introduction to Computers (ITEC115) -Computing for Education (BOTE112)

part-time lab demonstratorWorked in the teaching labs to supervise practical and help undergraduate and postgraduate students on their lab sessions to understand and relate theoretical knowledge with practical. Specialised on embedded systems subjects such as VHDL using Xilinx tools and Modelsim, microC using micrium, PIC microcontrollers using MPLAB IDE, MATLAB and research skills.

visiting lecturerTaught microprocessor architecture and embedded hardware to master levels and computer hardware to first years.

invigilatorWorked in a team to organise the exam hall before and after exams. Setting up stationaries, delivering exam scripts and also responsible during the exam, patrolling in the hall to deal with the queries.

industry

electronic engineerSetting up home automation electronics for flats, houses and work places. Designing customer scenarios to provide more comfort at their living and working environment.

software engineerWorked as intern in a software team to design and implement embedded code for demodulator and tuners, tested software produced for customers and performed WHQL tests for windows drivers. Demonstrated latest products to other internal groups.

other

part-time sales representativeSelling and renting properties. Responsible from customer database and social media adverts.

sales representative and social media coordinatorDealt with customer enquiries, sold and rented properties. Prepared social media and advertisement contents. Organised tasks to increase the demand and reach to other countries.

book designerSummer job in an English school in Japan. Designed educational books for children using adobe illustrator. Experience the Japan culture.

computer technicianWorked in a team and dealt with general computer hardware and software problems around the university.

Dogankent Construction Ltd. 01/2016 - Present

Intel Corporation UK Ltd. 07/2007 - 08/2008

Turyap Estate Agency04/2015 - Present

Erbatu Estate and Construction10/2014 - 01/2015

Formula 1 English School06/2005 - 07/2005

Eastern Mediterranean University09/2003 - 06/2004

2009-2010 2010-2013 2010-2014

Graduate studentrepresentative of

ICES Group

2010-2014

Student Ambassador

2012-2014

Social Network Coordinator

Event organiserof Turkish

Cypriot Society

President of Turkish

Cypriot Society

vo lu n t e e r

compu t ing s k i ll s

t eaching s k i ll s

Lecture Preparation Supervision Time management Research methodologies Problem solving

Project management Team management Analytical thinking

4

RTL and CAD design tools:

Tanner Tools Pro Xilinx ISEModelsimMPLAB IDEMATLAB

Other Applications:

Microsoft Office Suite E-mail packages Corel Draw

Programming Languages:

VHDL Verilog Embedded C Visual C++ Latex

Operating Systems:

Project managementMultitasking Communication

gene ra l s k i ll s

ENGLISHadvance level

TURKISHmother language

In dep enden t

Rea li s t i c

Se l f -mo t i va t ed

Cre a t i v e

5

award s

School Research Award

University of Kent

Divisional Recognition Award

Intel Corporation

Outstanding Contribution Award

Intel Corporation

s oc i a l

refe rence sAvailable on request.

6

append i x

ith advances in CMOS IC technology, more and more functionalities are being integrated on chips

Wwith ever increasing computational power and performance. However, an unwanted consequence of these advances has been that the power consumption has now become a critical concern in both high-

performance and portable devices. Concerns about power consumption have developed an interest in low-power computing techniques.

Generally most of these techniques have been implemented based on a conventional CMOS principle, where the energy taken from the supply is all dissipated to the ground at each transition. Adiabatic logic, which is also known as energy-recovery or charge recovery logic is an attractive alternative to conventional CMOS. Adiabatic logic circuits are powered with a time-varying power source and they operate based on slowly charging the output nodes while keeping the average current small to reduce the energy dissipated by the

2 resistive heating of components and by allowing charge recovery during discharge without dissipating 1/2 CV of energy to ground.

This thesis describes the design and implementation of a new ultra-low-power digital signal processor, built using a combination of hybrid logarithmic arithmetic and adiabatic logic circuit techniques. The circuit has been designed and fabricated using a 0.35 m AMS CMOS process. The 16-bit processor uses the Mitchell algorithm μ

2for conversion to and from the log domain and has an active area of 0.57 mm . Simulation and experimental test results show that it consumes approximately 12.3 mW when operating at frequency of 100MHz. This indicates a reduction of 89.5% in power when compared with CMOS circuits implemented using the same process. The circuits have been designed using a Clocked Adiabatic Logic (CAL) topology and a new library of full custom cells has been developed.

pu b li ca t i o n s

deta i l e d s y no p s i s of PhD

article in peer-reviewed journal IET Computers and Digital Technigues (SCI Expanded)

2015

international peer-reviewed conference

international peer-reviewed conference 8th Ph.D. Research in Microelectronics and

Electronics (PRIME).Aachen, DE

2012

55th IEEE International Midwest Symposium on

Circuits and Systems (MWSCAS).

Boise, US 2012

G. Yemiscioglu and P. Lee. “Very-Large-Scale Integration Implementation of a 16-bit Clocked Adiabatic Logic (CAL) Logarithmic Signal Processor."

G. Yemiscioglu and P . Le e .“16-Bit Clocked Adiabatic Logic ( CAL ) Lo g a r i t h mi c S i g n a l Processor."

G. Yemiscioglu and P . Le e .“16-Bit Clocked Adiabatic Logic (CAL) Leading One Detector for a Logarithmic Signal Processor."

rd3 School Research Conference

Canterbury, UK2014

local peer-reviewed conference

local peer-reviewed conference nd

2 School Research Conference

Canterbury, UK2012

local peer-reviewed conference st1 School Research Conference

Medway, UK2010

p re sen ta t i o n s

7

University of Kent, Canterbury, UK

2016

th4 School Research Conference

Poster presentation of completed project.

th3 School Research Conference

Poster presentation of results..

University of Kent, Canterbury, UK

2014

Boise, US2012

th55 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)Talk given to describe the complete processor.

Boise, US2012

th8 Ph.D. Research in Microelectronics and Electronics (PRIME).

Talk given to describe the leading-one detector.

nd2 School Research Conference

Talk given to describe the progress of our research.

University of Kent, Canterbury, UK

2012

ICES Group Seminar

Talk given to describe our approach and findings.

University of Kent, Canterbury, UK

2011

University of Kent, Canterbury, UK

2010

ICES Group Seminar

Talk given to present our investigations

University of Kent, Canterbury, UK

2010

st1 School Research Conference

Poster Presentation of project proposal

G. Yemiscioglu and P. Lee. “VLSI Implementation of 16-bit Clocked Adiabatic Logic (CAL) Logarithmic Signal Processor.”

G. Yemiscioglu and P. Lee.“Investigation of adiabatic logic circuits for very low-power logic design.”

G. Yemiscioglu and P. Lee.“Investigation of adiabatic logic circuits for very low-power logic design.”

8

con t r i b u t i o n s

Design and Implementation of Clocked Adiabatic Logic (CAL) Leading-One Detector (LOD) based on modular approach.

Design and Implementation of Clocked Adiabatic Logic (CAL) Lin2Log and Log2Lin conversion algorithms based on the Mitchell algorithm.

Comprehens ive inves t igat ion of the evolution of adiabatic logic .

Design of full-custom Clocked Adiabatic Logic (CAL) libraries .

Design and Implementation of ultra-low-power 16-bit Clocked Adiabatic Logic

Logarithmic Signal Processor (CAL-LOG-SP) .

16-bit Clocked Adiabatic Logic Logarithmic Signal Processor

CAL-LOG-SP chip tape-out .

Working prototype of CAL-LOG-SP chip.