handout.std.cell.design

8/11/2019 Handout.std.Cell.design

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An overview of standard cellbased digital VLSI design

Implementation of the first generation AsAPprocessor

Zhiyi Yu and Tinoosh Mohsenin

VCL Laboratory

UC Davis


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Outline

Overview of standard cell-based design

Overview of AsAP Implementation of the first generationAsAP


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Standard cell based ICvs. Custom design IC

Standard cell based IC: Design using standard cells

Standard cells come from library provider

Many different choices for cell size, delay, leakagepower

Many EDA tools to automate this flow

Shorter design time

Custom design IC: Design all by yourself

Higher performance


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Standard cell based VLSIdesign flow

Front end System specification and architecture

HDL coding & behavioral simulation

Synthesis & gate level simulation

Back end Placement and routing

DRC (Design Rule Check), LVS (Layout vsSchematic)

dynamic simulation and static analysis


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Outline

Overview of standard cell-based design

Overview of AsAP

Implementation of the first generationAsAP


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AsAP(Asynchronous Array of Simple Processors)

A processing chip containing multipleuniform simple processor elements

Each processor has its local clockgenerator

Each processor can communicate with

its neighbor processors using dual-clockFIFOs


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Diagram of a 3x3 AsAP

More information: http://www.ece.ucdavis.edu/vcl/asap/

Inst

Mem

ALU

MACControl

Data

Mem

Clock

In-

FIFO0

In-

FIFO1

Output


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Outline

Overview of standard cell-based design Overview of AsAP

Implementation of the firstgeneration AsAP


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Simple diagram of the front-end design flow

SystemSpecification

RTLCoding

Synthesis Gate level code

INV (.in (a), .out (a_inv));AND (.in1 (a_inv), .in2 (b), .out (c));Ex: c = !a & b


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Simple diagram of the back-end design flow

gate level Verilogfrom synthesis

Place&

Route

Final layout

(go for fabrication)

DRC

Gate level Verilog

LVS

Timing information

Gate level dynamic and/or static analysis

Design rulecheck

Layout vs.

schematic


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Back-end design of AsAP

Technology: TSMC 0.18 m CMOS Standard cell library: Artisan

Tools Synthesis: Synopsis Design compiler

Placement & Route: Cadence Encounter

DRC & LVS: Calibre Static timing analysis: Primetime


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Flow of placement and routing

Import needed files Floorplan

Placement & in-place optimization Clock tree generation

Routing


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Import needed files

Gate level verilog (.v) Geometry information (.lef)

Timing information (.lib)

INV (.in (a), .out (a_inv));

AND (.in1 (a_inv), .in2 (b), .out (c));

INV: 1um width AND: 2 um width

INV: 1ns delay; AND: 2 ns delay

INV AND

a

b

C

Delay (a->c): 1ns + 2ns = 3ns


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Floorplan

Size of chip Location of Pins

Location of main blocks

Power supply: give enough power for each gate

VDD (Metal)

Power supply (1.8V)

currentGate 1 Gate 2 Gate 3 Gate 4

1.75v

Voltage drop equation: V2 = V1 I * R

1.7v(need another power)

1.65v

VSS


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Floorplan of a single processor

Inst

Mem

Clock InFIFO0

Data Mem

ALU

MAC

Control

InFIFO0


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Placement &in-placement optimization

Placement: place the gates In-placement optimization

Why: timing information differencebetween synthesis and layout (wire delay)

How: change gate size, insert buffers

Should not change the circuit function!!


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Placement of a single processor


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Clock tree

Main parameters: skew, delay, transition time


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Clock tree of single processor


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Metal Layer Topology

Routing


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Layout of a single processor

Area:0.8mm x 0.8mm

Estimated speed:

450 MHz


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Layout of the first generation 6x6 AsAP

One processor

Area: 30 mm^2in 180 nm CMOS36 processors114 PADs


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Verification after layout

DRC (design rule check) LVS (layout vs. schematic)

.GDS vs. (verilog + spice module)

Gate level verilog dynamic simulation

Mainly check the function

Different with synthesis result


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Useful tools

Dynamic Simulation: Modelsim (Mentor), NC-verilog (Cadence), Active-HDL Synthesis:

Design-compiler, design-analyzer (Synopsys)

Placement & Routing Encounter & icfb (Cadence) Astro (Synopsys)

DRC & LVS Calibre (Mentor) Dracula (Cadence)

Static Analysis Primetime (Synsopsys)

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