hb_pj_02.doc

Handy Board Operations

Accessing the Data Bus

Pete Jackson(Senior Electrical Engineering)

December 5, 1997

2

Executive Summary

The Handy Board (HB) was developed by the Media Laboratory at the Massachusetts Institute ofTechnology. The Handy Board is based on the 52-pin Motorola MC68HC11 processor, andincludes 32K of battery-backed static RAM, four outputs for DC motors, a connector system thatallows active sensors to be individually plugged into the board, an LCD screen, and anintegrated, rechargeable battery pack. Additionally, the Handy Board is compatible withInteractive C, the programming environment created for the MIT LEGO Robot Design project.Interactive C (IC) is a multi-tasking, C language based compiler that includes a user commandline for dynamic expression implementation. The HB is the latest in a series of boards releasedunder MIT’s free licensing policy, in which the printed circuit board artwork, schematics, anddriver software may be freely licensed for personal, educational, and commercial use. The HBmay be purchased fully assembled or in kit form from several vendors. Information on the HBand links to vendors may be found on the World Wide Web at:• http://lcs.www.media.mit.edu/groups/el/Projects/handy-board/

Michigan State University is evaluating the HB for use in electrical engineering classes thataddress microprocessor architecture, bus interfacing, data transfer, interrupt structure,analog/digital interfacing, and the general application of embedded microcontrollers.

This document provides detailed information about interfacing with the HB’s eight bit data bus.The purpose is to allow students with basic electrical engineering studies to implement a datainterface with the Handy Board.

This demonstration consists of three hardware devices and a software component. Each of thehardware devices the HB, a proto-board, and the Switch Register Box (SRB) are fully describedin subsections of this document. A software subsection provides an overview of IC and theprogram code and procedures required for the interface.

The purpose of this demonstration is to provide an external 8-bit, bi-directional data busconnection to the HB’s data bus.

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Table of Contents

SYSTEM-LEVEL DESCRIPTION ..................................................................................................................... 4HB Microcontroller ............................................................................................................................................ 4SRB (User I/O) .................................................................................................................................................. 4Glue Logic (Proto-board interface) ..................................................................................................................... 5

• HB TO PROTO-BOARD BUS (I/O BUS #1) ............................................................................................ 5• SRB TO PROTO-BOARD BUS (I/O BUS #2)........................................................................................... 6

System Behavior ................................................................................................................................................ 6

A CLOSER LOOK AT THE HANDY BOARD.................................................................................................. 7Features Common To The HB ............................................................................................................................ 7Handy Board Physical Layout............................................................................................................................. 8Configuring The HB For Use............................................................................................................................ 10HB Memory ..................................................................................................................................................... 10The HB Data Bus ............................................................................................................................................. 11The HB Expansion Bus .................................................................................................................................... 11

I/O BUSES.......................................................................................................................................................... 13I/O Bus #1........................................................................................................................................................ 13

• PART ONE ........................................................................................................................................... 13• PART TWO........................................................................................................................................... 13

I/O Bus #2........................................................................................................................................................ 14

PHYSICAL SETUP ........................................................................................................................................... 14HB Setup ......................................................................................................................................................... 14Proto-Board Setup............................................................................................................................................ 15

INTERACTIVE C (IC)...................................................................................................................................... 17General Description.......................................................................................................................................... 17Running IC ...................................................................................................................................................... 17

SOFTWARE ...................................................................................................................................................... 19Program Code .................................................................................................................................................. 19

SUMMARY........................................................................................................................................................ 20

APPENDIX......................................................................................................................................................... 21DM74AS374 Octal D-Type Edge-Triggered Flip-Flop with TRI-STATE Ouputs .............................................. 21

List of Figures

Figure 1: System Level Schematic......................................................................................................................... 4Figure 2: Latched Data Flow ................................................................................................................................. 5Figure 3: Labeled Handy Board Diagram............................................................................................................... 8Figure 4: CPU and Memory Circuit ..................................................................................................................... 12Figure 5: Interface Schematic .............................................................................................................................. 15Figure 6: HB Header Pin-outs.............................................................................................................................. 16Figure 7: IC Initialization Screen Shot ................................................................................................................. 18Figure 8: Loading User Program Screen Shot....................................................................................................... 18Figure 9: Running Simple Interactive Command.................................................................................................. 19

List of Tables

Table 1: HB Memory Map ................................................................................................................................... 10Table 2: Decoder Operation.................................................................................................................................. 11Table 3: DM74374 Truth Table ............................................................................................................................ 13

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System-Level Description

The purpose of this demonstration is to provide an external 8-bit, bi-directional data busconnection to the HB. This section describes operation at the system-level, which is comprised ofthree main components connected by two busses.

Figure 1: System Level Schematic

HB Microcontroller

The goal of this demonstration is to read and write single byte data on the HB’s data bus. Thereis only one connection on the HB where access to the entire byte of the data bus is readilyavailable. This access is through the LCD header (see Figure 4). The HB looks for a functioningLCD upon start-up. Therefore, the LCD must be relocated to the proto-board. The relocationof the LCD is discussed in the HB Setup section.

SRB (User I/O)

The Switch Register Box (SRB) is a hardware device which contains an array of eight LED’s,two 7-segment displays, eight digital outputs (two position switches), and various clock signals.

The array of LED’s are used in this demonstration to display a representation of the latched datafrom the HB’s data bus. Each LED lights when a 5V signal is received from I/O bus #2. One ofthe 7-segment displays also provides a representation of this data by converting the entire 8-bits,present at the LED array, into its hexadecimal equivalent and displaying that value. Both theLED array and the 7-segement displays are generated from the same 8-pins on the SRB header.The eight digital output switches are used to generate the individual bits of the single byte of datathat is latched onto the HB data bus. Each switch provides a 0V signal in one position and a 5Vsignal in its other position. The second 7-segment display provides the hexadecimal equivalentof the byte generated by the positions of the digital output switches.

HB Microcontroller

Proto-boardInterface

SRB

8 8

I/O Bus

#1

I/O Bus#2Glue Logic

User I/OHB

5

Glue Logic (Proto-board interface)

The proto-board is the hardware interface between the HB and the SRB. For this demonstration,it consists of two DM74AS374 Tri-State Octal Latch IC’s and two male headers for connectionsto the HB and to the SRB. The data sheets for these latches may be obtained from NationalSemiconductors web site at : http://www.national.com

Figure 2: Latched Data Flow

Described fully, in the HB Expansion Bus section, software generated control signals latch dataonto and off of both I/O buses #1 and #2. These signals control each latch’s output control (OC)and clock (CLK) pins.

• HB to proto-board bus (I/O bus #1)

The purpose of I/O bus #1 is to transfer data to and from the HB. Data is latched onto the proto-board by a single latch (latch-1) connected to the HB by a 16-pin cable. Data is latched onto theHB by a second latch (latch-2) also utilizing the 16-pin cable.

This cable provides the physical path for I/O between the HB and the proto-board. The cablealso supplies six control signals, power and ground, and the eight data bits of the data bus to theLCD. This cable also supplies the two control signals for operation of the latches. The controlsignals for the LCD are transparent to the user, while the control signals for the operation of thelatches are software driven created by the users program code.

I/O #1 bus is significantly different from I/O bus #2, because the 8-data bits flowing between theHB and the proto-board, whether as input or output, use the same eight paths on the cable. OnI/O bus #2, there must exist separate paths for the SRB’s LED’s connection and the SRB’s dataout connection.

Latch-1

Latch-2

Data infrom HB1D..8D

Data outto HB

1Q..8Q

Data infrom SRB

1D..8D

Data outto SRB1Q..8Q

I/O Bus#1

I/O Bus#2

CLK

CLK

7437

474

374

OC

OC

8 8

88

Vcc

GND

GND

Vcc

Pin-out for DM74374 Tri-State Octal LatchesPin # Pin #1- output control (OC) 20- VCC2- data out (1Q) 19- data out (8Q)3- data in (1D) 18- data in (8D)4- data in (2D) 17- data in (7D)5- data out (2Q) 16- data out (7Q)6- data out (3Q) 15- data out (6Q)7- data in (3D) 14- data in (6D)8- data in (4D) 13- data in (5D)9- data out (4Q) 12- data out (5Q)10- ground (GND) 11- clock (CLK)

Pins 1-10 are from top to bottom on the left side of the IC.Pins 20-11 are from top to bottom on the right side of the IC.

Notes: The output control is a Tri-State design. The clock is Positive edge-triggered.

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• SRB to proto-board bus (I/O bus #2)

The purpose of I/O bus #2 is to transfer data between the SRB and the proto-board. For thisdemonstration, the SRB requires one byte of data from the HB to operate its LED’s. This data islatched from I/O bus #1 and flows to the SRB through 8-pins of a 16-pin cable. The additional8-pins on this cable provide a path for the SRB’s data output to the proto-board. The SRB’sdata output is latched from I/O bus #2 and is provided to I/O bus #1.

System Behavior

Software reads and writes to specific address ranges enable pins on the HB’s expansion bus(which is connected to the proto-board), thus latching data onto or off of the HB’s data bus. Forthis demonstration, a simple looping program was written in C to continually perform these readsand writes.

After the program has been started it continually samples (reads) data on the HB’s data bus,stores the data to memory, and then writes the stored data back to the HB’s data bus. During thisprocess, the program enables the transfer of data from the HB’s memory to the SRB’s bank ofLED’s, and enables the flow of data from the SRB onto the HB’s data bus to be read and stored.

This continuous read/write cycle allows the user to select the position of any or all of the eightdigital switches on the SRB and see the results displayed on the SRB’s LED’s and 7-segmentdisplay.

7

A Closer Look At The Handy Board

Features Common To The HB

• Microprocessor. The 68HC11A1FN (6811) with 256 bytes internal RAM, timer/counter &analog-to-digital subsystems. Systems clock runs at 2MZ.

• Memory. 32K bytes of static RAM. Battery protected so that memory retains data evenwhen board power is switched off. Memory is mapped to the upper half of the 6811’s 64Kaddress space.

• Addressing. Lower half of memory is decoded to provide signals for four digital outputlatches and four digital input latches. One of each of these is present on the HB, and theother six select signals are made available on an Expansion Bus.

• Display. 16x2 character-based LCD display, with printf() function for displaying messagesand dynamic data. Two user push-buttons and one knob allows manual input for menunavigation; piezo beeper for audio output.

• Battery. Integral 9.6V rechargeable battery pack (8 AA nickel cadmium cells with 600 mAcapacity). Two battery charging options are provided: a trickle-charge on the HB itself and aswitchable trickle-charge/zap charge mode on the serial interface board

• Motor Outputs. The digital output latch drives two TI H-bridge motor driver chips,providing outputs for four bidirectionally controllable DC motors. Each motor output cansupply 1 ampere of current at 9.6V.

• Sensor Inputs. Sixteen sensor headers (9 digital, 7 analog). Each sensor header providespolarized 3-wire connection (+5V, ground, and signal). Three of the digital inputs connect tothe built-in 6811 timer hardware. The analog inputs connect to the 6811’s built-in A/Dsubsystem, providing an 8-bit conversion each 17 microseconds.

• Infrared Subsystem. Integral Sharp infrared decoder receives signals from householdTV/VCR remotes; built-in 40KHz modulator and drive transistor allows easy attachment ofIR LED’s to broadcast such signals. Supplied software allows decoding of Sony infraredprotocol; other manufactures’ formats available.

• Interactive C. Multi-tasking, C-based development system. Compile and downloadprograms from MS-DOS, Macintosh, or Unix host computers. Features include standard Ccontrol statements (if, else, for, while, break, continue) and data types (16- and 32-bitintegers, floating point numbers, characters, strings, and one-dimensional arrays).

• Driver Software. Software available for a variety of devices, including shaft encoders,Polaroid ultrasonic ranging devices, and servo motors.

8

Handy Board Physical Layout

Figure 3: Labeled Handy Board Diagram

1- Power Switch. The power switch is used to turn the HB on and off. The HB retains thecontents of its memory even when the board is switched off.

2- Computer Connector. Via this RJ11 connector, the HB attaches to a desktop computer(using the separate Interface/Charger Board).

3- 4 DC Motor Outputs and Indicators. The HB’s four motor outputs are located at thissingle 12-pin connector. Each motor output consists of three pins; the motor connects to theouter two pins and the center pin is not used. Red and green LED’s indicate motor direction.From top to bottom, the motor outputs are numbered 0 to 3.

4- Start Button. The Start button is used to control the execution of Interactive C programs.Also, its state may be read under user program control.

5- Stop Button. The Stop button is used to put the HB into a special bootstrap download mode.Also, its state may be read under user program control.

(17) LCD screen

(6) low batteryindicator

(5) “Stop”button

(4) “Startbutton

(18) piezobeeper

(7) power/readyindicator

(8)9 digitalinputs

(9)7 analog

inputs

(11)IR inputsensor(10)

IR outputand

indicator

ON

(14) batterytrickle-charge

connector

(16) SPIexpansion

header

OFF

(13) userknob

(12) analogexpansion

header

(1) powerswitch

(2) computerconnector

(3) 4 DCmotor outputs

andindicators

(15) chargeindicator

(19) powerexpansion

header

9

6- Low Battery Indicator. The red Low Battery LED lights when for a brief interval each timethe HB is switched on. If this LED is on steadily, it indicates that the battery is low and thatthe CPU is halted.

7- Power/Ready Indicator. The green Power/Ready LED lights when the HB is in normaloperation, and flashes when the HB is transmitting serial data. If the board is powered on andthis LED is off, then the HB is in special bootstrap mode.

8- Digital Inputs (9). The bank of digital input ports is here. From right to left, the digitalinputs are numbered 7 to 15.

9- Analog Inputs (7). The bank of analog input ports is here. From right to left, the analoginputs are numbered 0 to6.

10- IR Output and Indicator. The infrared output port is here. The red indicator LED lightswhen the output is enabled.

11- IR Input Sensor. The dark green-colored infrared sensor is here.

12- Analog Expansion Header. The analog expansion header is a 1x4 connector row locatedabove analog inputs 0 to 3.

13- User Knob. The user knob is a trimmer potentiometer whose value can be read under userprogram control.

14- Battery Trickle-Charge Connector. The battery charge connector is a coaxial power jackcapable of accepting a 12V signal for trickle-charging the HB’s internal battery.

15- Charge Indicator. The yellow charge indicator LED lights when the HB is charging via thecoaxial power jack.

16- SPI Expansion Header. The SPI expansion header is a 2x4 pin jack that allows connectionwith the 6811’s serial peripheral interface circuit. See the CPU and memory schematicdiagram for a pin-out of this connector.

17- LCD Screen. The HB is provided with a 16x2 LCD screen which can display data underuser control.

18- Piezo Beeper. The HB has a simple piezo beeper for generating tones under user control.

19- Power Expansion Header. The power expansion header is a 1x4 pin jack that providesaccess to the unregulated motor power and ground signals.

10

Configuring The HB For Use

The HB, as any other microcontroller board, requires the programmer to download theirprograms Motorola hex file (also called an S19 record) into the HB memory. This hex file iscreated when an assembly code program is assembled. For the HB to run IC (the ability to run Cprograms interactively), a program named “pcode_hb.s19” must be downloaded into memory.The downloader must also modify the CONFIG register, initializing the 6811’s memory map(see table 1). This configuring of the CONFIG register is automatic for the Handy Boarddownloader (hbdl) shipped with the HB. Hbdl is specifically written for MS Windows, howeverthere are other downloaders available for use with Macintosh and Unix host computers.

To use the downloader, run the hbdl.exe application and select “pcode_hb.s19”. Also verify thatthe text box for the CONFIG register has the value “0c” to properly configure the memory map.

HB Memory

The HB has 32K of on board RAM which is external to its CPU, the 6811. This causes onepeculiarity that requires attention before writing program code that contains interrupt vectors.The HB operates in a special mode. This special mode allows the 6811 to switch betweenexpanded mode operation (the mode in which the external RAM is active) and single-chip mode.The HB uses the single-chip mode to communicate with the LCD. This causes the 6811’sinterrupt vector bank to be located at $bfc0 to $bfff rather than the normal area of $ffc0 to $ffff.

Device Location Notes68HC11 internalRAM

$0000-$00ff(A1 chip)

Built-in. Because of varying internal RAM with differentchips this area may extend out to $01ff.

68HC11 controlregisters

$1000-$103f Built-in

Expansion I/OBank 0

$4000-$4fff Memory reads in this range enable the Y1 latch selector,present on the HB expansion bus. Memory writes in this rangeenable the Y0 latch selector, present on the HB expansion bus.

Expansion I/OBank 1

$5000-$5fff Reads enable Y3; writes enable Y2. See explanation above.

Expansion I/OBank 2

$6000-$6fff Reads enable Y5; writes enable Y4. See explanation above.

Digital inputs $7000-$7fff The digital inputs consist of the two switches and sensor ports10 through 15. A memory read from this range returns thevalue of the digital input byte.

Motor outputs $7000-$7fff A memory write to this range controls the motor outputs. Thelow four bits are motor direction, and the high four bits aremotor enable (1=on).

External RAM $8000-$ffff The 32K of battery-backed memory is mapped to the upper32K block of the 6811 address space.

Table 1: HB Memory Map

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The HB Data Bus

The HB’s 8-bit data bus has three primary functions: Interfacing with the LCD and the twomotor controllers, and bussing in data from the digital input header on the HB. Port C on the6811 is used for the data bus connection to the 6811. The HB allows external devices tocommunicate with it. The HB incorporates an expansion bus to select which external devices areactive on the data bus by enabling latch selects. For this demonstration, the expansion bus willprovide control signals for two latches on the proto-board, latching data onto and off of the databus.

The HB Expansion Bus

The expansion bus uses a memory mapped I/O scheme. There are a total of eight latch selectpins (Y0-Y7) available to control devices connected to the HB’s data bus, one of these are usedby the output motor selection and another is used by digital input from the HB’s digital inputheader. The other latch select pins are available for use on the expansion bus. The 74HC138 IClabeled U6 (see figure 4, CPU and Memory Circuit) is an 8-3 decoder. The outputs of thisdecoder are the eight latch select bits Y0-Y7. The operation of this decoder is shown in table 2below.

A13 A12 R/W' Address Range I/O Latch selector0 0 0 $4000-$4FFF O Y0- enabled by a write0 0 1 $4000-$4FFF I Y1- enabled by a read0 1 0 $5000-$5FFF O Y2- enabled by a write0 1 1 $5000-$5FFF I Y3- enabled by a read1 0 0 $6000-$6FFF 0 Y4- enabled by a write1 0 1 $6000-$6FFF I Y5- enabled by a read1 1 0 $7000-$7FFF O Y6- in use by digital input1 1 1 $7000-$7FFF I Y7- in use by motors

Address bits A13, A12 and the R/W bit are used as inputs in the 8-3 decoder.The outputs of the decoder are latch select bits Y0-Y7.

Table 2: Decoder Operation

The scheme is to read or write to one of the address ranges which then generates the appropriatesignals on A13, A12, and R/W'. These signals are then decoded and a signal is directed to one ofthe 8 latch select pins. For this demonstration Y0 and Y1 were chosen to be the latch selectorpins.

12

Figure 4: CPU and Memory Circuit

13

I/O Buses

Data on I/O buses #1 and #2 are controlled by the use of two Dm74374 latches characterized bythe following truth table.

Output Control Clock D Output (Qn+1)L á H HL á L LL L X Qn

H X X Z

Table 3: DM74374 Truth Table

I/O Bus #1

Because I/O buses #1 and #2 terminate at the same latches, their physical and logical structuresare best described in two parts. For I/O bus #1, part one describes the flow of data from theHB’s data bus to the output of first latch (this output is then directed to the SRB’s LED’s), whilepart two describes the data flow from the input of the second latch (this input is from the SRB’sdata output) to the HB’s data bus.

• Part oneWhen a write statement to the address range $4000-$4fff is encountered in program code, asignal is generated on pin Y0 of the expansion header which is connected to latch-1’s clockpin. Y0 is normally in a high state and the write statement drives it low for several clockcycles. On the rising edge of this signal (Y0), the data is latched into latch-1’s D-type flip-flops. With the data held in the latch, the output control pin must be driven low to releasethis data from the output gates of latch-1 to the SRB’s LED’s. Because the output of thislatch drives only the SRB’s LED’s, and we desire the LED’s to continually display the mostrecently latched data, the output control pin is not driven low but is grounded to the proto-board.

• Part twoSimilarly, when a read statement to the address range $4000-$4fff is encountered in programcode, a signal is generated on pin Y1 of the expansion header which is connected to both theclock and output control pins of latch-2. Y1 is normally in a high state and the readstatement drives it low for several clock cycles. On the rising edge of this signal (Y1), thedata from the SRB is latched into latch-2’s D-type flip-flops. Because the output of this latchis connected to the HB’s data bus it cannot remain in a constant output state as is the case forlatch-1. Therefore, the control signal on (Y1) also puts the output gates of latch-2 back intoa high impedance state (Z) as it returns to a high state.

Qn+1 = Next OutputQn = Present OutputZ = High ImpedanceH = True (5V)L = False (0V)X = Don’t Care

14

As explained above, the rising edge of Y1 triggers the latching of data from the SRB, yet theoutput control releases the data to the HB’s data bus as soon as Y1 goes low. Therefore, thedata being released to the HB’s data bus is one latching cycle behind the most recent data.This could easily be remedied through hardware or software. However, this latching cycle isless than 50µs which is much faster than the data can actually change coming from theSRB’s digital data output switches.

I/O Bus #2

The characterization of the latching process from the HB’s data bus to the output of the latch-1and the latching of the data from the SRB’s data output at latch-2’s input to the HB’s data buswas described above. Data bus #2 is simply the physical conduit for the transfer of data betweenthe proto-board and the SRB. The actual connection from the proto-board to the SRB isdescribed in the proto-board setup section.

Physical SetupHB Setup

To gain access to the data and control pins of the LCD header on the HB, a 16-pin cable must beused. Unfortunately, most cables provide female connections on each end, which creates aproblem with the HB header connections. Specifically, the HB’s LCD header, as well as all theheaders on the HB, is a female header. Eight of these pins are data bus connections and theadditional six pins are used for control of the LCD. The proto-board uses standard male headers.Any size header may be used. For this demonstration (because of availability), a 34-pin headeris used and the extra eighteen pins are simply not connected. A cable with standard femaleconnectors on each end can be used by inserting pins into one end of the cable, thus enabling amale configuration on one end of the cable. For this demonstration, the sixteen pins inserted intothe cables end were extracted from a spare header. This male end of the cable is then connectedto the female LCD header on the HB, and the female end of the cable is connected to the maleheader on the proto-board.

As discussed earlier, the LCD must be present upon start-up of the HB. Therefore, the LCDmust be relocated. The LCD detaches as a self contained unit form the HB, and its row offourteen pins can be plugged directly into the proto-board. Then all that is required to operatethe LCD on the proto-board is to route each of the 14-pins from the proto-board header to therelocated LCD.

Two of these 14-pins are power and ground from the HB. For this demonstration, the power pin(5V) supplied power to the LCD only, while the ground pin (0V) supplied a common groundbetween the HB and the proto-board. Because the SRB and the latches on the proto-board alsorequire a 5V power source, and the HB could not supply enough power to operate the SRB, anadditional power supply is connected to the proto-board and the SRB. The proto-boards powerand ground terminals should also be connected to this power supply to provide power for theproto-board and a common ground to all components. However, do not connect the HB’s powerpin, at the HB to proto-board header, to the additional power supply.

15

Proto-Board Setup

The header connection for the HB to proto-board was explained above. The only other headerconnection on the proto-board is the proto-board to SRB header. Fortunately, the SRB cable is astandard 34-pin female cable that will plug directly into a standard 34-pin header. For thisdemonstration, sixteen pins on the proto-board to SRB header must be used. Eight of these pinsdrive the LED’s and one 7-segment display and the other eight pins except the eight data outputsfrom the SRB. See figure 3 for the pin-out of the SRB cable.

The proto-board also supplies power to the latches. Route power from the proto-boards powerterminal to the power pin (Vcc) of each latch. Also, route the proto-boards ground terminal to theground pin (GND) of each latch. Figure 3 is the interface schematic and shows all connectionsfor this demonstration.

Figure 5: Interface Schematic

CLK

246810121416182022242628303234

13579111315171921232527293133Y0

Y1Y2Y3Y4Y5Toc3ASA15MemPwr

GND+5VVRA9A8Toc4D0D1D2D3D4D4D6D7

(proto-board)

GND

VccLatch-1

GND

VccLatch-2

SRBHeader

SRB LED’s0-7

SRBSwitches0-7

CLK

<

<

D0-D7

OC

8

8

8

8

8

8

8

6

OC(Han

dy B

oard

)LC

D H

eade

rEx

pans

ion

Hea

der

74374

74374

LCD

Rel

ocat

ed fr

om H

B

16

Figure 6: HB Header Pin-outs

↓ LC

D H

eader↓

Expansion

17

Interactive C (IC)

General Description

IC is a C language consisting of a compiler and run-time machine language module. ICimplements a subset of C. This subset includes control structures (for, while, if, else), local andglobal variables, arrays, pointers, structures, 16-bit and 32-bit integers, and 32-bit floating pointnumbers.

IC works by compiling into pseudo-code for a custom stack machine, rather than compilingdirectly into native code for a particular processor. This pseudo-code (p-code) is then interpretedby the run-time machine language program. This unusual approach to compiler design allows ICto offer the following design tradeoffs:

• Error Checking. Interpreted execution that allows run-time error checking.

• Small objective code. Stack machine code tends to be smaller than a native coderepresentation.

• Multi-tasking. Because the pseudo-code is fully stack-based, a process’s state is definedsolely by its stack and its program counter. It is then easy to task-switch simply by loading anew stack pointer and program counter. This task-switching is handled by the run-timemodule, not by the compiler.

Since IC’s ultimate performance is limited by the fact that its output p-code is interpreted, theseadvantages are taken at the expense of raw execution speed.

The concept behind IC is to allow interactive program debugging and testing. Once a workingprogram is written it is downloaded into the HB’s memory, and then the HB may bedisconnected from the host PC. The HB is now in stand-alone operation and may be interfacedwith a device, machine, robot, or for the purpose of this demonstration, the proto-boardinterfacing with the SRB.

Running IC

The HB must be configured as explained in “Configuring the HB for use” before IC may beexecuted from the host PC. This configuring procedure is a one time event as long as the HB’sbattery pack is cable of powering the static ram IC’s on the HB. Assuming that the HB has beenproperly configured, and the proto-board has been supplied power to run the LCD and latches,you simply run the IC executable file from the host PC.

When IC is run it synchronizes with the HB and then downloads various files including Cfunctions that the HB uses to operate its on board devices such as the motor driver IC’s and theLCD. Figure 7 is a screen shot of the host PC after IC has been executed.

18

Welcome to Interactive C v3.1Copyright © 1997 Newton Research Labs. All Rights Reserved.http://www.newton labs.com/icBugs to ic@newtonlabs.com

This IC license is for Windows (Educational/personal license).6- user license for: Michigan State University

Synchronizing with boardPcode version 3.10 present on boardLoading C:\TEMP\pete\IC\libs\lib_hb.lisLoading C:\TEMP\pete\IC\libs\lib_hb.cLoading C:\TEMP\pete\IC\libs\r22_ir.lisLoading C:\TEMP\pete\IC\libs\r22_ir.icbLoading C:\TEMP\pete\IC\libs\lr22_ir.cInitializing interruptsDownloading 1724 bytes (address 8000-86BB) : 1724 loadedDownloading 78 bytes (address 86BC-8709) : 78 loadedDownloading 1724 bytes (address 870A-8719) : 16 loadedCode loaded.IC>

Figure 7: IC Initialization Screen Shot

The final line in figure 7 shows the IC command prompt (IC>). IC is now ready for user input.A user written program must be downloaded to run on the HB. Figure 8 shows the simpleprocedure for downloading and the running a user written program.

IC> load srb_interface.cLoading C:\TEMP\pete\IC\|libs|srb_interface.c.Initializing interruptsDownloading 2436 bytes (address 8000-8983) : 2436 loadedDownloading 78 bytes (address 8984-89D1) : 78 loadedDownloading 16 bytes (address 89D2-89E1) : 16 loadedCode loaded.IC>srb_io();Downloading 6 bytes (addresses C200-C205) : 6 loaded

Figure 8: Loading User Program Screen Shot

The first seven lines of figure 8 show a user written C program being loaded into the HB’smemory. The last two lines of this figure show how a function from a C program is executedsimply by typing the exact syntax of a line of C code. Notice that a semicolon is the last

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character on the command line just as it would be in a C program. In the above example, afunction within srb_interface.c was run. Many other C instructions may be run from thecommand line. Notice in figure 6 that after the function call was made from the command line,the code was downloaded but there was no return to the IC command line. The function was aninfinite loop written for this demonstration and never returns control to IC.

Figure 9 shows a simple C instruction for adding two integers that does return control to IC, andin this example it returns data along with control.

IC> 2+2;Downloading 7 bytes (addresses C200-C206) : 7 loaded<int> 4IC>

Figure 9: Running Simple Interactive Command

Software

Program Code

For this demonstration, the following C program code was used to read and write data onto andoff of the HB’s data bus.

/************************************************************//* srb_interface.c *//* Target: MC68HC11 on a Handy Board *//* by: *//* Pete Jackson *//* Michigan State University *//* jacks234@pilot.msu.edu 11-22-97 *//************************************************************//* This C program reads in data from the SRB and sends it *//* back out, for display, to the SRB's array of LED's. *//************************************************************/

void srb_io(){ int data; /* SRB switches 1-8 */

while(1) /* infinite loop */ { data = peek(16385); /* latch data onto HB data bus */

/* from SRB. */

poke(16385, data); /* latch data from HB data bus *//* to SRB LED's */

}}

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The while(1) expression provides for an infinite data bus monitoring loop. Memory mapping isused by the peek and poke expressions to control the latches via the HB’s expansion bus. Thelatch selector pins Y0 and Y1, are enabled by accessing the memory range $4000-$4FFF. Noticethat the peek and poke expressions use the decimal equivalent of $4000 which is 16385 decimal.

Summary

The purpose of this demonstration was to guide junior level electrical engineering studentsthrough the process of accessing the HB’s data bus. The student should have introductorycourses in digital logic and microprocessor architecture.

This report was written in a “step by step” format. First, a system-level description was providedto give the student an overall view and allow them the opportunity to generalize what materialsand skills would be required to complete the demonstration. Second, an in-depth look at the HBitself, from both a hardware and software perspective, provided all the necessary information tocomplete the demonstration. Third, the software control of latching data onto and off of the I/Obuses was described. Fourth, the actual physical setup was described. Finally, a brief outline ofIC and how it was incorporated in this demonstration was provided. Additionally, screen shotsof actual IC sessions along with the C code for this demonstration were provided.

Included in the format of this report were various tables and schematics provided at key locationsto reduce ambiguity and help the student understand physical components and their connections,system setup, and software use.

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Appendix

DM74AS374 Octal D-Type Edge-Triggered Flip-Flop with TRI-STATE Ouputs

This appendix contains the technical data sheet for the DM74AS374 Octal Lacth and wasdownloaded from National Semiconductor’s web site at:

• http://www.national.com