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Welcome to my second year course on Digital Electronics. You will find that the slides are supported by notes embedded with the Powerpoint presentations. All my teaching materials are also available on the course webpage: www.ee.ic.ac.uk/pcheung/teaching/ee2_digital/. The QR code here provides a shortcut to go to the course webpage. I will be updating the notes, the laboratory instructions and tutorial problem sheets each week after the lectures. All my lectures will be recorded with Panopto. The recordings will also be upload as soon as possible after the lectures. The course consists of about 16 hours lectures interleaved with 6 problem solving classes. These will be held on Tuesday 4pm to 6pm and Thursday 12 noon to 1pm starting from 10 th of October. This course follows on from the first year Digital Electronics I course. Unlike the first year course where all gates and flip-flops are assumed to exhibit ideal behaviour, this course will teach you about real-life digital circuits. Digital circuits are ubiquitous. For example, there are more electronic modules in cars these days than mechanical systems. A mobile phone has many times more transistors than human alive on earth, and most of these transistor are digital, i.e. working as on-off switches. Therefore this second year digital electronics course is fundamental to any EEE or EIE education. 1

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Page 1: Hardware Description Language - Imperial College London 1... · 6. Verilog HDL –While you mostly use schematic diagrams to describe your digital ... There are three recommended

WelcometomysecondyearcourseonDigitalElectronics.YouwillfindthattheslidesaresupportedbynotesembeddedwiththePowerpoint presentations.Allmyteachingmaterialsarealsoavailableonthecoursewebpage:www.ee.ic.ac.uk/pcheung/teaching/ee2_digital/.TheQRcodehereprovidesashortcuttogotothecoursewebpage.Iwillbeupdatingthenotes,thelaboratoryinstructionsandtutorialproblemsheetseachweekafterthelectures.AllmylectureswillberecordedwithPanopto.Therecordingswillalsobeuploadassoonaspossibleafterthelectures.

Thecourseconsistsofabout16hourslecturesinterleavedwith6problemsolvingclasses.ThesewillbeheldonTuesday4pmto6pmandThursday12noonto1pmstartingfrom10th ofOctober.

ThiscoursefollowsonfromthefirstyearDigitalElectronicsIcourse.Unlikethefirstyearcoursewhereallgatesandflip-flopsareassumedtoexhibitidealbehaviour,thiscoursewillteachyouaboutreal-lifedigitalcircuits.

Digitalcircuitsareubiquitous.Forexample,therearemoreelectronicmodulesincarsthesedaysthanmechanicalsystems.Amobilephonehasmanytimesmoretransistorsthanhumanaliveonearth,andmostofthesetransistoraredigital,i.e.workingason-offswitches.ThereforethissecondyeardigitalelectronicscourseisfundamentaltoanyEEEorEIEeducation.

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Page 2: Hardware Description Language - Imperial College London 1... · 6. Verilog HDL –While you mostly use schematic diagrams to describe your digital ... There are three recommended

Itisimportantforyoutoknowatthisstagewhatyouareexpectedtolearn(i.e.thelearningoutcomes)fromthismodule.LearningoutcomesspecifyWHATyoushouldbeabletodoasaresultoftakingthismodule.Letmegothroughthelistedoutcomesinsomedetails:1. Understandsynchronousdigitalsystems– ifyouaregivenacircuitwithgatesandflip-flops,youshouldbeabletopredicthowitbehaves.Forexample,youshouldbeabletodrawthetimingdiagramsforoutputsignalsgiventheinputstimuli,orwritedownthesequenceofstatesthatthecircuitmustgothrough.2. DesigncircuitstomeetspecificationInrealcircuits,outputsresponsetochangesininputsaftersomedelay.Inorderforadigitalcircuittoworkasintended,suchdelaymustbetakenintoaccount,andyouasadesignengineermustbesurethattherearenotimingviolations(i.e.circuitdelayscausingthecircuittofail).3. A/DandD/Aconversions– thephysicalworldisgenerallyanalogueinnatureandisnotjust‘1’sand‘0’s.However,electronicsystemsaremostlydigital.AnaloguetoDigital(ADC)andDigitaltoAnalogue(DAC)conversionprovidesthelinkbetweentheanaloguephysicalworldtothedigitalelectronicsworld.YouneedtounderstandHOWanaloguesignalsareconvertedtodigital,andhowtointerpretthedatasheetofsuchcomponents.4. FiniteStateMachines– Designingdigitalcircuitsinvolveunderstandingofvariousfields,andoneofthefieldofstudyisknownasFiniteStateMachine(FSM).Thisisasystematicwaysofthinkinghowadigitalsystemgoesthroughdifferentstates,andasaresult,controltheoperationofadigitalsub-system.5. FieldProgrammableGateArrays– FPGAsisoneoftheprimarytechnologyforimplementingdigitalcircuitsnowadays.Thishasreplacedmostoftheimplementationsin“discretelogic” (suchas16-pinpackagedTTLorCMOSgates).IthasalsoreplacedmanyApplicationSpecificIntegratedCircuits(ASICs)thattheindustryusedtodesign.FPGAsprovetobemuchlower-riskandmusteasiertodesignascomparedtootherapproaches.ThereforethiscoursewillbebasedaroundtheuseofFPGAs.(tocontinue…..)

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Page 3: Hardware Description Language - Imperial College London 1... · 6. Verilog HDL –While you mostly use schematic diagrams to describe your digital ... There are three recommended

6. VerilogHDL– Whileyoumostlyuseschematicdiagramstodescribeyourdigitaldesignsinyourfirstyear,youwillABANDONthisinfavour ofacomputerlanguagetospecifyanddesignyourdigitalcircuits.Youmayfindthisoddinitiallybecausediagramsaregenerallymoreintuitivethanacomputerlanguage.However,usingaHardwareDescriptionLanguage(HDLasitiscalled),andinourcase,usingVerilog,isthewaythatmostmoderndigitalsystemsarespecifiedanddesigned.Nomatterwhetheryoulikeprogrammingornot,asaelectronicengineer,youwillhavenochoicebuttolearnsuchalanguage.

ThiscoursewillbeassessedthroughanexaminationpaperinJune2017.TherewillalsobeanassociatedE2LaboratoryExperiment– VERI.

TheLaboratoryExperimentisEXTREMELYIMPORTANTinhelpingyoutolearnthissubject.ItisintendedtoteachyouhowtodesigndigitalcircuitsusingVerilogHDLtargetingimplementationsonFPGAs.TheLabsessionswillrunforFOURweeksstartingonthe13thofNovember,andassessmentforthisexperimentwilltakeplaceinthelastweekofterm(starting11thofDecember).Youmayalsoborrowtheexperimentboard(DE1-SOC)touseathomeandatyourleisure,oneweekatatime.Therewillbearoundonesuchboardforeveryfourstudentstoshare.

Therearethreerecommendedtextbook“FundamentalofDigitalLogicwithVerilogDesign3/e” byStephenBrownandZvonko Vranesic.Unfortunatelythisbookisinshortsupplyandisextremelyexpensivetobuynew.Youmaybeabletopickupasecondhandcopyontheinternet.AnotherpossiblebookbutlessrelevantisbyDallyandHarting.WhileitisNOTnecessarytoownatextbookformycoursebecauseIdonotfollowaparticulartextbookinmylecturesorinthelab,IwouldrecommendyoutogetholdofasecondhandcopyoraneBookindigitalasareference.Thethirdbook,alsonotcompulsory,is“DigitalDesign(Verilog)” andisveryVerilogspecific.ItisagoodbookifyouwanttolearnVerilogwell.Againitisnotcompulsory.

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ThepracticalaspectsofthiscoursemoduleisbasedaroundaFPGAboard,theDE1-SoC.Hereisanoverallblockdiagramoftheboard.Don’tworryaboutthedetailsfornow.IwillbeexplainingtoyouthevariousbitsoftheboardlaterwhenyouareabouttostarttheVERIexperimentintheLabinmid-November.

ThereshouldoneDE1boardforeveryfourstudentstoborrowanduseathome.Thebasiclendingdurationisoneweek.YoucanrenewyourborrowingperiodbeyondoneweekiftherearefreeonesintheStores.

Toborrowaboard,bringyourIDCardtoLevel1store,andyoucancheckoutaboardtotakeaway.Butyoumustreturnitattheendoftheloanperiod.ThisboardhaseverythingyouneedtodotheexperimentandMORE.ItconsistsofaCycloneVFPGA(whichIwillexplaininmoredetailsinalaterlecture).Ithasvariousinputandoutputdevices.Thisisaverypowerfulboardanditcontainslotsofadditionalhardwareresourcesthatgobeyondthescopeofthismoduleandtheexperiment.Youareencouragedtoexploreit,particularlyifyouareanEIEstudent(andthereforehavealreadyusedFPGAsinyourfirstyearSummerTermProject).

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Thisisthecurrentlectureplanforthecourse.Detailsmaychangeasweprogressthroughtheterm.Therewillbearound16lectures(slightlyhigherthanthenominal15lecturepermoduleinthesecondyear).

Iwillcoveranumberoftopicsthatformthebasiccourseindigitalelectronics.Bytheendofthecourse,youshouldbeabletoindependentlydesigndigitalcircuitsusingFPGAs.TherewillalsobeacoupleoflecturesonhowtointerfacedigitalsystemswiththeanaloguesystemviaD-to-AandA-to-Dconverters.

IwillbelinkingmylecturestotheLabExperimentwhereverpossible.Todowellonthiscourse,youreallyneedtotaketheLabseriously!

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Thislectureisjustpartlyarevisionlecture,andIalsowanttointroduceyoutoalternativenotationsusedbothinthenotesandinsometextbooks.ThisfollowstheIEEEstandardfordigitalschematics.

Insteadofusingcurvesforgates,onecoulduserectangularblocksandasymboltodenotethelogicfunction.Inversioncouldbeontheinputoroutputterminal.Insteadofacircle,wecoulduseasmalltriangleasshownhere.

IEEEpublishesthestandards,andthereisanexcellenttutorialonthisdigitalcircuitnotationspublishedbyTexasInstrument(seethecoursewebpage).Youdon’treallyneedtospendmucheffortonthis– justneedtolearnthebasicssothatyoucanunderstandthemeaningofthesymbolsandthelabelsusedforsignals.

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Inthefirstyear,youlearnedaboutthedifferentwaysofdescribingorspecifyingadigitalcircuit.

1. Schematicdiagramswithgates– thismethodisthefirstthingyoulearnedanditiseasytounderstand.However,aswillbeseeninLecture3,thisisnotnecessarilythebestwaytospecifyalargedigitalsystem.

2. Booleanequations– thisprovidesaformalwaytoexpresslogicalrelationshipsbetweenBooleanvariables.Usefulwhendesigningonpaper,butlessusefulinpractice.Inparticular,werarelyuseBooleanalgebratoperformlogicsimplificationinreal-life!

3. TruthTables– thisisauniversalwaytodescribethebehaviourofacircuitandwecontinuetousethisindatasheetsoreveninactualdesigns.

4. Timingdiagrams– thisisausefulwaytoexplainbehaviourofsequentialcircuitsandisusedindatasheets.However,notthatusefulasamethodtospecifyacircuitinaCADsystem.

5. HardwareDescriptionLanguages(HDLs)– thisisanewmethodyoulearnthisyear(exceptEIEstudentswhohavealreadyencounteredthisintheirgroupproject).Thisiswhatwewillbeusingtospecifyanddesigndigitalhardwarefromnowon.Forthiscourse,wewillbeusingVerilogHDL,whichisonethatisveryclosedtotheClanguage.ItisalsousedextensivelyfordesigningintegratedcircuitssuchasASICsandothertypeofchips.AnotherpopularHDLisVHDL.IpersonallyfindVHDLtoowordy(verbose).Finally,therearenowemerginghigherlevellanguagessuchasOpenCL,whichisattemptingtomakehardwaredesignmorelikeprogrammingacomputer.Thistopicislefttolateryears.

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Youhavealsolearnedaboutthevariousbuildingblocksfordigitalelectronics.1. Primitivegates– WehavethebasicAND,OR,NAND,NOR,XORandXNORgates.2. MultiplexersMUXs– Thesearereallyusefulcomponent.Shownhereisa2-to-1MUXwithtwodatainputsandoneselectinput.Theoutputisoneortheotherdependingontheselectinput(sel).Weoftenputanumberofthesetogethertoprovidemultiplexingfunctiontoamult-bitdataword(asshownherewithtwo3-bitnumbers).3. Arithmeticcircuits– Commonlyfoundareaddersandmultipliers.Subtractor canbebuiltfromanadderifweuse2’scomplementrepresentationofsignedintegers.4. Encoders/Decoders– Thesetwoarerelated.Encoding isalogicmodulethatreduces(encodes)alargenumberofbitsandproducesfeweroutputbits.Decoders aretheopposite.Shownhereisa7-segmentdisplaydecoder,where4inputbitsaredecodedinto7logicsignalstodrivethesevensegmentsofthedisplay.Theencoder hereisknownasapriorityencoder.Itproducesa3-bitoutputshowingwherethefirst‘1’ isencountersfromthemost-significantbitD7totheleastsignificantbitD0.5. Flipflops andRegisters– Thesearethebuildingblocksforallsequentialcircuits.Aswillbeseenlater,wereallyonlyuseonetypeofflipflop – theD-FF.Theseareallimportantcomponentsthatalldigitalcircuitdesignersneedtobefamiliarwith.However,nowadays,werarelydesignlargedigitalsystemsatsuchlowlevels.Insteadwegenerallytrytoexpressthesebuildingblocksinamoreabstractmannerinahardwaredescriptionlanguage(aswewillseeinlaterlectures).Inadditiontothesebasicblocks,wealsohavememorydevicesandmicroprocessors.Thesearetopicsthatwewillcovertowardstheendofthismodule.

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Alldigitalcircuitsexhibitpropagationdelay.Hereitshowsthedelaytablefora“discretelogic” CMOSNANDgate.Thedelaycouldbeintheregionofnanoseconds.However,withtheFPGAchipsweuseforthismodule,theinternal“gate”propagationdelayisapproximately100ps,whichismuchfasterthandiscretelogic.Ascanbeseenlater,the“gate” insidetheFPGAisalsomuchmorecomplexthanasimpleNANDgate.

Alsonotethatpropagationdelaydependsonthe“cause” (inputrisingorfalling,andontheslopeoftheedge)andthe“effect” (outputrisingorfalling).Delayalsodependsonwhatareconnectedtotheoutput(i.e.theloading).Ascanbeseenintheexamplehere,therisingedgeAtofallingedgeXdelayislowerthanthatofAfallingtoXrising.

NotethatIuseanarrowtoindicatethecause(thebluntend)andtheeffect(thepointedend)inatimingdiagram.

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Page 10: Hardware Description Language - Imperial College London 1... · 6. Verilog HDL –While you mostly use schematic diagrams to describe your digital ... There are three recommended

Youlearnedaboutvarioustypesofflipflops(FFs)inthefirstyear.Infact,allyouneedistheD-FF.WithaD-FF,youcanconstructcircuitstobehavelikevarioustypesofflipflops:Toggle(T-FF),set-reset(SR-FF)oraJK-FF.

Thereforeinthiscourse,wewillONLYuseD-FFforeverything.Thisisinfactwhathappensinpracticaldesigns.

WeusetheIEEEstandardsforthesymbolhere.Cmeanclockinput,thenumber1isanumericallabel(asclock1).Disfordatainput,and1Dmeansthisinputiscontrolledbyinput1.Qistheflipflopoutput.

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Timinganddelayparametersforflipflopisdifferentfromthatwithgates.ShownhereisaD-FFthatresponsestoarisingedgeontheclocksignal.AD-FFislikeacamera,takinga“picture” fromthescene(inputisD).TheclockinputC1islikethetriggeronthecamera– whenpresseditsamplestheinputandtakeapicture.The“cause” hereistherisingedgeoftheCLOCKandthe“effect” istheQoutputsamplingtheDinput,andkeepthevalueuntilthenextrisingedgeoftheclock.

ThedelayhereisfromCLOCKrisingedgetoQoutputchanging.However,fortheD-FFtoworkproperly,therearetwoothertimingparameterswhichareimportant:thesetuptimeandtheholdtime.Iwillbetalkingabouttheseinalaterlecture.

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Page 12: Hardware Description Language - Imperial College London 1... · 6. Verilog HDL –While you mostly use schematic diagrams to describe your digital ... There are three recommended

HereisanexampleofaD-FFusedinaripplecounter.

Q0valueisfirstinverted(representedbythetriangle)andthenusedasDinputonthenextclockcycle.TheflipflopistriggeredontheFALLINGedgeofCLOCK.ThereforetheQoutput“TOGGLES” oneachactiveedgeoftheclock(i.e.fallingedge).Q0isthereforechangingathalftherateofCLOCK,hencethisflipflopactsasadivide-by-2circuit.

TheQ0signalisnowusedasclockinputtothenextD-FF.HenceQ1istogglingathalfthefrequencyofQ0.Thecircuitiseffectivelyabinarycounter.

Thisisasimplefinitestatemachine(FSM)becauseithas8stateswhichcyclesthroughinasequence.FSMwillbecoveredinsomelaterlecturesindetailsanditisaveryimportanttopicindigitaldesigns.

WethenusetheQ0outputastheclockinputthenextstageetc.Notethatbecausethe2nd stageonlystartstoworkoncethefirststageiscompleted,thepropagationofeffects“ripples” throughthecircuit– hencewecallthisa“ripplecounter”.

Thiscounterisalsoknownasanasynchronoussequentialcircuit.Itis“asynchronous” becausetheoutputsignalsareNOTsynchronisedtoasingleclocksignal(sincetherearemanyclocksignals),and“sequential” becauseitscurrentoutputvalue(orstate)dependsonpreviousoutputvaluesinthesequence.

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Theripplecounterispotentiallyslow.Thedelaybetweentheactiveedgeoftheclockandthecounteroutputgivingthecorrectvalueisdependentonthenumberofflipflops inthecircuitandthereforethesizeofthecounter(i.e.howmanystages).

Afarbetterapproachistousetheflipflops TOGETHERasagroup,andclockthemusingTHESAMECLOCKsignalasshownhere.TheLogicBlockisacombinatorialcircuitwhichcomputesthenextDvalueD2:0fromthecurrentQvalueQ2:0.(DhasthreebitsD0,D1andD2.WeusethenotationD2:0torepresentthis.)TherelationshipbetweenDandQissimple:D2:0=Q2:0+1.

SincethethreeoutputbitsQ2:0changewithinafractionofananosecondofeachother,thiscircuitis:1)fasterthantheripplecounter;2)the“delay” isconstantinsteadofdependentonthesizeofthecounter.

Thiscircuitisknownasa synchronoussequentialcircuitbecauseitsfunctionissynchronoustoasingleclocksignal.IfyouregardtheQ2:0outputvalueasastatevalue,itfollowsafinitenumberofstatesinadefinedsequence.ThereforeitisalsoaformofFiniteStateMachine.

Notethenotationwiththearrows.

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