Hardware-In-The-Loop Testbed

Team 186: Douglas Pence, Ken Gobin, Aaron Eaddy, Advisor Sung Yeul Park Department of Electrical and Computer Engineering, School of Engineering

Acknowledgements• Center for Clean Energy Engineering (C2E2)• Office of Undergraduate Research• Department of Electrical and Computer Engineering

Introduction As we advance in technology, everything is getting smaller, faster and more versatile. This project focuses on versatility at its core, by proposing and developing a proof-of-concept multifunctional diagnostic testbed for potential use in electrochemical batteries, fuel cells and eventually all major versions of electronic energy storage devices. The goal of this project is to design and implement viable circuitry, programming and digital signal processing to measure and record operational battery parameters using a hardware-in-the-loop testbed. The hardware-in-the-loop testbed concept utilizes a hardware embedded test loop connected to a cache of third party software simulation tools through an interface circuit. This type of system setup allows the testing of individual components using simulated parameters without actually putting the system under load. These conditions make the development and testing of any system safer and more reliable.

Figure 1. Hardware-In-The-Loop Testbed Block Diagram

Methods and Materials The proposed design for this project uses three stages – a sensor board, an interface board and dSPACE® software simulation tools. The sensor board is a circuit board containing all analog sensor portions and mechanical interface of our design. The interface board provides the signal conditioning and analog-to-digital processing from the sensor board. The dSPACE® software package provides the ability to accept these signals and process them for display as well as perform programmed operations to display more detailed real-time parameters such as Remaining Useful Life (RUL) and State of Charge (SOC). MATLAB® Simulink is used to provide a smooth interface between the dSPACE® embedded test loop and user. A block diagram of the design is shown in Figure 1.

Implementation The implementation of our design consists of connecting sensors directly to the battery testbed and feeding the analog signals through a digital signal conditioning and interface board using a wired interface between two printed circuit boards (PCBs). The interface circuit processes and sends the now digital signal through eight BNC connections to the dSPACE® ADC interface. The signals are then translated, processed and displayed for use by the user. A pulse width modulation (PWM) select signal is generated by dSPACE® and sent to the interface board through a 37-pin dSUB ribbon connector for use by the multiplexers (MUXs). The physical design setup is shown above in Figure 3.

Results This hardware-in-the-loop testbed design setup functioned as intended. Through the process of designing the circuits, the decision was made to simplify from an initial ‘8’-channel design to the current ‘4+2’-channel design for simplification and efficiency. This design is also limited to a 30-Volt energy storage total testbed capacity. To qualitatively show our results, the measurement, processing and analysis results of the design are compared to a limited commercial test platform from Texas Instruments® for direct comparison.

Conclusion Overall this multifunctional testbed design can complete its purpose. Expansion of digital signal processing could be done to provide a wider extent of more complex properties of real-time battery operation. The scope of our overall design could also be expanded at a later date to attempt to include a much larger number of data processing channels and types of energy storage units.

Figure 4. dSPACE® RTI-1104

Figure 2. dSPACE® Control Desk Figure 3. Physical Design Setup