hc05jb3grs/h rev1...motorola, inc., 1998 hc05jb3grs/h rev 1 68hc05jb3 68hc705jb3 specification...
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HC05JB3GRS/HREV 1
68HC05JB368HC705JB3
SPECIFICATION(General Release)
November 5, 1998
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products hereinto improve reliability, function or design. Motorola does not assume any liability arising outof the application or use of any product or circuit described herein; neither does it conveyany license under its patent rights nor the rights of others. Motorola products are notdesigned, intended, or authorized for use as components in systems intended for surgicalimplant into the body, or other applications intended to support or sustain life, or for anyother application in which the failure of the Motorola product could create a situationwhere personal injury or death may occur. Should Buyer purchase or use Motorolaproducts for any such unintended or unauthorized application, Buyer shall indemnify andhold Motorola and its officers, employees, subsidiaries, affiliates, and distributorsharmless against all claims, costs, damages, and expenses, and reasonable attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associatedwith such unintended or unauthorized use, even if such claim alleges that Motorola wasnegligent regarding the design or manufacture of the part.
Motorola, Inc., 1998
November 5, 1998 GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section Page
SECTION 1GENERAL DESCRIPTION
1.1 FEATURES...................................................................................................... 1-11.2 MASK OPTIONS.............................................................................................. 1-21.3 MCU STRUCTURE.......................................................................................... 1-21.4 FUNCTIONAL PIN DESCRIPTION.................................................................. 1-41.4.1 VDD and VSS ................................................................................................ 1-41.4.2 OSC1, OSC2 ............................................................................................... 1-41.4.3 RESET......................................................................................................... 1-61.4.4 IRQ .............................................................................................................. 1-61.4.5 3.3V ............................................................................................................. 1-61.4.6 D+ and D– ................................................................................................... 1-61.4.7 PA0-PA7 ...................................................................................................... 1-61.4.8 PB0-PB2, PB3-PB7 ..................................................................................... 1-71.4.9 PC0-PC3...................................................................................................... 1-7
SECTION 2MEMORY
2.1 I/O AND CONTROL REGISTERS ................................................................... 2-22.2 RAM ................................................................................................................. 2-22.3 ROM................................................................................................................. 2-22.4 I/O REGISTERS SUMMARY ........................................................................... 2-3
SECTION 3CENTRAL PROCESSING UNIT
3.1 REGISTERS .................................................................................................... 3-13.2 ACCUMULATOR (A)........................................................................................ 3-23.3 INDEX REGISTER (X) ..................................................................................... 3-23.4 STACK POINTER (SP) .................................................................................... 3-23.5 PROGRAM COUNTER (PC) ........................................................................... 3-23.6 CONDITION CODE REGISTER (CCR) ........................................................... 3-33.6.1 Half Carry Bit (H-Bit) .................................................................................... 3-33.6.2 Interrupt Mask (I-Bit) .................................................................................... 3-33.6.3 Negative Bit (N-Bit) ...................................................................................... 3-33.6.4 Zero Bit (Z-Bit) ............................................................................................. 3-33.6.5 Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
SECTION 4INTERRUPTS
4.1 INTERRUPT VECTORS .................................................................................. 4-14.2 INTERRUPT PROCESSING............................................................................ 4-24.3 RESET INTERRUPT SEQUENCE .................................................................. 4-44.4 SOFTWARE INTERRUPT (SWI) ..................................................................... 4-4
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4.5 HARDWARE INTERRUPTS ............................................................................ 4-44.5.1 External Interrupt IRQ.................................................................................. 4-44.5.2 IRQ Control/Status Register (ICSR) - $0A................................................... 4-54.5.3 Port A External Interrupts (PA0-PA3, by mask option) ................................ 4-64.5.4 Timer1 Interrupt (TIMER1)........................................................................... 4-74.5.5 USB Interrupt (USB) .................................................................................... 4-74.5.6 MFT Interrupt (MFT) .................................................................................... 4-7
SECTION 5RESETS
5.1 POWER-ON RESET........................................................................................ 5-25.2 EXTERNAL RESET ......................................................................................... 5-25.3 INTERNAL RESETS........................................................................................ 5-25.3.1 Power-On Reset (POR) ............................................................................... 5-25.3.2 USB Reset ................................................................................................... 5-35.3.3 Computer Operating Properly (COP) Reset ................................................ 5-35.3.4 Low Voltage Reset (LVR) ............................................................................ 5-35.3.5 Illegal Address Reset................................................................................... 5-4
SECTION 6LOW POWER MODES
6.1 STOP MODE.................................................................................................... 6-36.2 WAIT MODE .................................................................................................... 6-36.3 DATA-RETENTION MODE.............................................................................. 6-3
SECTION 7INPUT/OUTPUT PORTS
7.1 PORT-A............................................................................................................ 7-17.1.1 Port-A Data Register.................................................................................... 7-27.1.2 Port-A Data Direction Register .................................................................... 7-27.1.3 Port-A Pull-down/up Register ...................................................................... 7-27.1.4 PA0-PA3 Interrupts...................................................................................... 7-27.1.5 PA0-PA7 Optical Interface........................................................................... 7-37.2 PORT-B............................................................................................................ 7-37.2.1 Port-B Data Register.................................................................................... 7-37.2.2 Port-B Data Direction Register .................................................................... 7-37.2.3 Port-B Pull-down/up Register ...................................................................... 7-47.2.4 PB1, PB2 Slow Transition Output................................................................ 7-47.3 PORT-C ........................................................................................................... 7-57.3.1 Port-C Data Register ................................................................................... 7-57.3.2 Port-C Data Direction Register .................................................................... 7-57.3.3 Port-C Pull-down/up Register ...................................................................... 7-6
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SECTION 8MULTI-FUNCTION TIMER
8.1 OVERVIEW...................................................................................................... 8-28.2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-28.3 MFT REGISTERS............................................................................................ 8-28.3.1 Timer Counter Register (TCNT) $09 ........................................................... 8-28.3.2 Timer Control/Status Register (TCSR) $08 ................................................. 8-38.4 OPERATION DURING STOP MODE .............................................................. 8-48.5 COP CONSIDERATION DURING STOP MODE............................................. 8-4
SECTION 916-BIT TIMER
9.1 TIMER REGISTERS (TMRH, TMRL)............................................................... 9-29.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-49.3 INPUT CAPTURE REGISTERS ...................................................................... 9-59.4 OUTPUT COMPARE REGISTERS ................................................................. 9-89.5 TIMER CONTROL REGISTER (TCR) ........................................................... 9-109.6 TIMER STATUS REGISTER (TSR)............................................................... 9-119.7 TIMER OPERATION DURING WAIT MODE................................................. 9-129.8 TIMER OPERATION DURING STOP MODE................................................ 9-12
SECTION 10UNIVERSAL SERIAL BUS MODULE
10.1 FEATURES.................................................................................................... 10-110.2 OVERVIEW.................................................................................................... 10-210.2.1 USB Protocol ............................................................................................. 10-310.2.2 Reset Signaling.......................................................................................... 10-810.2.3 Suspend..................................................................................................... 10-910.2.4 Resume After Suspend.............................................................................. 10-910.2.5 Low Speed Device................................................................................... 10-1010.3 CLOCK REQUIREMENTS........................................................................... 10-1010.4 HARDWARE DESCRIPTION....................................................................... 10-1010.4.1 Voltage Regulator .................................................................................... 10-1110.4.2 USB Transceiver...................................................................................... 10-1210.4.3 Receiver Characteristics.......................................................................... 10-1210.4.4 USB Control Logic ................................................................................... 10-1410.5 I/O REGISTER DESCRIPTION ................................................................... 10-1810.5.1 USB Address Register (UADDR)............................................................. 10-1910.5.2 USB Interrupt Register 0 (UIR0) .............................................................. 10-1910.5.3 USB Interrupt Register 1 (UIR1) .............................................................. 10-2110.5.4 USB Control Register 0 (UCR0) .............................................................. 10-2210.5.5 USB Control Register 1 (UCR1) .............................................................. 10-2310.5.6 USB Control Register 2 (UCR2) .............................................................. 10-24
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10.5.7 USB Status Register (USR)..................................................................... 10-2510.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)................................... 10-2610.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7) ................ 10-2610.6 USB INTERRUPTS...................................................................................... 10-2610.6.1 USB End of Transaction Interrupt............................................................ 10-2710.6.2 Resume Interrupt ..................................................................................... 10-2710.6.3 End of Packet Interrupt ............................................................................ 10-28
SECTION 11OPTICAL INTERFACE
11.1 OVERVIEW.................................................................................................... 11-111.2 OPTICAL INTERFACE ENABLE REGISTER................................................ 11-3
SECTION 12INSTRUCTION SET
12.1 ADDRESSING MODES ................................................................................. 12-112.1.1 Inherent...................................................................................................... 12-112.1.2 Immediate .................................................................................................. 12-112.1.3 Direct ......................................................................................................... 12-212.1.4 Extended.................................................................................................... 12-212.1.5 Indexed, No Offset..................................................................................... 12-212.1.6 Indexed, 8-Bit Offset .................................................................................. 12-212.1.7 Indexed, 16-Bit Offset ................................................................................ 12-312.1.8 Relative...................................................................................................... 12-312.1.9 Instruction Types ....................................................................................... 12-312.1.10 Register/Memory Instructions .................................................................... 12-412.1.11 Read-Modify-Write Instructions ................................................................. 12-512.1.12 Jump/Branch Instructions .......................................................................... 12-512.1.13 Bit Manipulation Instructions...................................................................... 12-712.1.14 Control Instructions.................................................................................... 12-712.1.15 Instruction Set Summary ........................................................................... 12-8
SECTION 13ELECTRICAL SPECIFICATIONS
13.1 MAXIMUM RATINGS..................................................................................... 13-113.2 THERMAL CHARACTERISTICS................................................................... 13-113.3 DC ELECTRICAL CHARACTERISTICS........................................................ 13-213.4 USB DC ELECTRICAL CHARACTERISTICS ............................................... 13-313.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS............... 13-413.6 CONTROL TIMING........................................................................................ 13-5
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SECTION 14MECHANICAL SPECIFICATIONS
14.1 20-PIN PDIP (CASE 738) .............................................................................. 14-114.2 28-PIN PDIP (CASE 710) .............................................................................. 14-114.3 20-PIN SOIC (CASE 751D) ........................................................................... 14-214.4 28-PIN SOIC (CASE 751F)............................................................................ 14-2
APPENDIX AMC68HC705JB3
A.1 INTRODUCTION..............................................................................................A-1A.2 MEMORY.........................................................................................................A-1A.3 MASK OPTION REGISTER (MOR).................................................................A-1A.4 BOOTSTRAP MODE .......................................................................................A-3A.5 EPROM PROGRAMMING...............................................................................A-3A.5.1 EPROM Program Control Register (PCR)...................................................A-3A.5.2 Programming Sequence ..............................................................................A-4A.6 EPROM PROGRAMMING SPECIFICATIONS................................................A-5
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MOTOROLA MC68HC05JB3vi REV 1
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LIST OF FIGURES
Figure Title Page
1-1 MC68HC05JB3 Block Diagram........................................................................ 1-31-2 MC68HC05JB3 Pin Assignments .................................................................... 1-41-3 Oscillator Connections ..................................................................................... 1-52-1 MC68HC05JB3 Memory Map .......................................................................... 2-12-2 MC68HC05JB3 I/O Registers $0000-$000F.................................................... 2-32-3 MC68HC05JB3 I/O Registers $0010-$001F.................................................... 2-42-4 MC68HC05JB3 I/O Registers $0020-$002F.................................................... 2-52-5 MC68HC05JB3 I/O Registers $0030-$003F.................................................... 2-62-6 COP Register (COPR) ..................................................................................... 2-63-1 MC68HC05 Programming Model ..................................................................... 3-14-1 Interrupt Stacking Order................................................................................... 4-24-2 Interrupt Flowchart ........................................................................................... 4-34-3 External Interrupt (IRQ) Logic .......................................................................... 4-54-4 IRQ Control and Status Register (ICSR).......................................................... 4-55-1 Reset Sources.................................................................................................. 5-15-2 COP Watchdog Register (COPR).................................................................... 5-36-1 STOP and WAIT Flowchart.............................................................................. 6-27-1 PB1 Slow Falling-edge Output ......................................................................... 7-58-1 Multi-Function Timer Block Diagram................................................................ 8-18-2 Timer Counter Register.................................................................................... 8-38-3 Timer Control/Status Register (TCSR)............................................................. 8-39-1 Programmable Timer Block Diagram............................................................... 9-19-2 Programmable Timer Counter Block Diagram ................................................. 9-29-3 Programmable Timer Counter Registers (TMRH, TMRL)................................ 9-39-4 Alternate Counter Block Diagram..................................................................... 9-49-5 Alternate Counter Registers (ACRH, ACRL).................................................... 9-49-6 Timer Input Capture Block Diagram................................................................. 9-59-7 TCAP Input Signal Conditioning....................................................................... 9-69-8 TCAP Input Comparator Output....................................................................... 9-79-9 Input Capture Registers (ICRH, ICRL)............................................................. 9-79-10 Timer Output Compare Block Diagram............................................................ 9-99-11 Output Compare Registers (OCRH, OCRL) .................................................... 9-99-12 Timer Control Register (TCR) ........................................................................ 9-109-13 Timer Status Registers (TSR) ........................................................................ 9-1110-1 USB Block Diagram ....................................................................................... 10-210-2 Supported Transaction Types per Endpoint................................................... 10-310-3 Supported USB Packet Types ....................................................................... 10-410-4 Sync Pattern................................................................................................... 10-410-5 SOP, Sync Signaling and Voltage Levels ...................................................... 10-510-6 CRC Block Diagram for Address and Endpoint Fields................................... 10-610-7 CRC Block Diagram for Data Packets ........................................................... 10-710-8 EOP Transaction Voltage Levels ................................................................... 10-810-9 EOP Width Timing.......................................................................................... 10-8
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LIST OF FIGURES
Figure Title Page
10-10 External Low Speed Device Configuration................................................... 10-1010-11 Regulator Electrical Connections................................................................. 10-1110-12 Low Speed Driver Signal Waveforms .......................................................... 10-1210-13 Differential Input Sensitivity Over Entire Common Mode Range ................. 10-1310-14 Data Jitter..................................................................................................... 10-1410-15 Data Signal Rise and Fall Time.................................................................... 10-1410-16 NRZI Data Encoding .................................................................................... 10-1510-17 Flow Diagram for NRZI ................................................................................ 10-1510-18 Bit Stuffing.................................................................................................... 10-1610-19 Flow Diagram for Bit Stuffing ....................................................................... 10-1710-20 USB Address Register (UADDR)................................................................. 10-1910-21 USB Interrupt Register 0 (UIR0) .................................................................. 10-1910-22 USB Interrupt Register 1(UIR1) ................................................................... 10-2110-23 USB Control Register 0 (UCR0)................................................................... 10-2210-24 USB Control Register 1 (UCR1)................................................................... 10-2310-25 USB Control Register 2 (UCR2)................................................................... 10-2410-26 USB Status Register (USR) ......................................................................... 10-2510-27 USB Endpoint 0 Data Register (UE0D0-UE0D7)......................................... 10-2610-28 USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)...................... 10-2610-29 OUT Token Data Flow for Receive Endpoint 0 ............................................ 10-2910-30 SETUP Token Data Flow for Receive Endpoint 0........................................ 10-3010-31 IN Token Data Flow for Transmit Endpoint 0 ............................................... 10-3110-32 IN Token Data Flow for Transmit Endpoint 1/2 ............................................ 10-3211-1 A pair of Optical Coupler Interface................................................................. 11-211-2 Optical Interface Comparator ......................................................................... 11-211-3 Optical Interface Enable Register (TCSR) ..................................................... 11-314-1 20-Pin PDIP Mechanical Dimensions ............................................................ 14-114-2 28-Pin PDIP Mechanical Dimensions ............................................................ 14-114-3 20-Pin SOIC Mechanical Dimensions............................................................ 14-214-4 28-Pin SOIC Mechanical Dimensions............................................................ 14-2A-1 MC68HC705JB3 Memory Map ........................................................................A-2A-2 EPROM Programming Sequence ....................................................................A-5
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4-1 Reset/Interrupt Vector Addresses.................................................................... 4-17-1 Summary of Port Pin Functions ....................................................................... 7-18-1 RTI and COP Rates at fOP=3.0MHz................................................................ 8-310-1 Supported Packet Identifiers .......................................................................... 10-510-2 Register Summary ....................................................................................... 10-1811-1 Port-A Optical Interface Pairs......................................................................... 11-111-2 Optical Interface Reference Voltage Selection .............................................. 11-312-1 Register/Memory Instructions ........................................................................ 12-412-2 Read-Modify-Write Instructions ..................................................................... 12-512-3 Jump and Branch Instructions........................................................................ 12-612-4 Bit Manipulation Instructions .......................................................................... 12-712-5 Control Instructions ........................................................................................ 12-712-6 Instruction Set Summary ............................................................................... 12-812-7 Opcode Map................................................................................................. 12-1413-1 DC Electrical Characteristics.......................................................................... 13-213-2 USB DC Electrical Characteristics ................................................................. 13-313-3 USB Low Speed Source Electrical Characteristics ........................................ 13-413-4 Control Timing................................................................................................ 13-5A-1 EPROM Programming Electrical Characteristics .............................................A-5
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MOTOROLA MC68HC05JB3x REV 1
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SECTION 1GENERAL DESCRIPTION
The MC68HC05JB3 is a member of the low-cost, high-performance M68HC05Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based onthe customer-specified integrated circuit design strategy. All MCUs in the familyuse the popular M68HC05 central processing unit (CPU) and are available with avariety of subsystems, memory sizes and types, and package types.
The MC68HC05JB3 is specifically designed to be used in applications where alow speed (1.5Mbps) Universal Serial Bus (USB) interface is required.
1.1 FEATURES
• Industry standard M68HC05 CPU core
• Memory-mapped input/output (I/O) registers
• 2560 Bytes of user ROM
• 144 Bytes of user RAM (includes 64 byte stack)
• Fully compliant Low Speed USB with 3 Endpoints:
– 1 Control Endpoint (2×8-byte buffer)
– 2 Interrupt Endpoints (1×8-byte buffer shared)
• 3.3V dc output for USB pull-up resistors
• 19 Bidirectional I/O pins with the following features:
– 17 I/Os have software programmable pull-down capability
– 2 open-drain I/Os have software programmable pull-up, 25mA currentsink capability
– 4 I/Os with external interrupt capability
– 8 I/Os (in 4 pairs) with programmable optical interface
• Multi-Function Timer (MFT)
• 16-bit Timer with 1 input capture and 1 output compare
• Low Voltage Reset (LVR)
• Computer Operating Properly (COP) Watchdog Reset
• Illegal Address Reset
MC68HC05JB3 GENERAL DESCRIPTION MOTOROLAREV 1 1-1
GENERAL RELEASE SPECIFICATION November 5, 1998
• Power-Saving STOP and WAIT Modes
• Available in 20-pin PDIP, 20-pin SOIC, 28-pin PDIP, and 28-pin SOICpackages
1.2 MASK OPTIONS
The following mask options are available:
• External interrupt pins (IRQ, PA0 to PA3):[edge-triggered or edge-and-level-triggered]
• Port A, port B, and port C pull-down/pull-up resistors:[connected or disconnected]
• PA0-PA3 external interrupt capability:[enabled or disabled]
• OSC, crystal/ceramic resonator startup delay:[4064 or 224 internal bus cycles]
• Low Voltage Reset (LVR):[enabled or disabled]
• COP function of MFT:[enabled or disabled]
1.3 MCU STRUCTURE
Figure 1-1 shows the structure of MC68HC05JB3 MCU.
MOTOROLA GENERAL DESCRIPTION MC68HC05JB31-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 1-1. MC68HC05JB3 Block Diagram
144 Bytes RAM 2560 Bytes EPROM
Low SpeedUSB
16-bit Timer
CoreTImer
OSC÷2
RESETandIRQ
LVRVREF
POWERSUPPLY
PO
RT
A
DA
TA
DIR
EC
TIO
N R
EG
. A
PO
RT
B
DA
TA
DIR
EC
TIO
N R
EG
. B
CPU CONTROL ALU
68HC05 CPU
ACCUM
INDEX REG.
CPU REGISTERS
PROGRAM COUNTER
COND CODE REG.
000 0 0 0 0 1 1 STK PNTR0
1 1 1 H I N Z C
PA0①
PA1①
PA2①
PA3①
PA4②
PA5②
PA6②
PA7②
VDD
VSS
3.3V
RESET
IRQ
TCAP➂
D+
D–
OSC1
OSC2
②: 8mA current sink capability and optical interface
➃: 25mA current sink, open-drained
①: External edge interrupt capability,
with internal pull-up, slow transition O/P
➂: PB0 is shared with TCAP
with Schmitt trigger input and optical interface
PB0➂
PB1➃
PB2➃
PB4➄
PB5➄
PB6➄
PB7➄
PO
RT
C
DA
TA
DIR
EC
TIO
N R
EG
. C
PC0➄†
PC1➄
PC2➄
PC3➄
➄: Pins available in 28-pin package only
➄†: PC0 shared with OCMP
OCMP➄†
MC68HC05JB3 GENERAL DESCRIPTION MOTOROLAREV 1 1-3
GENERAL RELEASE SPECIFICATION November 5, 1998
Figure 1-2. MC68HC05JB3 Pin Assignments
1.4 FUNCTIONAL PIN DESCRIPTION
The following paragraphs give a description of the general function of each pinassigned in Figure 1-2.
1.4.1 VDD and VSS
Power is supplied to the MCU through VDD and VSS. VDD is the positive supply,and VSS is ground. The MCU operates from a single power supply.
Very fast signal transitions occur on the MCU pins. The short rise and fall timesplace very high short-duration current demands on the power supply. To preventnoise problems, special care should be taken to provide good power supplybypassing at the MCU by using bypass capacitors with good high-frequency char-acteristics that are positioned as close to the MCU as possible. Bypassingrequirements vary, depending on how heavily the MCU pins are loaded.
1.4.2 OSC1, OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator. TheOSC1 and OSC2 pins can accept the following sets of components:
1. A crystal as shown in Figure 1-3(a)
2. A ceramic resonator as shown in Figure 1-3(a)
3. An external clock signal as shown in Figure 1-3(b)
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
8
9
10
11
PA6
PB7
PA5
PB4
PA7
PA3
PB5
D+
D–
PC2
PA2
PA1
RESET
PA0 OSC1
OSC2
VSS
12
13
14
PB2
IRQ
17
16
15
PC0/OCMP
PC1
3.3V
VDD
PB1
PB0/TCAP PB6
PC3
PA4
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10 PA5IRQ
PA4
PB2
PA7
PA6
PA3
PA2
PA1
RESET
PA0 OSC1
OSC2
VSS
3.3V
D+
D–
VDD
PB0/TCAP
PB1
20-pin package
28-pin package
MOTOROLA GENERAL DESCRIPTION MC68HC05JB31-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
The frequency, f
OSC
, of the oscillator or external clock source is divided by two toproduce the internal operating frequency, f
OP
. If the internal operating frequency is3MHz, then the external oscillator frequency will be 6MHz. For LS USB 1.5MHzfrequency clock can be derived from a divided by 4 circuit. The type of oscillator isselected by a mask option. An internal 2M
Ω
resistor may be selected betweenOSC1 and OSC2 by a mask option (crystal/ceramic resonator mode only).
Crystal Oscillator
The circuit in
Figure 1-3
(a) shows a typical oscillator circuit for an AT-cut, parallelresonant crystal. The crystal manufacturer’s recommendations should be fol-lowed, as the crystal parameters determine the external component valuesrequired to provide maximum stability and reliable start-up. The load capacitancevalues used in the oscillator circuit design should include all stray capacitances.The crystal and components should be mounted as close as possible to the pinsfor start-up stabilization and to minimize output distortion. An internal start-upresistor of approximately 2M
Ω
is provided between OSC1 and OSC2 for the crys-tal type oscillator as a mask option.
Figure 1-3. Oscillator Connections
Ceramic Resonator Oscillator
In cost-sensitive applications, a ceramic resonator can be used in place of thecrystal. The circuit in
Figure 1-3
(a) can be used for a ceramic resonator. The res-onator manufacturer’s recommendations should be followed, as the resonatorparameters determine the external component values required for maximum sta-bility and reliable starting. The load capacitance values used in the oscillator cir-cuit design should include all stray capacitances. The ceramic resonator andcomponents should be mounted as close as possible to the pins for start-up stabi-lization and to minimize output distortion. An internal start-up resistor of approxi-mately 2 M
Ω
is provided between OSC1 and OSC2 for the ceramic resonator typeoscillator as a mask option.
MCU
OSC1 OSC2
2MΩUnconnected
External Clock
MCU
OSC1 OSC2
(a) Crystal or Ceramic Resonator Connections (b) External Clock Source Connection
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External Clock
An external clock from another CMOS-compatible device can be connected to theOSC1 input, with the OSC2 input not connected, as shown in
Figure 1-3
(b).Thisconfiguration is possible ONLY when the crystal/ceramic resonator mask option isselected.
1.4.3 RESET
This is an I/O pin. This pin can be used as an input to reset the MCU to a knownstart-up state by pulling it to the low state. The RESET pin contains a steeringdiode to discharge any voltage on the pin to V
DD
, when the power is removed. Aninternal pull-up is also connected between this pin and V
DD
. The RESET pin con-
tains an internal Schmitt trigger to improve its noise immunity as an input. This pinis an output pin if LVR triggers an internal reset.
1.4.4 IRQ
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQinterrupt function has a mask option to provide either only negative edge-sensitivetriggering or both negative edge-sensitive and low level-sensitive triggering. If theoption is selected to include level-sensitive triggering, the IRQ input requires anexternal resistor to V
DD
for "wired-OR" operation, if desired. The IRQ pin containsan internal Schmitt trigger as part of its input to improve noise immunity.
NOTE
Each of the PA0 to PA3 I/O pins may be connected as an OR function with the IRQinterrupt function by a mask option. This capability allows keyboard scanapplications where the transitions or levels on the I/O pins will behave the sameas the IRQ pin. The edge or level sensitivity selected by a separate mask option
for the IRQ pin also applies to the I/O pins OR’ed to create the IRQ signal.
1.4.5 3.3V
This is an output reference voltage nominally set at 3.3V dc.
1.4.6 D+ and D–
These two lines carry the USB differential data. For low speed device such asMC68HC05JB3, a 1.5 k
Ω
resistor is required to be connected across D– and 3.3Vfor proper signal termination.
1.4.7 PA0-PA7
These eight I/O lines comprise Port A. PA0 to PA7 are push-pull pins with pull-down devices. The state of any pin is software programmable and all Port A linesare configured as inputs during power-on or reset.
MOTOROLA GENERAL DESCRIPTION MC68HC05JB31-6 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
PA0 to PA3 has external interrupt function (mask option) with schmitt trigger inputcircuit, and PA4 to PA7 has 8mA current sink capability.
Port A can also be configured as the optical interface.
1.4.8 PB0-PB2, PB3-PB7
These seven I/O lines comprise Port B. The state of any pin is software program-mable and is configured as an input during power-on or reset.
PB1 and PB2 are open-drain I/O lines with pull-up devices. PB0 (shared withTCAP) is a push-pull I/O line with pull-down device.
PB1 and PB2 are also slow transition outputs, each has 25mA current sink capa-bility at V OL =0.5V.
PB4-PB7 I/O lines are push-pull pins with pull-down devices, and are only avail-able in the 28-pin package.
1.4.9 PC0-PC3
These four I/O lines comprise Port C. The state of any pin is software programma-ble and all Port C lines are configured as inputs during power-on or reset.
PC0 to PC3 are push-pull pins with pull-down devices. PC0 is also shared with theOCMP pin from the output compare function of the 16-bit timer.
Port C is only available in the 28-pin package.
MC68HC05JB3 GENERAL DESCRIPTION MOTOROLAREV 1 1-7
GENERAL RELEASE SPECIFICATION November 5, 1998
MOTOROLA GENERAL DESCRIPTION MC68HC05JB31-8 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 2MEMORY
The MC68HC05JB3 has 8k-bytes of addressable memory, with 64 bytes of I/O,144 bytes of user RAM, and 2560 bytes of user ROM, as shown in
Figure 2-1
.
Figure 2-1. MC68HC05JB3 Memory Map
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
$003F
$0000
$1FF6
$1FF3
$1FF4
$1FF5
$1FF2
$1FF1
Reserved
USB Vector (Low Byte)
Timer1 Vector (Low Byte)
USB Vector (High Byte)
Timer1 Vector (High Byte)
MFT Vector (Low Byte)
MFT Vector (High Byte)
Reserved
$1FF0
Reserved
Reserved
IRQ Vector (High Byte)
IRQ Vector (Low Byte)
SWI Vector (High Byte)
SWI Vector (Low Byte)
Reset Vector (High Byte)
Reset Vector (Low Byte)
I/O Registers
64 Bytes
I/O Registers64 Bytes
$0000
$003F $0040
$006F
Unused48 Bytes
User RAM144 Bytes
64 Byte Stack
$0070
$00C0
$00FF$0100
$13FF
Unused4864 Bytes
$1400
$1DFF$1E00
$1FEF
User ROM2560 Bytes
Self-Check ROM496 Bytes
User Vectors16 Bytes
$1FF0
$1FFF
MC68HC05JB3 MEMORY MOTOROLAREV 1 2-1
GENERAL RELEASE SPECIFICATION November 5, 1998
2.1 I/O AND CONTROL REGISTERS
The I/O and Control Registers reside in locations $0000 to $003F. The bit assign-ments for each register are shown in
Figure 2-2
,
Figure 2-3
,
Figure 2-4
, and
Figure 2-5
. Reading from unused bits will return unknown states, and writing tounused bits will be ignored.
2.2 RAM
The user RAM consists of 144 bytes (including the stack) at locations $0080 to$012F. The stack begins at address $00FF and proceeds down to $00C0. Usingthe stack area for data storage or temporary work locations requires care to pre-vent it from being overwritten due to stacking from an interrupt or subroutine call.
2.3 ROM
There are a total of 3k-bytes of ROM on chip. This includes 2560 bytes of userROM with locations $1400 to $1DFF for user program storage and 16 bytes foruser vectors at locations $1FF0 to $1FFF. Also, 496 bytes of Self-check ROM onchip at locations $1E00 to $1FEF.
MOTOROLA MEMORY MC68HC05JB32-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
2.4 I/O REGISTERS SUMMARY
ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$0000Port A Data R
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0PORTA W
$0001Port B Data R
PB7 PB6 PB5 PB4 PB2 PB1 PB0PORTB W
$0002Port C Data R
PC3 PC2 PC1 PC0PORTC W
$0003 UnusedR
W
$0004Port A Data Direction R
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0DDRA W
$0005Port B Data Direction R
DDRB7 DDRB6 DDRB5 DDRB4 SLOWE DDRB2 DDRB1 DDRB0DDRB W
$0006Port C Data Direction R
OCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0DDRC W
$0007 UnusedR
W
$0008MFT Ctrl/Status R TOF RTIF
TOFE RTIE0 0
RT1 RT0TCSR W TOFR RTIFR
$0009MFT Counter R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
TCNT W
$000AIRQ Control/Status R
IRQE0 0 0 IRQF 0 0
IRQPUICSR W IRQR
$000B UnusedR
W
$000C UnusedR
W
$000D UnusedR
W
$000EOptical Interface En. R
TCMPE VREF2 VREF1 VREF0 OIE3 OIE2 OIE1 OIE0OIER W
$000FPort C Pull-down/up R
PDURC W PDRC3 PDRC2 PDRC1 PDRC0
unused bits reserved bits
Figure 2-2. MC68HC05JB3 I/O Registers $0000-$000F
MC68HC05JB3 MEMORY MOTOROLAREV 1 2-3
GENERAL RELEASE SPECIFICATION November 5, 1998
ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$0010Port A Pull-down/up R
PDURA W PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0
$0011Port B Pull-down/up R
PDURB W PDRB7 PDRB6 PDRB5 PDRB4 PURB2 PURB1 PDRB0
$0012Timer1 Control R
ICIE OCIE TOIE0 0 0
IEDG0
TCR W
$0013Timer1 Status R ICF OCF TOF 0 0 0 0 0
TSR W
$0014Input Capture MSB R ICH7 ICH6 ICH5 ICH4 ICH3 ICH2 ICH1 ICH0
ICH W
$0015Input Capture LSB R ICL7 ICL6 ICL5 ICL4 ICL3 ICL2 ICL1 ICL0
ICL W
$0016Output Compare MSB R
OCH7 OCH6 OCH5 OCH4 OCH3 OCH2 OCH1 OCH0OCH W
$0017Output Compare LSB R
OCL7 OCL6 OCL5 OCL4 OCL3 OCL2 OCL1 OCL0OCL W
$0018Timer1 Counter MSB R TCNTH7 TCNTH6 TCNTH5 TCNTH4 TCNTH3 TCNTH2 TCNTH1 TCNTH0
TCNTH W
$0019Timer1 Counter LSB R TCNTL7 TCNTL6 TCNTL5 TCNTL4 TCNTL3 TCNTL2 TCNTL1 TCNTL0
TCNTL W
$001AAlter. Counter MSB R ACNTH7 ACNTH6 ACNTH5 ACNTH4 ACNTH3 ACNTH2 ACNTH1 ACNTH0
ACNTH W
$001BAlter. Counter LSB R ACNTL7 ACNTL6 ACNTL5 ACNTL4 ACNTL3 ACNTL2 ACNTL1 ACNTL0
ACNTL W
$001C UnusedR
W
$001D UnusedR
W
$001E UnusedR
W
$001F UnusedR
W
unused bits reserved bits
Figure 2-3. MC68HC05JB3 I/O Registers $0010-$001F
MOTOROLA MEMORY MC68HC05JB32-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$0020USB Endpoint 0 Data 0 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R0 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0021USB Endpoint 0 Data 1 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R1 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0022USB Endpoint 0 Data 2 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R2 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0023USB Endpoint 0 Data 3 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R3 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0024USB Endpoint 0 Data 4 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R4 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0025USB Endpoint 0 Data 5 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R5 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0026USB Endpoint 0 Data 6 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R6 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0027USB Endpoint 0 Data 7 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UD0R7 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0028USB Endpoint 1 Data 0 R
UD1R0 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
$0029USB Endpoint 1 Data 1 R
UD1R1 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
$002AUSB Endpoint 1 Data 2 R
UD1R2 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
$002BUSB Endpoint 1 Data 3 R
UD1R3 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
$002CUSB Endpoint 1 Data 4 R
UD1R4 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
$002DUSB Endpoint 1 Data 5 R
UD1R5 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
$002EUSB Endpoint 1 Data 6 R
UD1R6 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
$002FUSB Endpoint 1 Data 7 R
UD1R7 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
unused bits reserved bits
Figure 2-4. MC68HC05JB3 I/O Registers $0020-$002F
MC68HC05JB3 MEMORY MOTOROLAREV 1 2-5
GENERAL RELEASE SPECIFICATION November 5, 1998
ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$0030 UnusedR
W
$0031 UnusedR
W
$0032 UnusedR
W
$0033 UnusedR
W
$0034 UnusedR
W
$0035 UnusedR
W
$0036 UnusedR
W
$0037USB Control 2 R 0 TX1ST 0
ENABLE2 ENABLE1 STALL2 STALL1UCR2 W TX1STR
$0038USB Address R
USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0UADR W
$0039USB Interrupt 0 R TXD0F RXD0F RSTF
SUSPND TXD0IE RXD0IE0 0
UIR0 W 0 0 0 TXD0FR RXD0FR
$003AUSB Interrupt 1 R TXD1F EOPF RESUMF 0
TXD1IE EOPIE0 0
UIR1 W 0 0 0 RESUMFR TXD1FR EOPFR
$003BUSB Control 0 R
T0SEQ STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0UCR0 W
$003CUSB Control 1 R
T1SEQ ENDADD TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0UCR1 W
$003DUSB Status R RSEQ SETUP RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0
USR W
$003E ReservedR
W
$003F ReservedR
W
unused bits reserved bits
Figure 2-5. MC68HC05JB3 I/O Registers $0030-$003F
ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$1FF0COP Register R 0 0 0 0 0 0 0 0
COPR W COPR
Figure 2-6. COP Register (COPR)
MOTOROLA MEMORY MC68HC05JB32-6 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 3CENTRAL PROCESSING UNIT
The MC68HC05JB3 has an 8k-bytes memory map. The stack has only 64 bytes.Therefore, the stack pointer has been reduced to only 6 bits and will onlydecrement down to $00C0 and then wrap-around to $00FF. All other instructionsand registers behave as described in this chapter.
3.1 REGISTERS
The MCU contains five registers which are hard-wired within the CPU and are notpart of the memory map. These five registers are shown in Figure 3-1 and aredescribed in the following paragraphs.
Figure 3-1. MC68HC05 Programming Model
CONDITION CODE REGISTER I
ACCUMULATOR
6 0
A
INDEX REGISTER
7 1
X
45 23
STACK POINTER SP
14 815 91213 1011
PC
CC1 1 1
1 100000000
PROGRAM COUNTER
H N Z C
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
MC68HC05JB3 CENTRAL PROCESSING UNIT MOTOROLAREV 1 3-1
GENERAL RELEASE SPECIFICATION November 5, 1998
3.2 ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. TheCPU uses the accumulator to hold operands and results of arithmetic calculationsor non-arithmetic operations. The accumulator is not affected by a reset of thedevice.
3.3 INDEX REGISTER (X)
The index register shown in Figure 3-1 is an 8-bit register that can perform twofunctions:
• Indexed addressing
• Temporary storage
In indexed addressing with no offset, the index register contains the low byte ofthe operand address, and the high byte is assumed to be $00. In indexedaddressing with an 8-bit offset, the CPU finds the operand address by adding theindex register content to an 8-bit immediate value. In indexed addressing with a16-bit offset, the CPU finds the operand address by adding the index registercontent to a 16-bit immediate value.
The index register can also serve as an auxiliary accumulator for temporarystorage. The index register is not affected by a reset of the device.
3.4 STACK POINTER (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices withmemory space less than 64k-bytes the unimplemented upper address lines areignored. The stack pointer contains the address of the next free location on thestack. During a reset or the reset stack pointer (RSP) instruction, the stack pointeris set to $00FF. The stack pointer is then decremented as data is pushed onto thestack and incremented as data is pulled off the stack.
When accessing memory, the ten most significant bits are permanently set to0000000011. The six least significant register bits are appended to these ten fixedbits to produce an address within the range of $00FF to $00C0. Subroutines andinterrupts may use up to 64($C0) locations. If 64 locations are exceeded, thestack pointer wraps around and overwrites the previously stored information. Asubroutine call occupies two locations on the stack and an interrupt uses fivelocations.
3.5 PROGRAM COUNTER (PC)
The program counter shown in Figure 3-1 is a 16-bit register. In MCU deviceswith memory space less than 64k-bytes the unimplemented upper address linesare ignored. The program counter contains the address of the next instruction oroperand to be fetched.
MOTOROLA CENTRAL PROCESSING UNIT MC68HC05JB33-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Normally, the address in the program counter increments to the next sequentialmemory location every time an instruction or operand is fetched. Jump, branch,and interrupt operations load the program counter with an address other than thatof the next sequential location.
3.6 CONDITION CODE REGISTER (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used toindicate the results of the instruction just executed. The fifth bit is the interruptmask. These bits can be individually tested by a program, and specific actions canbe taken as a result of their states. The condition code register should be thoughtof as having three additional upper bits that are always ones. Only the interruptmask is affected by a reset of the device. The following paragraphs explain thefunctions of the lower five bits of the condition code register.
3.6.1 Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4of the accumulator during the last ADD or ADC (add with carry) operation. Thehalf-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
3.6.2 Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled.Interrupts are enabled when the interrupt mask is cleared. When an interruptoccurs, the interrupt mask is automatically set after the CPU registers are savedon the stack, but before the interrupt vector is fetched. If an interrupt requestoccurs while the interrupt mask is set, the interrupt request is latched. Normally,the interrupt is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,restoring the interrupt mask to its state before the interrupt was encountered. Afterany reset, the interrupt mask is set and can only be cleared by the Clear I-Bit(CLI), or WAIT instructions.
3.6.3 Negative Bit (N-Bit)
The negative bit is set when the result of the last arithmetic operation, logicaloperation, or data manipulation was negative. (Bit 7 of the result was a logicalone.)
The negative bit can also be used to check an often tested flag by assigning theflag to bit 7 of a register or memory location. Loading the accumulator with thecontents of that register or location then sets or clears the negative bit accordingto the state of the flag.
3.6.4 Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logicaloperation, data manipulation, or data load operation was zero.
MC68HC05JB3 CENTRAL PROCESSING UNIT MOTOROLAREV 1 3-3
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3.6.5 Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurredduring the last arithmetic operation, logical operation, or data manipulation. Thecarry/borrow bit is also set or cleared during bit test and branch instructions andduring shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.
MOTOROLA CENTRAL PROCESSING UNIT MC68HC05JB33-4 REV 1
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SECTION 4INTERRUPTS
The MCU can be interrupted in six different ways:
• Non-maskable Software Interrupt Instruction (SWI)
• External Asynchronous Interrupt (IRQ)
• External Interrupt via IRQ on PA0-PA3 (mask option)
• USB Interrupt
• Timer1 Interrupt (16-bit Timer)
• Multi-Function Timer Interrupt
4.1 INTERRUPT VECTORS
Table 4-1. Reset/Interrupt Vector Addresses
Function SourceControl
Bit
GlobalHardware
Mask
LocalSoftware
Mask
Priority(1 = Highest)
VectorAddress
Reset
Power-On LogicRESET Pin
Low Voltage ResetIllegal Address Reset
— — — 1 $1FFE–$1FFF
COP Watchdog
SoftwareInterrupt (SWI)
User Code — — —Same PriorityAs Instruction
$1FFC–$1FFD
ExternalInterrupt (IRQ)
IRQ Pin — I Bit IRQE Bit 2 $1FFA–$1FFB
USBInterrupts
TXD0FTXD1F
RESUMP— I Bit
TXD0IETXD1IE
—3 $1FF8–$1FF9
Timer1Interrupts
ICF BitOCF BitTOF Bit
— I BitICIE BitOCIE BitTOIE Bit
4 $1FF6–$1FF7
MFTInterrupts
CTOF BitRTIF Bit
— I BitCTOFE BitRTIE Bit
5 $1FF4–$1FF5
Reserved $1FF2–$1FF3
Reserved $1FF0–$1FF1
MC68HC05JB3 INTERRUPTS MOTOROLAREV 1 4-1
GENERAL RELEASE SPECIFICATION November 5, 1998
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of thehigher priority interrupt first. A higher priority interrupt does not actually interrupt alower priority interrupt service routine unless the lower priority interrupt serviceroutine clears the I bit.
4.2 INTERRUPT PROCESSING
The CPU does the following actions to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in Figure 4-1.
• Sets the I bit in the condition code register to prevent further interrupts.
• Loads the program counter with the contents of the appropriate interruptvector locations as shown in Table 4-1.
The return from interrupt (RTI) instruction causes the CPU to recover its registercontents from the stack as shown in Figure 4-1. The sequence of events causedby an interrupt are shown in the flow chart in Figure 4-2.
$0020 (BOTTOM OF RAM)
$0021
$00BE
$00BF
$00C0 (BOTTOM OF STACK)
$00C1
$00C2 UNSTACKING
ORDER
⇓n CONDITION CODE REGISTER 5 1
n+1 ACCUMULATOR 4 2
n+2 INDEX REGISTER 3 3
n+3 PROGRAM COUNTER (HIGH BYTE) 2 4
n+4 PROGRAM COUNTER (LOW BYTE) 1 5
⇑STACKING
$00FD ORDER
$00FE
$00FF TOP OF STACK (RAM)
Figure 4-1. Interrupt Stacking Order
MOTOROLA INTERRUPTS MC68HC05JB34-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 4-2. Interrupt Flowchart
NO
EXTERNALINTERRUPT?
I BIT SET?
FROMRESET
YES
YESCLEAR IRQ LATCH.
NO
EXECUTE INSTRUCTION.
UNSTACK CCR, A, X, PCH, PCL.
FETCH NEXTINSTRUCTION.
STACK PCL, PCH, X, A, CCR.SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
USBINTERRUPT?
YES
NO
TIMER1INTERRUPT?
YES
NO
MFTINTERRUPT?
YES
NO
SWIINSTRUCTION?
YES
NO
RTIINSTRUCTION?
YES
NO
MC68HC05JB3 INTERRUPTS MOTOROLAREV 1 4-3
GENERAL RELEASE SPECIFICATION November 5, 1998
4.3 RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is actedupon in a similar manner as shown in Figure 4-2. A low level input on the RESETpin or an internally generated RST signal causes the program to vector to its start-ing address which is specified by the contents of memory locations $1FFE and$1FFF. The I-bit in the condition code register is also set.
4.4 SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-rupts pending during the previous instruction will be serviced before the SWIopcode is fetched. The interrupt service routine address is specified by the con-tents of memory locations $1FFC and $1FFD.
4.5 HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If theI-bit is set, all hardware interrupts (internal and external) are disabled. Clearingthe I-bit enables the hardware interrupts. There are two types of hardware inter-rupts which are explained in the following sections.
4.5.1 External Interrupt IRQ
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram ofthe IRQ logic is shown in Figure 4-3.
The IRQ pin is one source of an IRQ interrupt and a mask option can also enablethe four lower Port-A pins (PA0 to PA3) to act as other IRQ interrupt sources.
Refer to Figure 4-3 for the following descriptions. IRQ interrupt source comesfrom IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or onany falling edge of PA0-3 pins if PA0-3 interrupts have been enabled. If ‘edge-only’sensitivity is chosen by a mask option, only the IRQ latch output can activate anIRQF flag which creates a request to the CPU to generate the IRQ interruptsequence. This makes the IRQ interrupt sensitive to the following cases:
1. Falling edge on the IRQ pin.
2. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option).
If level sensitivity is chosen, the active high state of the signal to the clock input ofthe IRQ latch can also activate an IRQF flag which creates an IRQ request to theCPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensi-tive to the following cases:
1. Low level on the IRQ pin.
2. Falling edge on the IRQ pin.
3. Low level on any PA0-PA3 pin with IRQ enabled (via mask option).
4. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option).
MOTOROLA INTERRUPTS MC68HC05JB34-4 REV 1
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The IRQE enable bit controls whether an active IRQF flag can generate an IRQinterrupt sequence. This interrupt is serviced by the interrupt service routinelocated at the address specified by the contents of $1FFA and $1FFB.
If IRQF is set, the only way to clear this flag is by writing a logic one to the IRQRacknowledge bit in the ICSR. As long as the output state of the IRQF flag bit isactive the CPU will continuously re-enter the IRQ interrupt sequence until theactive state is removed or the IRQE enable bit is cleared.
Figure 4-3. External Interrupt (IRQ) Logic
4.5.2 IRQ Control/Status Register (ICSR) - $0A
The IRQ interrupt function is controlled by the ICSR located at $000A. All unusedbits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit isset by reset.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ICSR RIRQE
0 0 0 IRQF 0 0IRQPU
$000A W IRQR
reset: 1 0 0 0 0 0 0 0
Figure 4-4. IRQ Control and Status Register (ICSR)
IRQ
IRQLATCH
VDD
RSTIRQ VECTOR FETCH
IRQ STATUS/CONTROL REGISTER
EXTERNALINTERRUPTREQUEST
IRQ
E
IRQ
F
IRQ
R
INTERNAL DATA BUS
TO BIH & BILINSTRUCTIONPROCESSING
R
IRQ Level(Mask Option)
PA0
PA1
PA2
PA3
Port A External Interrupt(Mask Option)
MC68HC05JB3 INTERRUPTS MOTOROLAREV 1 4-5
GENERAL RELEASE SPECIFICATION November 5, 1998
IRQPU — IRQ pin PUll-up resistor enableThis bit enables/disables the internal pull-up resistor on the IRQ pin.
1 = Internal pull-up resistor in IRQ pin enabled.0 = Internal pull-up resistor in IRQ pin disabled.
IRQR — IRQ Interrupt AcknowledgeThis write-only bit clears an IRQ interrupt by clearing the IRQ latch, and hencethe IRQF bit. The IRQR bit will always read as a logic zero.
1 = Clears IRQ interrupt request (clears IRQF). 0 = No effect.
IRQF — IRQ Interrupt Request FlagWriting to the IRQF flag bit will have no effect on it. If the additional setting ofIRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bitremains set the CPU will re-enter the IRQ interrupt sequence continuously untileither the IRQF flag bit or the IRQE enable bit is clear. The IRQF latch iscleared by reset.
1 = Indicates that an IRQ request is pending.0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
pending. The IRQF flag bit can be cleared by writing a logic one tothe IRQR acknowledge bit to clear the IRQ latch and alsoconditioning the external IRQ sources to be inactive (if the levelsensitive interrupts are enabled via mask option). Doing so beforeexiting the service routine will mask out additional occurrences ofthe IRQF.
IRQE — IRQ Interrupt EnableThe IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interruptsequence.
1 = Enables IRQ interrupt, that is, the IRQF flag bit can generate aninterrupt sequence. Reset sets the IRQE enable bit, therebyenabling IRQ interrupts once the I-bit is cleared. Execution of theSTOP or WAIT instructions causes the IRQE bit to be set in order toallow the external IRQ to exit these modes.
0 = The IRQF flag bit cannot generate an interrupt sequence.
4.5.3 Port A External Interrupts (PA0-PA3, by mask option)
The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pinsif enabled by a single mask option. If enabled, the lower four bits of Port A canactivate the IRQ interrupt function, and the interrupt operation will be the same asfor inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of theseinput pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pinsmust be selected as a group as an additional IRQ interrupt. All the PA0-3 interruptsources are also controlled by the IRQE enable bit.
MOTOROLA INTERRUPTS MC68HC05JB34-6 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ pin itself, andnot to the output of the logic OR function with the PA0 to PA3 pins. The state of theindividual Port A pins can be checked by reading the appropriate Port A pins asinputs.
NOTE
If enabled, the PA0 to PA3 pins will cause an IRQ interrupt only when thecorresponding pin is configured as input.
4.5.4 Timer1 Interrupt (TIMER1)
The TIMER1 interrupt is generated by the 16-bit timer when either an overflow oran input capture or output compare has occurred as described in the section on16-bit timer. The interrupt flags and enable bits for the Timer1 interrupts arelocated in the Timer1 Control & Status Register (TSR) located at $0012, $0013.The I-bit in the CCR must be clear in order for the TIMER1 interrupt to be enabled.Either of these three interrupts will vector to the same interrupt service routinelocated at the address specified by the contents of memory locations $1FF6 and$1FF7.
4.5.5 USB Interrupt (USB)
The USB interrupt is generated by the USB module as described in the section onUniversal Serial Bus. The interrupt enable bits for the USB interrupt are located atbit3-bit2 of UIR0 register and bit3-bit2 of UIR1 register. Also Once the device goesinto Suspend Mode, any bus activities will cause the USB to generate an interruptto CPU to come out from the Suspend mode. The I-bit in the CCR must be clear inorder for the USB interrupt to be enabled. Either of these two interrupts will vectorto the same interrupt service routine located at the address specified by the con-tents of memory locations $1FF8 and $1FF9.
4.5.6 MFT Interrupt (MFT)
The MFT interrupt is generated by the MFT module as described in the section onMulti-function Timer. These interrupts will vector to the same interrupt service rou-tine located at the address specified by the contents of memory locations $1FF4and $1FF5.
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SECTION 5RESETS
This section describes the six reset sources and how they initialize the MCU. Areset immediately stops the operation of the instruction being executed, initializescertain control bits, and loads the program counter with a user defined reset vec-tor address. The following conditions produce a reset:
• Initial power up of device (power on reset).
• A logic zero applied to the RESET pin (external reset).
• Timeout of the COP watchdog (COP reset).
• Low voltage applied to the device (LVR reset).
• Fetch of an opcode from an address not in the memory map (illegaladdress reset).
• Detection of USB reset signal (USB reset).
Figure 5-1 shows a block diagram of the reset sources and their interaction.
Figure 5-1. Reset Sources
RESETRESETLATCH
R
COP WATCHDOG
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL
D
INTERNALCLOCK
S RST TO CPUAND
LOW VOLTAGE RESET
VDD
SUBSYSTEMS
ADDRESS BUS
USB RESET DETECTION
MC68HC05JB3 RESETS MOTOROLAREV 1 5-1
GENERAL RELEASE SPECIFICATION November 5, 1998
5.1 POWER-ON RESET
A positive transition on the VDD pin generates a power-on reset. The power-onreset is strictly for conditions during powering up and cannot be used to detectdrops in power supply voltage.
A 224tCYC or 4064tCYC (internal clock cycle) delay after the oscillator becomesactive allows the clock generator to stabilize. If the RESET pin is at logic zero atthe end of the multiple tCYC time, the MCU remains in the reset condition until thesignal on the RESET pin goes to a logic one.
5.2 EXTERNAL RESET
A logic zero applied to the RESET pin for 1.5tCYC generates an external reset.This pin is connected to a Schmitt trigger input gate to provide and upper andlower threshold voltage separated by a minimum amount of hysteresis. The exter-nal reset occurs whenever the RESET pin is pulled below the lower threshold andremains in reset until the RESET pin rises above the upper threshold. This activelow input will generate the internal RST signal that resets the CPU and peripher-als.
The RESET pin can also act as an open drain output. It will be pulled to a lowstate by an internal pulldown device that is activated by three internal resetsources. This RESET pulldown device will only be asserted for 3 to 4 cycles of theinternal clock, fOP, or as long as the internal reset source is asserted. When theexternal RESET pin is asserted, the pulldown device will not be turned on.
NOTE
Do not connect the RESET pin directly to VDD, as this may overload some powersupply designs when the internal pulldown on the RESET pin activates.
5.3 INTERNAL RESETS
The five internally generated resets are the initial power-on reset function, theCOP Watchdog timer reset, the low voltage reset, and the illegal address detector.Only the COP Watchdog timer reset, low voltage reset and illegal address detec-tor will also assert the pulldown device on the RESET pin for the duration of thereset function or 3 to 4 internal clock cycles, whichever is longer.
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-lize. The POR is strictly for power turn-on conditions and is not able to detect adrop in the power supply voltage (brown-out). There is an oscillator stabilizationdelay of 224 or 4064 (224 or 4064 is selected by mask option) internal processorbus clock cycles after the oscillator becomes active.
MOTOROLA RESETS MC68HC05JB35-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
The POR will generate the RST signal which will reset the CPU. If any other resetfunction is active at the end of the 224 or 4064 cycle delay, the RST signal willremain in the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. VDD must dropbelow VPOR in order for the internal POR circuit to detect the next rise of VDD.
5.3.2 USB Reset
The USB reset is generated by a detection on the USB bus reset signal. ForMC68HC05JB3, seeing a single-end zero on its upstream port for 4 to 8 bit timeswill set RSTF bit in UIR0 register. The detections will also generate the RST signalto reset the CPU and other peripherals in the MCU.
5.3.3 Computer Operating Properly (COP) Reset
The COP watchdog is enabled by a mask option.
A timeout of the COP watchdog generates a COP reset. The COP watchdog ispart of a software error detection system and must be cleared periodically to starta new timeout period. To clear the COP watchdog and prevent a COP reset, writea logic zero to the COPC bit of the COP register at location $1FF0.
COPC — COP ClearCOPC is a write-only bit. Periodically writing a logic zero to COPC prevents theCOP watchdog from resetting the MCU. Reset clears the COPC bit.
1 = No effect on system.0 = Reset COP watchdog timer.
The COP Watchdog reset will assert the pull-down device to pull the RESET pinlow for one cycle of the internal bus clock.
Refer to section on Multi-Function Timer for detail on COP watchdog timeout peri-ods.
5.3.4 Low Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage onthe VDD pin falls below the LVR trip voltage. The LVR will assert the pulldowndevice to pull the RESET pin low one cycle of the internal bus clock. The Low Volt-age Reset circuit is enabled by a mask option.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COPR R 0 0 0 0 0 0 0 0
$1FF0 W COPC
reset: U U U U U U U 0
U = UNAFFECTED BY RESET
Figure 5-2. COP Watchdog Register (COPR)
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5.3.5 Illegal Address Reset
An opcode fetch from an address that is not in the ROM or the RAM generates anillegal address reset. The illegal address reset will assert the pull-down device topull the RESET pin low for 3 to 4 cycles of the internal bus clock.
MOTOROLA RESETS MC68HC05JB35-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 6LOW POWER MODES
There are three modes of operation that reduce power consumption:
• Stop mode
• Wait mode
• Data retention mode
Figure 6-1 shows the sequence of events in Stop and Wait modes.
MC68HC05JB3 LOW POWER MODES MOTOROLAREV 1 6-1
GENERAL RELEASE SPECIFICATION November 5, 1998
Figure 6-1. STOP and WAIT Flowchart
STOP
EXTERNALRESET?
EXTERNALINTERRUPT?
NO
NO
START STABILIZATION DELAY
YES
YES
END OFSTABILIZATION
DELAY?
YES
NO
WAIT
RESTART INTERNAL PROCESSOR CLOCK
1. LOAD PC WITH RESET VECTOROR
2. SERVICE INTERRUPT.a. SAVE CPU REGISTERS ON STACK.b. SET I BIT IN CCR.c. LOAD PC WITH INTERRUPT VECTOR.
NO
EXTERNALRESET?
YES
NO
EXTERNALINTERRUPT?
YES
NO
USB
INTERRUPT?
YESRESET OR
NO
YES
YES
NO
STOP EXTERNAL OSCILLATOR,STOP INTERNAL TIMER CLOCK,
RESET START-UP DELAY
STOP INTERNAL PROCESSOR CLOCK,CLEAR I-BIT IN CCR,
SET IRQE IN ICSR
USBINTERRUPT
NO
YES
IRQ
OR RESET?
RESTART EXTERNAL OSCILLATOR,
IRQ
TIMER1
INTERRUPT?INTERNAL
MFT
INTERRUPT?INTERNAL
EXTERNAL OSCILLATOR ACTIVE,INTERNAL TIMER CLOCK ACTIVE
STOP INTERNAL PROCESSOR CLOCK,CLEAR I-BIT IN CCR,
SET IRQE IN ICSR
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6.1 STOP MODE
STOP mode is entered by executing the STOP instruction. This is the lowestpower consumption mode of the MCU. In the STOP Mode the internal oscillator isturned off, halting all internal processing.
Execution of the STOP instruction automatically clears the I-bit in the ConditionCode Register and sets the IRQE enable bit in the IRQ Control/Status Register sothat the IRQ external interrupt is enabled. All other registers, including the otherbits in the TCSR, and memory remain unaltered. All input/output lines remainunchanged.
The MCU can be brought out of the STOP Mode by an IRQ external interrupt or aUSB coming out from Suspend Mode Interrupt (Bus activity detection) or an exter-nally generated RESET, USB Reset or an LVR reset. When exiting the STOPMode the internal oscillator will resume after a 224 or 4064 internal processorclock cycle oscillator stabilization delay.
6.2 WAIT MODE
WAIT mode is entered by executing the WAIT instruction. This places the MCU ina low-power mode, which consumes more power than the STOP Mode. In theWAIT Mode the internal processor clock is halted, suspending all processor andinternal bus activity. Execution of the WAIT instruction automatically clears the I-bitin the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled. All other registers,memory, and input/output lines remain in their previous states.
The WAIT Mode may be exited when an external IRQ, USB, Timer1 or MFT inter-rupt, an LVR reset, USB reset or an external RESET occurs.
6.3 DATA-RETENTION MODE
The Data-Retention mode is only available if the Low Voltage Reset function(mask option) is not enabled.
In the data retention mode, the MCU retains RAM contents and CPU register con-tents at VDD voltages as low as 2Vdc. The data retention feature allows the MCUto remain in a low power consumption state during which it retains data, but theCPU cannot execute instructions. The RESET pin must be held low during data-retention mode.
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MOTOROLA LOW POWER MODES MC68HC05JB36-4 REV 1
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SECTION 7INPUT/OUTPUT PORTS
In normal operating mode there are 19 usable bidirectional I/O lines arranged asone 8-bit I/O port (Port-A), one 7-bit I/O port (Port-B), and one 4-bit I/O port(Port C). The individual bits in these ports are programmable as either inputs oroutputs under software control by the data direction registers (DDRs).
The eight port pins, PB4-PB7 and PC0-PC3, are only available on the 28-pinversion of the device.
Table 7-1 shows a summary of Port-A, Port-B, and Port-C functions.
7.1 PORT-A
Port-A is an 8-bit bi-directional port. The Port-A data register is at $0000 and thedata direction register (DDRA) is at $0004. Reset does not affect the data regis-ters, but clears the data direction registers, thereby returning the port pins toinputs. Writing a ‘1’ to a DDR bit sets the corresponding port bit to output mode.
All Port-A pins have programmable pull-down resistors. PA4 to PA7 each has 8mAcurrent sink capability.
The table below summarizes the pin configurations for Port-A.
Table 7-1. Summary of Port Pin Functions
Port PinsInternal Resistor
ConfigurationCurrent
Drive/SinkAdditional Features
PA0-PA3
Pull-down1
1.6mA sink External Interrupt2
Optical InterfacePA4-PA7 8mA sink
PB0 1.6mA sink shared with TCAP
PB1, PB2 Pull-up1 25mA sink, open-drain
Slow Transition Output
PB4-PB7
Pull-down1 1.6mA sinkPins available only
in 28-pin devicePC0 shared with OCMP
PC1-PC3
Notes:1. A pull-up/pull-down resistor is enabled by setting the corresponding register bit to “0” and the
port pull-up/down mask option is selected.2. Selected by mask option.
MC68HC05JB3 INPUT/OUTPUT PORTS MOTOROLAREV 1 7-1
GENERAL RELEASE SPECIFICATION November 5, 1998
7.1.1 Port-A Data Register
7.1.2 Port-A Data Direction Register
DDRAx — PAx Data Direction1 = Port pin set as output.0 = Port pin set as input.
7.1.3 Port-A Pull-down/up Register
With the pull-up/down mask option selected, each pin in Port-A has an internalpull-down resistor which can be enabled by writing a ‘0’ to the corresponding bit inthe Port-A pull-down/up control register (PDURA) at location $0010.
PDRAx — PAx Pin Pull-down enable1 = Internal pull-down disabled.0 = Internal pull-down enabled.
7.1.4 PA0-PA3 Interrupts
A mask option selects the capability for PA0-PA3 to be used as external IRQ inter-rupt inputs. These four I/O pins also have schmitt trigger input circuits.
See INTERRUPTS section for detail.
PDRAx DDRAx Pin Configuration
0 0 Input with pull-down
0 1 Output Push/Pull
1 0 Input
1 1 Output Push/Pull
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PORTA RPA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
$0000 W
reset: 0 0 0 0 0 0 0 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DDRA RDDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
$0004 W
reset: 0 0 0 0 0 0 0 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PDURA R
$0010 W PDRA7 PDRA7 PDRA7 PDRA7 PDRA7 PDRA7 PDRA7 PDRA7
reset: 0 0 0 0 0 0 0 0
MOTOROLA INPUT/OUTPUT PORTS MC68HC05JB37-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
7.1.5 PA0-PA7 Optical Interface
Port-A is programmable to use as ports for the optical interface.
See OPTICAL INTERFACE section for details.
7.2 PORT-B
Port-B is a 7-bit bi-directional port. The Port-B data register is at $0001 and thedata direction register (DDRB) is at $0005. Reset does not affect the data regis-ters, but clears the data direction registers, thereby returning the port pins toinputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
PB4-PB7 are only available on the 28-pin version of the device.
All Port-B pins have programmable pull-down or pull-up resistors. PB1 and PB2each has 25mA current sink capability.
PB0 is also used as the 16-timer TCAP input pin. When configured as output, theinput to the input capture will be permanently tied “low” and no input capture canbe generated.
The table below summarizes the pin configurations for Port-B.
7.2.1 Port-B Data Register
7.2.2 Port-B Data Direction Register
DDRBx — PBx Data Direction1 = Port pin set as output.0 = Port pin set as input.
PDRBx/PURBx DDRBx Pin Configuration
0 0PB0, PB4-PB7: Input with pull-down
PB1, PB2: Input with pull-up
0 1PB0, PB4-PB7: Output Push-Pull
PB1, PB2: Output Open-drain with pull-up
1 0 Input
1 1PB0, PB4-PB7: Output Push-Pull
PB1, PB2: Output Open-drain
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PORTB RPB7 PB6 PB5 PB4
0PB2 PB1 PB0
$0001 W
reset: 0 0 0 0 0 0 0 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DDRB RDDRB7 DDRB6 DDRB5 DDRB4 SLOWE DDRB2 DDRB1 DDRB0
$0005 W
reset: 0 0 0 0 0 0 0 0
MC68HC05JB3 INPUT/OUTPUT PORTS MOTOROLAREV 1 7-3
GENERAL RELEASE SPECIFICATION November 5, 1998
SLOWE — Slow Transition EnableSee Section 7.2.4 for details.
1 = Enable slow falling-edge output transition feature on PB1 and PB2.0 = Disable slow falling-edge output transition feature on PB1 and PB2.
7.2.3 Port-B Pull-down/up Register
With the pull-up/down mask option selected, PB0 and PB4-PB7 each has an inter-nal pull-down resistor, while PB1 and PB2 each has an internal pull-up resistor,which can be enabled by writing a ‘0’ to the corresponding bit in the Port-Bpull-down/up control register (PDURB) at location $0011.
PDRBx — PBx Pin Pull-down enable1 = Internal pull-down disabled.0 = Internal pull-down enabled.
PURBx — PBx Pin Pull-up enable1 = Internal pull-up disabled.0 = Internal pull-up enabled.
7.2.4 PB1, PB2 Slow Transition Output
The slow transition output feature is enabled by setting the SLOWE bit in DDRB at$0005.
PB2 — a high-to-low output transition is a sharp falling edge transition delayed bytCYC ÷ 2.
PB1 — a high-to-low output transition is a slow falling edge (drops from 5.0V to2.2V in 167ns typically at fOP=3MHz, with 50pF load) followed by a fast transitionto VSS. The fast transition duration is depending on the strength of the outputdriver defined for each port. See Figure 7-1.
Both PB1 and PB2 have 25mA current sink capability.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PDURB R
$0011 W PDRB7 PDRB6 PDRB5 PDRB4 PURB2 PURB1 PDRB0
reset: 0 0 0 0 0 0 0 0
MOTOROLA INPUT/OUTPUT PORTS MC68HC05JB37-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 7-1. PB1 Slow Falling-edge Output
7.3 PORT-C
Port-C is a 4-bit bi-directional port. The Port-C data register is at $0002 and thedata direction register (DDRC) is at $0006. Reset does not affect the data regis-ters, but clears the data direction registers, thereby returning the port pins toinputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
All Port-C pins have programmable pull-down resistors, and are only available onthe 28-pin version of the device.
PC0 is also used as the 16-timer OCMP output pin.
The table below summarizes the pin configurations for Port-A.
7.3.1 Port-C Data Register
7.3.2 Port-C Data Direction Register
PDRCx DDRCx Pin Configuration
0 0 Input with pull-down
0 1 Output Push-Pull
1 0 Input
1 1 Output Push-Pull
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PORTC RPC3 PC2 PC1 PC0
$0002 W
reset: 0 0 0 0 0 0 0 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DDRC ROCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0
$0006 W
reset: 0 0 0 0 0 0 0 0
50pF
5.0V
165ns 330ns
2.2VOutput Driver
0V
MC68HC05JB3 INPUT/OUTPUT PORTS MOTOROLAREV 1 7-5
GENERAL RELEASE SPECIFICATION November 5, 1998
DDRCx — PCx Data Direction1 = Port pin set as output.0 = Port pin set as input.
VROFF — USB 3.3V Voltage ReferenceSee USB section for details.
1 = Disable 3.3V regulator.0 = Enables 3.3V regulator.
OCMPO — OCMP Output EnableSee 16-BIT TIMER section for details.
1 = PC0 is OCMP pin, OCF from 16-bit timer output compare.0 = PC0 is standard I/O pin, from Port-C data register.
7.3.3 Port-C Pull-down/up Register
With the pull-up/down mask option selected, each pin in Port-C has an internalpull-down resistor which can be enabled by writing a ‘0’ to the corresponding bit inthe Port-C pull-down/up control register (PDURC) at location $000F.
PDRCx — PCx Pin Pull-down Enable1 = Internal pull-down disabled.0 = Internal pull-down enabled.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PDURC R
$000F W PDRC3 PDRC2 PDRC1 PDRC0
reset: 0 0 0 0 0 0 0 0
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November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 8MULTI-FUNCTION TIMER
The Multi-Function Timer (or Core Timer) module is a 15-stage ripple counter withTimer Over Flow (CTOF), Real Time Interrupt (RTI), and COP Watchdog function.
Figure 8-1. Multi-Function Timer Block Diagram
COP Watchdog
RTI Select Circuit
Overflow
CircuitDetect
8 8
fOP÷22
÷210
InternalTimer Clock(NTF1)
CTOF RTIF CTOFE RTIE RT1 RT0RTIFRCTOFR
Timer Control & Status Register ($08)
Timer Counter Register ($09)
Interrupt Circuit
Resetable Timer (÷8)
7-bit counter
MCU Internal Bus
to CPU interrupt
÷214÷215÷217 ÷216
÷4
MC68HC05JB3 MULTI-FUNCTION TIMER MOTOROLAREV 1 8-1
GENERAL RELEASE SPECIFICATION November 5, 1998
8.1 OVERVIEW
As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided byfour. NTF1 has the same phase and frequency as the processor bus clock, PH2,but continues to run in WAIT mode. The NTF1 drives an 8-bit ripple counter. Thevalue of this 8-bit ripple counter can be read by the CPU at any time by accessingthe Timer Counter Register (TCNT) at address $09. A timer overflow function isimplemented on the last stage of this 8-bit counter, giving a possible interrupt rateof fOP÷1024.
The last stage of the 8-bit counter also drives a further 7-bit counter. The final fourstages is used by the RTI circuit, giving possible RTI rates of fOP÷214, 215, 216 or217, selected by RT1 and RT0 (see Table 8-1). The RTI rate selector bits, and theRTI and CTOF enable bits and flags are located in the Timer Control and StatusRegister at location $08.
The power-on cycle clears the entire counter chain and begins clocking thecounter. After 224 or 4064 cycles, the power-on reset circuit is released whichagain clears the counter chain and allows the device to come out of reset. At thispoint, if RESET is not asserted, the timer will start counting up from zero and nor-mal device operation will begin. If RESET is asserted at any time during operationthe counter chain will be cleared.
8.2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG
The COP Watchdog is enabled by a mask option.
The COP Watchdog Timer function is implemented by using the output of the RTIcircuit and further dividing it by eight. The minimum COP reset rates are listed inTable 8-1. If the COP circuit times out, an internal reset is generated and the nor-mal reset vector is fetched.
Preventing a COP time-out is done by writing a “0” to bit-0 of address $1FF0.When the COP is cleared, only the final divide by eight stage (output of the RTI) iscleared.
8.3 MFT REGISTERS
8.3.1 Timer Counter Register (TCNT) $09
The Timer Counter Register is a read-only register which contains the currentvalue of the 8-bit ripple counter at the beginning of the timer chain. This counter isclocked at fOP÷4 and can be used for various functions including a software inputcapture. Extended time periods can be attained using the CTOF function to incre-ment a temporary RAM storage location thereby simulating a 16-bit (or more)counter. The value of each bit of the TCNT is shown in Figure 8-2. This register iscleared by reset.
MOTOROLA MULTI-FUNCTION TIMER MC68HC05JB38-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 8-2. Timer Counter Register
8.3.2 Timer Control/Status Register (TCSR) $08
The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, andthe real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which willread as logical zeros. Figure 8-3 shows the value of each bit in the TCSR follow-ing reset.
Figure 8-3. Timer Control/Status Register (TCSR)
RT0, RT1 — Real-Time Interrupt period select bitsThese two bits select the Real-Time Interrupt period and the COP Watchdogreset period.
RTIFR — Real Time Interrupt AcknowledgeThe RTIFR is an acknowledge bit that resets the RTIF flag bit. This bit is unaf-fected by reset. Reading the RTIFR will always return a logical zero.
1 = Clears the RTIF flag bit.0 = Does not clear the RTIF flag bit.
CTOFR — Timer Overflow AcknowledgeThe CTOFR is an acknowledge bit that resets the CTOF flag bit. This bit isunaffected by reset. Reading the CTOFR will always return a logical zero.
1 = Clears the CTOF flag bit.0 = Does not clear the CTOF flag bit.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TCNT R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
$0009 W
reset: 0 0 0 0 0 0 0 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TCSR R CTOF RTIFCTOFE RTIE
0 0RT1 RT0
$0008 W CTOFR RTIFR
reset: 0 0 0 0 0 0 1 1
Table 8-1. RTI and COP Rates at fOP=3.0MHz
Bus Frequency, fBUS=fOP=3.0 MHz
RT1 RT0 Divide Ratio RTI RateCOP Reset Period
(RTI × 8)
0 0 214 5.46ms 43.68ms
0 1 215 10.92ms 87.36ms
1 0 216 21.85ms 174.8ms
1 1 217 43.69ms 349.52ms
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RTIE — Real Time Interrupt EnableThe RTIE is an enable bit that allows generation of a TIMER Interrupt by theRTIF bit.
1 = When set, the TIMER Interrupt is generated when the RTIF flag bit isset.
0 = When cleared, no TIMER interrupt caused by RTIF bit set will begenerated. This bit is cleared by reset.
CTOFE — Timer Overflow EnableThe CTOFE is an enable bit that allows generation of a TIMER Interrupt uponoverflow of the Timer Counter Register.
1 = When set, the TIMER Interrupt is generated when the CTOF flag bitis set.
0 = When cleared, no TIMER interrupt caused by CTOF bit set will begenerated. This bit is cleared by reset.
RTIF — Real Time Interrupt FlagThe RTIF is a read-only flag bit.
1 = Set when the output of the chosen (1 of 4 selections) Real TimeInterrupt stage goes active. A TIMER Interrupt request will begenerated if RTIE is also set.
0 = Reset by writing a logical one to the RTIF acknowledge bit, RTIFR.Writing to the RTIF flag bit has no effect on its value. This bit iscleared by reset.
CTOF — Timer Overflow FlagThe CTOF is a read-only flag bit.
1 = Set when the 8-bit ripple counter rolls over from $FF to $00. ATIMER Interrupt request will be generated if CTOFE is also set.
0 = Reset by writing a logical one to the CTOF acknowledge bit,CTOFR. Writing to the CTOF flag bit has no effect on its value. Thisbit is cleared by reset.
8.4 OPERATION DURING STOP MODE
When STOP is exited by an external interrupt or an LVR reset or an externalRESET, the internal oscillator will resume, followed by a 224 or 4064 internal pro-cessor oscillator stabilization delay.
8.5 COP CONSIDERATION DURING STOP MODE
In STOP mode, the clock to the Watchdog Timer is stopped and is thereforeimpossible to generate COP reset when in STOP mode. The COP function willresume 224 or 4064 cycles after exiting from STOP.
MOTOROLA MULTI-FUNCTION TIMER MC68HC05JB38-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 916-BIT TIMER
This 16-bit Programmable Timer (Timer1) has an Input Capture function and anOutput Compare function. Figure 9-1 shows a block diagram of the 16-bitprogrammable timer.
Figure 9-1. Programmable Timer Block Diagram
IED
G
ICIE
OC
IE
TOIE
TMRH ($0018) TMRL ($0019)
16-BIT COUNTER ÷ 4INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REGISTER
TIMER
REQUEST
OV
ER
FLO
W (
TOF
)
RESET
CLOCK
INTERRUPT
ACRH ($001A) ACRL ($001B)
16-BIT COMPARATOR
OCRH ($0016) OCRL ($0017)
EDGESELECT
& DETECT
ICF
OC
F
TOF
TIMER STATUS REGISTER
IED
G
ICF
OC
F
$0012 $0013
INTERNAL DATA BUS
LOGIC
ICRH ($0014) ICRL ($0015)
PC0/OCMPMUX
PORT-C LOGIC
OCMPO
PB0/TCAP
SIGNALCONDITIONING
TCMPE(bit7 at $0E)
MC68HC05JB3 16-BIT TIMER MOTOROLAREV 1 9-1
GENERAL RELEASE SPECIFICATION November 5, 1998
The basis of the 16-bit Timer is a 16-bit free-running counter which increases incount with each internal bus clock cycle. The counter is the timing reference forthe input capture and output compare functions. The input capture and outputcompare functions provide a means to latch the times at which external eventsoccur, to measure input waveforms, and to generate output waveforms and timingdelays. Software can read the value in the 16-bit free-running counter at any timewithout affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture andoutput compare functions are pairs of 8-bit registers. Each register pair containsthe high and low byte of that function. Generally, accessing the low byte of a spe-cific timer function allows full control of that function; however, an access of thehigh byte inhibits that specific timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four pres-caler, the counter rolls over every 262,144 internal clock cycles. Timer resolutionwith a 4MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state arecontrolled by the timer control register (TCR) located at $0012 and the status ofthe interrupt flags can be read from the timer status register (TSR) located at$0013.
9.1 TIMER REGISTERS (TMRH, TMRL)
The functional block diagram of the 16-bit free-running timer counter and timerregisters is shown in Figure 9-2. The timer registers include a transparent bufferlatch on the LSB of the 16-bit timer counter.
Figure 9-2. Programmable Timer Counter Block Diagram
TOIE
TMRH ($0018) TMR LSB
16-BIT COUNTER ÷ 4INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
OVERFLOW (TOF)
RESETCLOCK
INTERRUPT
TMRL ($0019)
TOF
TIMER STATUS REG.
$0012 $0013
INTERNAL
($FFFC)
DATA
READTMRH
READTMRL
READ
LATCH
BUS
MOTOROLA 16-BIT TIMER MC68HC05JB39-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locationswhich contain the current high and low bytes of the 16-bit free-running counter.Writing to the timer registers has no effect. Reset of the device presets the timercounter to $FFFC.
The TMRL latch is a transparent read of the LSB until the a read of the TMRHtakes place. A read of the TMRH latches the LSB into the TMRL location until theTMRL is again read. The latched value remains fixed even if multiple reads of theTMRH take place before the next read of the TMRL. Therefore, when reading theMSB of the timer at TMRH the LSB of the timer at TMRL must also be read tocomplete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and beginscounting after the oscillator start-up delay. Because the counter is sixteen bits andpreceded by a fixed divide-by-four prescaler, the value in the counter repeatsevery 262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overflowflag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt ifthe timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flagbit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in anyorder or any number of times does not have any effect on the 16-bit free-runningcounter.
NOTE
To prevent interrupts from occurring between readings of the TMRH and TMRL,set the I bit in the condition code register (CCR) before reading TMRH and clearthe I bit after reading TMRL.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TMRH R TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
$0018 W
reset: 1 1 1 1 1 1 1 1
TMRL R TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0
$0019 W
reset: 1 1 1 1 1 1 0 0
Figure 9-3. Programmable Timer Counter Registers (TMRH, TMRL)
MC68HC05JB3 16-BIT TIMER MOTOROLAREV 1 9-3
GENERAL RELEASE SPECIFICATION November 5, 1998
9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternatecounter registers is shown in Figure 9-4. The alternate counter registers behavethe same as the timer registers, except that any reads of the alternate counter willnot have any effect on the TOF flag bit and Timer interrupts. The alternate counterregisters include a transparent buffer latch on the LSB of the 16-bit timer counter.
Figure 9-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-onlylocations which contain the current high and low bytes of the 16-bit free-runningcounter. Writing to the alternate counter registers has no effect. Reset of thedevice presets the timer counter to $FFFC.
The ACRL latch is a transparent read of the LSB until the a read of the ACRHtakes place. A read of the ACRH latches the LSB into the ACRL location until theACRL is again read. The latched value remains fixed even if multiple reads of theACRH take place before the next read of the ACRL. Therefore, when reading theMSB of the timer at ACRH the LSB of the timer at ACRL must also be read tocomplete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and beginscounting after the oscillator start-up delay. Because the counter is sixteen bits andpreceded by a fixed divide-by-four prescaler, the value in the counter repeatsevery 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not haveany effect on the 16-bit free-running counter or the TOF flag bit.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ACRH R ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
$001A W
reset: 1 1 1 1 1 1 1 1
ACRL R ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0
$001B W
reset: 1 1 1 1 1 1 0 0
Figure 9-5. Alternate Counter Registers (ACRH, ACRL)
ACRH ($001A) TMR LSB
16-BIT COUNTER ÷ 4INTERNAL
(fOSC ÷ 2)
RESETCLOCK
ACRL ($001B)
INTERNAL
($FFFC)
DATA
READACRH
READACRL
READ
LATCH
BUS
MOTOROLA 16-BIT TIMER MC68HC05JB39-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
NOTE
To prevent interrupts from occurring between readings of the ACRH and ACRL,set the I bit in the condition code register (CCR) before reading ACRH and clearthe I bit after reading ACRL.
9.3 INPUT CAPTURE REGISTERS
Figure 9-6. Timer Input Capture Block Diagram
The input capture function is a technique whereby an external signal (connectedto PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-ble to relate the timing of an external signal to the internal counter value, andhence to elapsed time.
NOTE
Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0DDR or Data Register can cause an unwanted TCAP interrupt. This can beavoided by clearing the ICIE bit before changing the configuration of PB0, andclearing any pending interrupts before enabling ICIE.
The signal on the TCAP pin is first directed to a schmitt trigger or a voltagecomparator as shown in Figure 9-7. Setting the TCMPE bit to “1” will enable thecomparator and the VDD/2 reference voltage.
ICIE
ICRH ($0014)
16-BIT COUNTER ÷ 4 INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
INPUT CAPTURE (ICF)
RESET
CLOCK
INTERRUPT
ICRL ($0015)
ICF
TIMER STATUS REG.
$0012 $0013
INTERNAL
($F
FF
C)
DATA
READICRH
READICRLLATCH
BUS
IED
G
EDGESELECT
& DETECTLOGIC
IED
GINTERNAL
DATABUS
SIGNALCONDITIONING
PB0/TCAP
TCMPE(bit7 at $0E)
MC68HC05JB3 16-BIT TIMER MOTOROLAREV 1 9-5
GENERAL RELEASE SPECIFICATION November 5, 1998
TCMPE — Timer Input Capture Comparator Enable1 = Timer input capture comparator is selected.0 = Timer input capture comparator schmitt trigger is selected.
NOTE
When the comparator and VDD/2 reference are enabled, PB0 pin will automaticallybecomes an input pin, irrespective of DDR setting. However, it is recommended toset PB0 as an input first (via DDR), before enabling the comparator. A read of PB0will reflect the TCAP pin status, not the PB0 register bit.
The comparator uses the VDD/2 reference as the compare voltage, resulting in atypical output as shown in Figure 9-8.
Switching off the VDD/2 voltage reference by clearing TCMPE=0 will further savepower when the MCU is in a low power mode.
Figure 9-7. TCAP Input Signal Conditioning
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OIER RTCMPE VREF2 VREF1 VREF0 OIE3 OIE2 OIE1 OIE0
$000E W
reset: 0 0 0 0 0 0 0 0
+–
MUX
PB0/TCAP
VoltageReference
VREF
EN
PB0 I/OPORT LOGIC
TCMPE bit
VDD ÷ 2
Schmitt Trigger
ComparatorTo edge select anddetect logic
MOTOROLA 16-BIT TIMER MC68HC05JB39-6 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 9-8. TCAP Input Comparator Output
When the input capture circuitry detects an active edge on the TCAP pin, itlatches the contents of the free-running timer counter registers into the input cap-ture registers as shown in Figure 9-6.
Latching values into the input capture registers at successive edges of the samepolarity measures the period of the selected input signal. Latching the counter val-ues at successive edges of opposite polarity measures the pulse width of the sig-nal.
The input capture registers are made up of two 8-bit read-only registers (ICRH,ICRL) as shown in Figure 9-9. The input capture edge detector contains a Schmitttrigger to improve noise immunity. The edge that triggers the counter transfer isdefined by the input edge bit (IEDG) in the TCR. Reset does not affect the con-tents of the input capture registers.
The result obtained by an input capture will be one count higher than the value ofthe free-running timer counter preceding the external transition. This delay isrequired for internal synchronization. Resolution is affected by the prescaler,allowing the free-running timer counter to increment once every four internal clockcycles (eight oscillator clock cycles).
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ICRH R ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0
$0014 W
reset: U U U U U U U U
ICRL R ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0
$0015 W
reset: U U U U U U U U
U = UNAFFECTED BY RESET
Figure 9-9. Input Capture Registers (ICRH, ICRL)
VDD ÷ 2
VDD
Output of Comparator
Signal on TCAP pin
Time
MC68HC05JB3 16-BIT TIMER MOTOROLAREV 1 9-7
GENERAL RELEASE SPECIFICATION November 5, 1998
Reading the ICRH inhibits further captures until the ICRL is also read. Readingthe ICRL after reading the timer status register (TSR) clears the ICF flag bit. doesnot inhibit transfer of the free-running counter. There is no conflict between read-ing the ICRL and transfers from the free-running timer counters. The input captureregisters always contain the free-running timer counter value which correspondsto the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH and ICRL, setthe I bit in the condition code register (CCR) before reading ICRH and clear theI bit after reading ICRL.
9.4 OUTPUT COMPARE REGISTERS
The Output Compare function is a means of generating an interrupt when the 16-bit timer counter reaches a selected value as shown in Figure 9-10. Softwarewrites the selected value into the output compare registers. On every fourth inter-nal clock cycle (every eight oscillator clock cycle) the output compare circuitrycompares the value of the free-running timer counter to the value written in theoutput compare registers. When a match occurs, the output compare interruptflag, OCF is set. A timer interrupt request to the CPU is generated if the outputcompare interrupt enable is set, i.e. OCIE=1.
Port pin, PC0 is configured as the OCMP output pin when the OCMPO bit (bit7 at$06) is set to “1”. The OCMP output reflects the logic of the output compare inter-rupt flag, OCF, as shown in Figure 9-10.
OCMPO — OCMP Output Enable1 = PC0 is OCMP pin, OCF from 16-bit timer output compare.0 = PC0 is standard I/O pin, from Port-C data register.
Software can use the output compare register to measure time periods, to gener-ate timing delays, or to generate a pulse of specific duration or a pulse train ofspecific frequency and duty cycle.
Writing to the OCRH before writing to the OCRL inhibits timer compares until theOCRL is written. Reading or writing to the OCRL after reading the TSR will clearthe output compare flag bit (OCF).
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DDRC ROCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0
$0006 W
reset: 0 0 0 0 0 0 0 0
MOTOROLA 16-BIT TIMER MC68HC05JB39-8 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 9-10. Timer Output Compare Block Diagram
To prevent OCF from being set between the time it is read and the time the outputcompare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This alsoclears the OCF flag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown below.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OCRH ROCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
$0016 W
reset: U U U U U U U U
OCRL ROCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
$0017 W
reset: U U U U U U U U
U = UNAFFECTED BY RESET
Figure 9-11. Output Compare Registers (OCRH, OCRL)
OC
IE
OCRH ($0016)
16-BIT COUNTER ÷ 4INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
OUTPUT COMPARE
RESET
CLOCK
INTERRUPT
OCRL ($0017)
OC
FTIMER STATUS REG.
$0012 $0013
INTERNAL
($FFFC)
DATA
R/WOCRH
R/WOCRL
BUS
16-BIT COMPARATOR
(OCF)
PC0/OCMPMUX
OCMPO (bit7 at $06)
PORT-C LOGIC
MC68HC05JB3 16-BIT TIMER MOTOROLAREV 1 9-9
GENERAL RELEASE SPECIFICATION November 5, 1998
9.5 TIMER CONTROL REGISTER (TCR)
The timer control register is shown in Figure 9-12 performs the following func-tions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Control the active edge polarity of the TCAP signal on pin PB0/TCAP
Reset clears all the bits in the TCR with the exception of the IEDG bit which isunaffected.
ICIE - INPUT CAPTURE INTERRUPT ENABLEThis read/write bit enables interrupts caused by an active signal on the PB0/TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled.0 = Input capture interrupts disabled.
OCIE - OUTPUT COMPARE INTERRUPT ENABLEThis read/write bit enables interrupts caused by a successful compare betweenthe timer counter and the output compare registers. Reset clears the OCIE bit.
1 = Output compare interrupts enabled.0 = Output compare interrupts disabled.
TOIE - TIMER OVERFLOW INTERRUPT ENABLEThis read/write bit enables interrupts caused by a timer overflow. Reset clearsthe TOIE bit.
1 = Timer overflow interrupts enabled.0 = Timer overflow interrupts disabled.
9B......B7B6BF......9A
161317
SEI......STALDASTX......CLI
OCRHTSROCRL
DISABLE INTERRUPTS..........INHIBIT OUTPUT COMPAREARM OCF FLAG FOR CLEARINGREADY FOR NEXT COMPARE, OCF CLEARED..........ENABLE INTERRUPTS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TCR RICIE OCIE TOIE
0 0 0IEDG
0
$0012 W
reset: 0 0 0 0 0 0 Unaffected 0
Figure 9-12. Timer Control Register (TCR)
MOTOROLA 16-BIT TIMER MC68HC05JB39-10 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
IEDG - INPUT CAPTURE EDGE SELECTThe state of this read/write bit determines whether a positive or negative transi-tion on the TCAP pin triggers a transfer of the contents of the timer register tothe input capture register. Reset has no effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.0 = Negative edge (high to low transition) triggers input capture.
9.6 TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in Figure 9-13 contains flags for the follow-ing events:
• An active signal on the PB0/TCAP pin, transferring the contents of thetimer registers to the input capture registers.
• A match between the 16-bit counter and the output compare registers
• An overflow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change thestate of any of the flag bits in the TSR.
ICF - INPUT CAPTURE FLAGThe ICF bit is automatically set when an edge of the selected polarity occurs onthe PB0/TCAP pin. Clear the ICF bit by reading the timer status register withthe ICF set, and then reading the low byte (ICRL, $0015) of the input captureregisters. Reset has no effect on ICF.
OCF - OUTPUT COMPARE FLAGThe OCF bit is automatically set when the value of the timer registers matchesthe contents of the output compare registers. Clear the OCF bit by reading thetimer status register with the OCF set, and then accessing the low byte (OCRL,$0017) of the output compare registers. Reset has no effect on OCF.OCF status will be latched to the output of OCMP (PC0 pin) if the OCMPO bit isset to “1” (bit7 at $06).
TOF - TIMER OVERFLOW FLAGThe TOF bit is automatically set when the 16-bit timer counter rolls over from$FFFF to $0000. Clear the TOF bit by reading the timer status register with theTOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.Reset has no effect on TOF.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TSR R ICF OCF TOF 0 0 0 0 0
$0013 W
reset: U U U 0 0 0 0 0
U = UNAFFECTED BY RESET
Figure 9-13. Timer Status Registers (TSR)
MC68HC05JB3 16-BIT TIMER MOTOROLAREV 1 9-11
GENERAL RELEASE SPECIFICATION November 5, 1998
9.7 TIMER OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may gener-ate an interrupt to trigger the MCU out of the WAIT mode.
9.8 TIMER OPERATION DURING STOP MODE
When the MCU enters the STOP mode the free-running counter stops counting(the internal processor clock is stopped). It remains at that particular count valueuntil the STOP mode is exited by applying a low signal to the IRQ pin, at whichtime the counter resumes from its stopped value as if nothing had happened. IfSTOP mode is exited via an external reset (logic low applied to the RESET pin)the counter is forced to $FFFC.
If a valid input capture edge occurs at the PB0/TCAP pin during the STOP modethe input capture detect circuitry will be armed. This action does not set any flagsor “wake up” the MCU, but when the MCU does “wake up” there will be an activeinput capture flag (and data) from the first valid edge. If the STOP mode is exitedby an external reset, no input capture flag or data will be present even if a validinput capture edge was detected during the STOP mode.
MOTOROLA 16-BIT TIMER MC68HC05JB39-12 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 10UNIVERSAL SERIAL BUS MODULE
This USB Module is designed for USB application in LS products. With minimizedsoftware effort, it can fully comply with USB LS device specification. See USBspecification version 1.0 for the detail description of USB.
10.1 FEATURES
• Integrated 3.3 Volt Regulator with 3.3V Output Pin
• Integrated USB transceiver supporting Low Speed functions
• USB Data Control Logic
– Packet decoding/generation
– CRC generation and checking
– NRZI encoding/decoding
– Bit-stuffing
• USB reset support
• Control Endpoint 0 and Interrupt Endpoints 1 and 2
• Two 8-byte transmit buffers
• One 8-byte receive buffer
• Suspend and resume operations
• Remote Wake-up support
• USB generated interrupts
• Transaction interrupt driven
• Resume interrupt
• End of Packet interrupt
• STALL, NAK, and ACK handshake generation
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-1
GENERAL RELEASE SPECIFICATION November 5, 1998
10.2 OVERVIEW
This section provides an overview of the Universal Serial Bus (USB) module in theMC68HC05JB3. This USB module is designed to serve as a low-speed (LS) USBdevice per the Universal Serial Bus Specification Rev 1.0. Three types of USBdata transfers are supported: control, interrupt, and bulk (transmit only).Endpoint 0 functions as a receive/transmit control endpoint. Endpoints 1 and 2can function as interrupt or bulk, but only in the transmit direction.
A block diagram of the USB module is shown Figure 10-1. The USB modulemanages communications between the host and the USB function. The module ispartitioned into four functional blocks. These blocks consist of a 3.3 volt regulator,a dual function transceiver, the USB control logic, and the endpoint registers. Theblocks are further detailed in Section 10.4.
Figure 10-1. USB Block Diagram
D+
D–
US
B C
ON
TR
OL
LOG
IC
TRA
NS
CE
IVE
R
RCV
VPIN
VMIN
VPOUT
VMOUT
REGULATOR 3.3V OUTCPU BUS USB REGISTERS
USBUpstreamPort
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
10.2.1 USB Protocol
Figure 10-2 shows the various transaction types supported by theMC68HC05JB3 USB module. The transactions are portrayed as error free. Theeffect of errors in the data flow are discussed later.
Figure 10-2. Supported Transaction Types per Endpoint
Each USB transaction is comprised of a series of packets. The MC68HC05JB3USB module supports the packet types shown in Figure 10-3. Token packets aregenerated by the USB host and decoded by the USB device. Data andHandshake packets are both decoded and generated by the USB devicedepending on the type of transaction.
SETUP
IN
OUT
DATA0/1
DATA0 DATA1ACK
DATA1
OUT ACKOUT DATA0 ACK
ACK
DATA0/1
ENDPOINT 0 TRANSACTIONS:
Control Write
Control Read
No-Data Control
ENDPOINTS 1 & 2 TRANSACTIONS:
Interrupt
Bulk Transmit
IN ACK
KEY:
Unrelated BusTraffic
HostGenerated
DeviceGenerated
ACK
SETUP
OUT
IN
DATA0/1
DATA0 DATA1ACK
DATA1
IN ACKIN DATA0 ACK
ACK
ACK
SETUP INDATA0 DATA1ACK ACK
DATA0/1IN ACK
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-3
GENERAL RELEASE SPECIFICATION November 5, 1998
Figure 10-3. Supported USB Packet Types
The following sections will give some detail on each segment used to form acomplete USB transaction.
10.2.1.1 Sync Pattern
The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as asynchronization pattern and is prefixed to each packet. This pattern is equivalentto a data pattern of seven 0’s followed by a 1 (0x80).
Figure 10-4. Sync Pattern
The start of a packet (SOP) is signaled by the originating port by driving the D+and D– lines from the idle state (also referred to as the “J” state) to the oppositelogic level (also referred to as the “K” state). This switch in levels represents thefirst bit of the Sync field. Figure 10-5 shows the data signaling and voltage levelsfor the start of packet and the sync pattern.
Token Packet:
IN
OUT SYNC PID PID ADDR ENDP CRC5 EOP
SETUP
Data Packet:
DATA0 SYNC PID PID DATA CRC5 EOP
DATA1 0 - 8 bytes
Handshake Packet:
ACK
NAK SYNC PID PID EOP
STALL
SYNC PATTERN
PID0 PID1IdleNRZI DataEncoding
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 10-5. SOP, Sync Signaling and Voltage Levels
10.2.1.2 Packet Identifier Field
The Packet Identifier field is an eight bit number comprised of the four bit packetidentification (PID) and its complement. The field follows the sync pattern anddetermines the direction and type of transaction on the bus. Table 10-1 shows thePID values for the supported packet types.
Table 10-1. Supported Packet Identifiers
10.2.1.3 Address Field (ADDR)
The Address field is a seven bit number that is used to select a particular USBdevice. This field is compared to the lower seven bits of the UADDR register todetermine if a given transaction is targeting the MC68HC05JB3 USB device.
PID Value PID Type
%1001 IN Token
%0001 OUT Token
%1101 SETUP Token
%0011 DATA0 Packet
%1011 DATA1 Packet
%0010 ACK Handshake
%1010 NAK Handshake
%1110 STALL Handshake
END OF SYNC
FIRST BIT OF PACKET
SOPBUS IDLE
VOH (min)
VSE (max)
VSE (min)
VOL (min)
VSS
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-5
GENERAL RELEASE SPECIFICATION November 5, 1998
10.2.1.4 Endpoint Field (ENDP)
The Endpoint field is a four bit number that is used to select a particular endpointwithin a USB device. For the MC68HC05JB3, this will be a binary numberbetween zero and two inclusive. Any other value will cause the transaction to beignored.
10.2.1.5 Cyclic Redundancy Check (CRC)
Cyclic Redundancy Checks are used to verify the address and data stream of aUSB transaction. This field is five bits wide for token packets and sixteen bits widefor data packets. CRCs are generated in the transmitter and sent on the USB datalines after both the endpoint field and the data field. Figure 10-6 shows how thefive bit CRC value is calculated from the data stream and verified for the addressand endpoint fields of a token packet. Figure 10-7 shows how the sixteen bit CRCvalue is calculated and either transmitted or verified for the data packet of a giventransaction.
Figure 10-6. CRC Block Diagram for Address and Endpoint Fields
0 0 1 0 1
0 1 1 0 0
0
5
5
5
5
next bitData Stream
Update every bit timeReset to ones at SOP
Equal?Good CRC Bad CRC
5
Y N
Expected Residual:
Generator Polynomial:
MUX10
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-6 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 10-7. CRC Block Diagram for Data Packets
10.2.1.6 End Of Packet (EOP)
The single-ended 0 (SE0) state is used to signal an end of packet (EOP). Thesingle-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP willbe signaled by driving D+ and D– to the single-ended 0 state for two bit timesfollowed by driving the lines to the idle state for one bit time. The transition fromthe single-ended 0 to the idle state defines the end of the packet. The idle state isasserted for one bit time and then both the D+ and D– output drivers are placed intheir high-impedance state. The bus termination resistors hold the bus in the idlestate. Figure 10-8 shows the data signaling and voltage levels for an end ofpacket transaction.
MUX
0
16
16
16
16
10
next bit
Input / Output
Update every bit timeReset to ones at SOP
Equal?Good CRC Bad CRC
16
Y N
Expected Residual:
Generator Polynomial:
Data Stream
Output Data Stream
CRC16 TransmittedMSB first after final data byte.
TRANSMIT
RECEIVE
0 0 0 0 01 0 0 0 0 0 0 0 1 0 1
0 0 0 0 01 0 0 0 0 0 0 1 1 0 1
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-7
GENERAL RELEASE SPECIFICATION November 5, 1998
Figure 10-8. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width ismeasured with the same capacitive load used for maximum rise and fall times andis measured at the same level as the differential signal crossover points of thedata lines.
Figure 10-9. EOP Width Timing
10.2.2 Reset Signaling
A reset is signaled on the bus by the presence of an extended SE0 at the USBdata pins of a device. The reset signaling is specified to be present for a minimumof 10 ms. An active device (powered and not in the suspend state) seeing asingle-ended zero on its USB data inputs for more than 2.5µs may treat that signalas a reset, but must have interpreted the signaling as a reset within 5.5 µs. For aLow speed device, an SE0 condition between 4 and 8 low speed bit timesrepresents a valid USB reset.
A USB sourced reset will hold the MC68HC05JB3 in reset for the duration of thereset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will beset after the internal reset is removed (See Section 10.5.2 for more detail).
After a reset is removed, the device will be in the attached, but not yet addressedor configured state (refer to Section 9.1 of the USB specification). The device mustbe able to accept a device address via a SET_ADDRESS command (refer tosection 9.4 of the USB specification) no later than 10 ms after the reset isremoved.
BUS DRIVEN TO LAST BIT OF
BUS IDLE
EOPSTROBE
PACKETIDLE STATE
BUS FLOATS
VOH (min)
VSE (max)
VSE (min)
VOL (min)
VSS
EOPWIDTH
tPeriod
DIFFERENTIALDATA LINES
DATACROSSOVER
LEVEL
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-8 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Reset can wake a device from the suspended mode. A device may take up to10ms to wake up from the suspended state.
10.2.3 Suspend
The MC68HC05JB3 supports suspend mode for low power. Suspend modeshould be entered when the USB data lines are in the idle state for more than 3.0ms. Entry into Suspend mode is controlled by the SUSPND bit in the USBInterrupt Register. Any low speed bus activity should keep the device out of thesuspend state. Low speed devices are kept awake by periodic low speed EOPsignals from the host. This is referred to as Low speed keep alive (refer to Section11.2.5.1 of the USB specification).
Firmware should monitor the EOPF flag and enter suspend mode by setting theSUSPND bit if an EOP is not detected for 3 ms.
Per the USB specification, the MC68HC05JB3 is required to draw less than500µA from the VDD supply when in the suspend state. This includes the currentsupplied by the voltage regulator to the 15 KΩ to ground termination resistorsplaced at the host end of the USB bus. This low current requirement means thatfirmware is responsible for entering STOP mode once the USB module has beenplaced in the suspend state.
10.2.4 Resume After Suspend
The MC68HC05JB3 can be activated from the suspend state by normal busactivity, a USB reset signal, or by a forced resume driven from theMC68HC05JB3.
10.2.4.1 Host Initiated Resume
The host signals resume by initiating resume signalling (“K” state) for at least 20ms followed by a standard low speed EOP signal. This 20 ms ensures that alldevices in the USB network are awakened.
After resuming the bus, the host must begin sending bus traffic within 3 ms toprevent the device from re-entering suspend mode.
10.2.4.2 USB Reset Signalling
Reset can wake a device from the suspended mode. A device may take up to 10ms to wake up from the suspended state.
10.2.4.3 Remote Wake-up
The MC68HC05JB3 also supports the remote wake-up feature. The firmware hasthe ability to exit suspend mode by signaling a resume state to the upstream Hostor Hub. A non-idle state (“K” state) on the USB data lines is accomplished byasserting the FRESUM bit in the UCR1 register.
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-9
GENERAL RELEASE SPECIFICATION November 5, 1998
When using the remote wake-up capability, the firmware must wait for at least 5ms after the bus is in the idle state before sending the remote wake-up resumesignaling. This allows the upstream devices to get into their suspend state andprepare for propagating resume signaling. The FRESUM bit should be asserted tocause the resume state on the USB data lines for at least 10ms, but not more than15ms. Note that the resume signalling is controlled by the FRESUM bit andmeeting the timing specifications is dependent on the firmware. When FRESUM iscleared by firmware, the data lines will return to their high impedance state. Referto Section 10.5.5 for more information about how the Force Resume (FRESUM)bit can be used to initiate the remote wake-up feature.
10.2.5 Low Speed Device
Externally, low speed devices are configured by the position of a pull-up resistoron the USB D– pin of the MC68HC05JB3. Low speed devices are terminated asshown in Figure 10-10 with the pull-up on the D– line.
Figure 10-10. External Low Speed Device Configuration
For low speed transmissions, the transmitter’s EOP width must be between1.25µs and 1.50µs. These ranges include timing variations due to differentialbuffer delay and rise/fall time mismatches and to noise and other random effects.A low speed receiver must accept a 670ns wide SE0 followed by a J transition asa valid EOP. An SE0 narrower than 330ns or an SE0 not followed by a J transitionmust be rejected as an EOP. An EOP between 330ns and 670ns may be rejectedor accepted as above. Any SE0 that is 2.5µs or wider is automatically a reset.
10.3 CLOCK REQUIREMENTS
The low speed data rate is nominally 1.5 Mbs. The OSCXCLK signal driven by theoscillator circuits is the clock source for the USB module and requires that a 6MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permittedfrequency tolerance for low speed functions is approximately ±1.5% (15000 ppm).This tolerance includes inaccuracies from all sources: initial frequency accuracy,crystal capacitive loading, supply voltage on the oscillator, temperature, andaging. The jitter in the low speed data rate must be less than 10 ns. This toleranceallows the use of resonators in low cost, low speed devices.
10.4 HARDWARE DESCRIPTION
The USB module as previously shown in Figure 10-1 contains four functionalblocks: a 3.3 volt regulator, a LS USB transceiver, the USB control logic, and theUSB registers. The following will detail the function of the regulator, transceiverand control logic. See Section 10.5 for the register discussion.
1.5KΩD+
D–
3.3V Regulator Out
USB Low Speed Cable
MC68HC05JB3
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-10 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
10.4.1 Voltage Regulator
The USB data lines are required by the USB Specification to have a maximumoutput voltage between 2.8V and 3.6V. The data lines are also required to have anexternal 1.5KΩ pullup resistor connected between a data line and a voltagesource between 3.0V and 3.6V. Since the power provided by the USB cable isspecified to be between 4.4V and 5.0V, an on-chip regulator is used to drop thevoltage to the appropriate level for sourcing the USB transceiver and externalpullup resistor. An output pin driven by the regulator voltage is provided to sourcethe 1.5KΩ external resistor. Figure 10-11 shows the worst case electricalconnection for the voltage regulator.
This regulator can be switched off by user program to save power when the deviceis in suspend mode. Please note that if the regulator is off, the D– line should betied to another voltage source with an external pull-up resistor.
VROFF — USB 3.3V Voltage ReferenceThe 3.3V Voltage Regulator for the USB transmitter and external D– pull-up canbe switched off to reduce power consumption when device is in suspend mode.
1 = Disable 3.3V regulator.0 = Enables 3.3V regulator.
Figure 10-11. Regulator Electrical Connections
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DDRC ROCMPO VROFF DDRC3 DDRC2 DDRC1 DDRC0
$0006 W
reset: 0 0 0 0 0 0 0 0
LSTransceiver
3.3V
R2 R2
R1
R1 = 1.5KΩ ±5%
R2 = 15KΩ ±5%
Regulator USB Data Lines
Hostor
HubUSB Cable
4.4VVROFF
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-11
GENERAL RELEASE SPECIFICATION November 5, 1998
10.4.2 USB Transceiver
The USB transceiver provides the physical interface to the USB D+ and D– datalines. The transceiver is composed of two parts: an output drive circuit and adifferential receiver.
10.4.2.1 Output Driver Characteristics
The USB transceiver uses a differential output driver to drive the USB data signalonto the USB cable. The static output swing of the driver in its low state is belowthe VOL of 0.3 V with a 1.5 kΩ load to 3.6 V and in its high state is above the VOHof 2.8 V with a 15 kΩ load to ground. The output swings between the differentialhigh and low state are well balanced to minimize signal skew. Slew rate control onthe driver is used to minimize the radiated noise and cross talk. The driver’soutputs support three-state operation to achieve bi-directional half duplexoperation. The driver can tolerate a voltage on the signal pins of –0.5 V to 3.8 Vwith respect to local ground reference without damage.
10.4.2.2 Low Speed (1.5 Mbs) Driver Characteristics
The rise and fall time of the signals on this cable are greater than 75 ns to keepRFI emissions under FCC class B limits, and less than 300 ns to limit timingdelays and signaling skews and distortions. The driver reaches the specified staticsignal levels with smooth rise and fall times, and minimal reflections and ringingwhen driving the cable. This driver is used only on network segments between lowspeed devices and the ports to which they are connected.
Figure 10-12. Low Speed Driver Signal Waveforms
10.4.3 Receiver Characteristics
USB data transmission is done with differential signals. A differential input receiveris used to accept the USB data signal. A differential 1 on the bus is represented byD+ being at least 200 mV more positive than D– as seen at the receiver, and adifferential 0 is represented by D– being at least 200 mV more positive than D+ asseen at the receiver. The signal cross over point must be between 1.3V and 2.0V.
ONE BITTIME
(1.5 Mb/s)
SIGNAL PINS PASS OUTPUT SPEC
LEVELS WITH MINIMALREFLECTIONS AND RINGING
VSE (min)
VSE (max)
VSS
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-12 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
The receiver features an input sensitivity of 200 mV when both differential datainputs are in the range of 0.8 V to 2.5 V with respect to the local ground reference.This is called the common mode input voltage range. Proper data reception is alsoachieved when the differential data lines are outside the common mode range, asshown in Figure 10-13. The receiver can tolerate static input voltages between–0.5V to 3.8 V with respect to its local ground reference without damage. Inaddition to the differential receiver, there is a single-ended receiver (schmitttrigger) for each of the two data lines.
Figure 10-13. Differential Input Sensitivity Over Entire Common Mode Range
10.4.3.1 Receiver Data Jitter
The data receivers for all types of devices must be able to properly decode thedifferential data in the presence of jitter. The more of the bit cell that any data edgecan occupy and still be decoded, the more reliable the data transfer will be. Datareceivers are required to decode differential data transitions that occur in awindow plus and minus a nominal quarter bit cell from the nominal (centered) dataedge position.
Jitter will be caused by the delay mismatches and by mismatches in the sourceand destination data rates (frequencies). The receive data jitter budget for lowspeed is given in the electrical section of the this specification. The specificationincludes the consecutive (next) and paired transition values for each source ofjitter.
10.4.3.2 Data Source Jitter
The source of data can have some variation (jitter) in the timing of edges of thedata transmitted. The time between any set of data transitions isN x TPERIOD ± jitter time, where ‘N’ is the number of bits between the transitionsand TPERIOD is defined as the actual period of the data rate. The data jitter is
COMMON MODE INPUT VOLTAGE (VOLTS)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
1.0
0.8
0.6
0.4
0.2
MIN
IMU
M D
IFFE
REN
TIAL
SEN
SITI
VITY
(VO
LTS)
0
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-13
GENERAL RELEASE SPECIFICATION November 5, 1998
measured with the same capacitive load used for maximum rise and fall times andis measured at the crossover points of the data lines as shown in Figure 10-14.
Figure 10-14. Data Jitter
For low speed transmissions, the jitter time for any consecutive differential datatransitions must be within ±25 ns and within ±10 ns for any set of paireddifferential data transitions. These jitter numbers include timing variations due todifferential buffer delay, rise/fall time mismatches, internal clock source jitter, andto noise and other random effects.
10.4.3.3 Data Signal Rise and Fall Time
The output rise time and fall time are measured between 10% and 90% of thesignal. Edge transition time for the rising and falling edges of low speed signals is75 ns (minimum) into a capacitive load (CL) of 50 pF and 300 ns (maximum) into acapacitive load of 350 pF. The rising and falling edges should be smoothtransitional (monotonic) when driving the cable to avoid excessive EMI.
Figure 10-15. Data Signal Rise and Fall Time
10.4.4 USB Control Logic
The USB control logic manages data movement between the CPU and thetransceiver. The control logic handles both transmit and receive operations on theUSB. It contains the logic used to manipulate the transceiver and the endpointregisters. The logic contains byte count buffers for transmit operations that loadthe active transmit endpoints byte count and use this to determine the number ofbytes to transfer. This same buffer is used for receive transactions to count thenumber of bytes received and, upon the end of the transaction, transfer thatnumber to the receive endpoints byte count register.
CONSECUTIVETRANSITIONS
tPeriod
DIFFERENTIALDATA LINES
CROSSOVERPOINTS
PAIREDTRANSITIONS
tR
DIFFERENTIALDATA LINES
tF
RISE TIME FALL TIME
10%
90% 90%
10%
LOW SPEED: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF
CL
CL
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-14 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
When transmitting, the control logic handles parallel to serial conversion, CRCgeneration, NRZI encoding, and bit stuffing.
When Receiving, the control logic handles Sync detection, packet identification,end of packet detection, bit (un)stuffing, NRZI decoding, CRC validation, andserial to parallel conversion. Errors detected by the control logic include bad CRC,time-out while waiting for EOP, and bit stuffing violations.
10.4.4.1 Data Encoding/Decoding
The USB employs NRZI data encoding when transmitting packets. In NRZIencoding, a 1 is represented by no change in level and a 0 is represented by achange in level. Figure 10-16 shows a data stream and the NRZI equivalent andFigure 10-17 is a flow diagram for NRZI. The high level represents the J state onthe data lines in this and subsequent figures showing NRZI encoding. A string ofzeros causes the NRZI data to toggle each bit time. A string of ones causes longperiods with no transitions in the data.
Figure 10-16. NRZI Data Encoding
Figure 10-17. Flow Diagram for NRZI
IDLEDATA
IDLENRZI
0 1 1 0 0 0 0 0 0 0 01 1 1 1 1
POWER UP
NO PACKETTRANSMISSION
IDLE
BEGIN PACKET
FETCH THEDATA BIT
NO YES
NO DATATRANSITION
TRANSITION
IS PACKAGETRANSFER
DONE?
NO YES
DATA
TRANSMISSION
IS DATABIT = 0?
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-15
GENERAL RELEASE SPECIFICATION November 5, 1998
10.4.4.2 Bit Stuffing
In order to ensure adequate signal transitions, bit stuffing is employed by thetransmitting device when sending a packet on the USB (see Figure 10-18 andFigure 10-19). A 0 is inserted after every six consecutive 1’s in the data streambefore the data is NRZI encoded to force a transition in the NRZI data stream.This gives the receiver logic a data transition at least once every seven bit times toguarantee the data and clock lock. The receiver must decode the NRZI data,recognize the stuffed bits, and discard them. Bit stuffing is enabled beginning withthe Sync Pattern and throughout the entire transmission. The data “one” that endsthe Sync Pattern is counted as the first one in a sequence. Bit stuffing is alwaysenforced, without exception. If required by the bit stuffing rules, a zero bit will beinserted even if it is the last bit before the end-of-packet (EOP) signal.
Figure 10-18. Bit Stuffing
IDLENRZI
ENCODEDDATA
BITSTUFFED
DATA
RAWDATA
STUFFED BIT
SYNC PATTERN PACKET DATA
PACKET DATASYNC PATTERN
PACKET DATASYNC PATTERNSIX ONES
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-16 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 10-19. Flow Diagram for Bit StuffingPOWER UP
NO PACKETTRANSMISSION
IDLE
NO YES
IS PACKAGETRANSFER
DONE?
NO YES
RESET THE BITCOUNTER TO 0
INSERT AZERO BIT
COUNTER = 6?
INCREMENTTHE COUNTER
= 0 = 1BIT VALUE?
GET NEXTBIT
RESET BITCOUNTER TO 0
BEGIN PACKETTRANSMISSION
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-17
GENERAL RELEASE SPECIFICATION November 5, 1998
10.5 I/O REGISTER DESCRIPTION
The USB Endpoint registers are comprised of a set of control/status registers andtwenty-four data registers that provide storage for the buffering of data betweenthe USB and the CPU. These registers are shown in Table 10-2.
Table 10-2. Register SummaryRegister Name Bit 7 6 5 4 3 2 1 Bit 0 Addr
USB Control Register 2(UCR2)
0 TX1ST 0ENABLE2 ENABLE1 STALL2 STALL1 $0037
TX1STR
USB Address Register(UADDR)
USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 $0038
USB Interrupt Register 0(UIR0)
TXD0F RXD0F RSTFSUSPND TXD0IE RXD0IE
0 0$0039
TXD0FR RXD0FR
USB Interrupt Register 1(UIR1)
TXD1F EOPF RESUMF 0TXD1IE EOPIE
0 0$003A
RESUMFR TXD1FR EOPFR
USB Control Register 0(UCR0)
T0SEQ STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 $003B
USB Control Register 1(UCR1)
T1SEQ ENDADD TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 $003C
USB Status Register(USR)
RSEQ SETUP 0 0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0$003D
USB Endpoint 0 DataRegister 0 (UE0D0)
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0$0020
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
↓ ↓USB Endpoint 0 Data
Register 7 (UE0D7)
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0$0027
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
USB Endpoint 1/2 DataRegister 0 (UE1D0)
$0028UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
↓ ↓USB Endpoint 1/2 Data
Register 7 (UE1D7)$002F
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
= Unimplemented
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-18 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
10.5.1 USB Address Register (UADDR)
USBEN — USB Module EnableThis read/write bit enables and disables the USB module and the USB pins.When USBEN is clear, the USB module will not respond to any tokens. Resetclears this bit.
1 = USB function enabled.0 = USB function disabled.
UADD6-UADD0 — USB Function AddressThese bits specify the USB address of the device. Reset clears these bits.
10.5.2 USB Interrupt Register 0 (UIR0)
TXD0F — Endpoint 0 Data Transmit FlagThis read only bit is set after the data stored in Endpoint 0 transmit buffers hasbeen sent and an ACK handshake packet from the host is received. Once thenext set of data is ready in the transmit buffers, software must clear this flag bywriting a logic 1 to the TXD0FR bit. To enable the next data packet transmis-sion, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake willbe returned in the next IN transaction.Reset clears this bit. Writing a logic 0 to TXD0F has no effect.
1 = Transmit on Endpoint 0 has occurred.0 = Transmit on Endpoint 0 has not occurred.
RXD0F — Endpoint 0 Data Receive FlagThis read only bit is set after the USB module has received a data packet andresponded with an ACK handshake packet. Software must clear this flag bywriting a logic 1 to the RXD0FR bit after all of the received data has been read.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UADDR RUSBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
$0038 W
reset: 0 0 0 0 0 0 0 0
Figure 10-20. USB Address Register (UADDR)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UIR0 R TXD0F RXD0F RSTFSUSPND TXD0IE RXD0IE
0 0
$0039 W TXD0FR RXD0FR
reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 10-21. USB Interrupt Register 0 (UIR0)
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-19
GENERAL RELEASE SPECIFICATION November 5, 1998
Software must also set RX0E bit to one to enable the next data packet recep-tion. If RXD0F bit is not cleared, a NAK handshake will be returned in the nextOUT transaction.Reset clears this bit. Writing a logic 0 to RXD0F has no effect.
1 = Receive on Endpoint 0 has occurred.0 = Receive on Endpoint 0 has not occurred.
RSTF — USB Reset FlagThis read only bit is set when a valid reset signal state is detected on the D+and D– lines. This reset detection will also generate an internal reset signal toreset the CPU and other peripherals including the USB module. This bit iscleared by writing a logic 1 to the RSTFR bit in the UCR2 register. This bit iscleared by a POR reset.
SUSPND — USB Suspend FlagTo save power, this read/write bit should be set by the software if a 3ms con-stant idle state is detected on USB bus. Setting this bit stops the clock to theUSB and causes the USB module to enter Suspend mode. Unnecessary ana-log circuitry will be powered down. Software must clear this bit after theResume flag (RESUMF) is set while this Resume interrupt flag is serviced.
TXD0IE — Endpoint 0 Transmit Interrupt EnableThis read/write bit enables the Transmit Endpoint 0 to generate a USB interruptwhen the TXD0F bit becomes set.
1 = USB interrupts enabled for Transmit Endpoint 0.0 = USB interrupts disabled for Transmit Endpoint 0.
RXD0IE — Endpoint 0 Receive Interrupt EnableThis read/write bit enables the Transmit Endpoint 0 to generate a USB interruptwhen the RXD0F bit becomes set.
1 = USB interrupts enabled for Receive Endpoint 0.0 = USB interrupts disabled for Receive Endpoint 0.
TXD0FR — Endpoint 0 Transmit Flag ResetWriting a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing alogic 0 to TXD0FR has no effect. Reset clears this bit.
RXD0FR — Endpoint 0 Receive Flag ResetWriting a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing alogic 0 to RXD0FR has no effect. Reset clears this bit.
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-20 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
10.5.3 USB Interrupt Register 1 (UIR1)
TXD1F — Endpoint 1/Endpoint 2 Data Transmit FlagThis read only bit is shared by Endpoint 1 and Endpoint 2. It is set after the datastored in the shared Endpoint 1/Endpoint 2 transmit buffer has been sent andan ACK handshake packet from the host is received. Once the next set of datais ready in the transmit buffers, software must clear this flag by writing a logic 1to the TXD1FR bit. To enable the next data packet transmission, TX1E mustalso be set. If TXD1F bit is not cleared, a NAK handshake will be returned inthe next IN transaction.Reset clears this bit. Writing a logic 0 to TXD1F has no effect.
1 = Transmit on Endpoint 1 or Endpoint 2 has occurred.0 = Transmit on Endpoint 1 or Endpoint 2 has not occurred.
EOPF — End of Packet Detect FlagThis read only bit is set when a valid End-of-Packet sequence is detected onthe D+ and D– lines. Software must clear this flag by writing a logic 1 to theEOPFR bit.Reset clears this bit. Writing a logic 0 to EOPF has no effect.
1 = End-of-Packet sequence has been detected.0 = End-of-Packet sequence has not been detected.
RESUMF — Resume FlagThis read only bit is set when USB bus activity is detected while the SUSPNDbit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit.Reset clears this bit. Writing a logic 0 to RESUMF has no effect.
1 = USB bus activity has been detected.0 = No USB bus activity has been detected.
RESUMFR — Resume Flag ResetWriting a logic 1 to this write only bit will clear the RESUMF bit if it is set. Writ-ing a logic 0 to RESUMFR has no effect. Reset clears this bit.
TXD1IE — Endpoint 1/Endpoint 2 Transmit Interrupt EnableThis read/write bit enables the USB to generate an interrupt when the sharedTransmit Endpoint 1/Endpoint 2 interrupt flag (TXD1F) bit becomes set. Resetclears this bit.
1 = USB interrupts enabled for Transmit Endpoints 1 and 2.0 = USB interrupts disabled for Transmit Endpoints 1 and 2.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UIR1 R TXD1F EOPF RESUMF 0TXD1IE EOPIE
0 0
$003A W RESUMFR TXD1FR EOPFR
reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 10-22. USB Interrupt Register 1(UIR1)
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-21
GENERAL RELEASE SPECIFICATION November 5, 1998
EOPIE — End of Packet Detect Interrupt EnableThis read/write bit enables the USB to generate an interrupt when the EOPF bitbecomes set. Reset clears this bit.
1 = USB interrupts enabled for Transmit Endpoints 1 and 2.0 = USB interrupts disabled for Transmit Endpoint 1 and 2.
TXD1FR — Endpoint 1/Endpoint 2 Transmit Flag ResetWriting a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing alogic 0 to TXD1FR has no effect. Reset clears this bit.
EOPFR — End of Packet Flag ResetWriting a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing alogic 0 to the EOPFR has no effect. Reset clears this bit.
10.5.4 USB Control Register 0 (UCR0)
T0SEQ — Endpoint 0 Transmit Sequence BitThis read/write bit determines which type of data packet (DATA0 or DATA1) willbe sent during the next IN transaction. Toggling of this bit must be controlled bysoftware. Reset clears this bit.
1 = DATA1 Token active for next Endpoint 0 transmit.0 = DATA0 Token active for next Endpoint 0 transmit.
STALL0 — Endpoint 0 Force Stall BitThis read/write bit causes Endpoint 0 to return a STALL handshake whenpolled by either an IN or OUT token by the USB Host Controller. The USB hard-ware clears this bit when a SETUP token is received. Reset clears this bit.
1 = Send STALL handshake.0 = Default.
TX0E — Endpoint 0 Transmit EnableThis read/write bit enables a transmit to occur when the USB Host controllersends an IN token to Endpoint 0. Software should set this bit when data isready to be transmitted. It must be cleared by software when no more Endpoint0 data needs to be transmitted.If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshaketo any Endpoint 0 IN tokens. Reset clears this bit.
1 = Data is ready to be sent.0 = Data is not ready. Respond with NAK.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UCR0 RT0SEQ STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
$003B W
reset: 0 0 0 0 0 0 0 0
Figure 10-23. USB Control Register 0 (UCR0)
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-22 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
RX0E — Endpoint 0 Receive EnableThis read/write bit enables a receive to occur when the USB Host controllersends an OUT token to Endpoint 0. Software should set this bit when data isready to be received. It must be cleared by software when data cannot bereceived.If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshaketo any Endpoint 0 OUT tokens. Reset clears this bit.
1 = Data is ready to be received.0 = Not ready for data. Respond with NAK.
TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet SizeThese read/write bits store the number of transmit data bytes for the next INtoken request for Endpoint 0. These bits are cleared by reset.
10.5.5 USB Control Register 1 (UCR1)
T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence BitThis read/write bit determines which type of data packet (DATA0 or DATA1) willbe sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.Toggling of this bit must be controlled by software. Reset clears this bit.
1 = DATA1 Token active for next Endpoint 1/Endpoint 2 transmit.0 = DATA0 Token active for next Endpoint 1/Endpoint 2 transmit.
ENDADD — Endpoint Address SelectThis read/write bit specifies whether the data inside the registersUE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for asuccessful Endpoint 2 USB response to a hosts IN token are satisfied(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bitis configured for Endpoint 1, the USB responds with a NAK handshake packet.
1 = The data buffers are used for Endpoint 2.0 = The data buffers are used for Endpoint 1.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UCR1 RT1SEQ ENDADD TX1E FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
$003C W
reset: 0 0 0 0 0 0 0 0
Figure 10-24. USB Control Register 1 (UCR1)
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-23
GENERAL RELEASE SPECIFICATION November 5, 1998
TX1E — Endpoint 1/Endpoint 2 Transmit EnableThis read/write bit enables a transmit to occur when the USB Host controllersends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpointenable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.Software should set the TX1E bit when data is ready to be transmitted. It mustbe cleared by software when no more data needs to be transmitted.If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshaketo any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.
1 = Data is ready to be sent.0 = Data is not ready. Respond with NAK.
FRESUM — Force ResumeThis read/write bit forces a resume state (“K” or non-idle state) onto the USBdata lines to initiate a remote wake-up. Software should control the timing of theforced resume to be between 10ms and 15 ms. Setting this bit will not causethe RESUMF bit to set.
1 = Force data lines to “K” state.0 = Default.
TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet SizeThese read/write bits store the number of transmit data bytes for the next INtoken request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.
10.5.6 USB Control Register 2 (UCR2)
TX1STR — Clear Transmit First FlagWriting a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing alogic 0 to the TX1STR has no effect. Reset clears this bit.
TX1ST — Transmit First FlagThis read-only bit is set if the Endpoint 0 Data Transmit Flag (TXD0F) is setwhen the USB control logic is setting the Endpoint 0 Data Receive Flag(RXD0F). That is, this bit will be set if an Endpoint 0 Transmit Flag is still set atthe end of an Endpoint 0 reception. This bit lets the firmware know that theEndpoint 0 transmission happened before the Endpoint 0 reception. Resetclears this bit.
1 = IN transaction occurred before SETUP/OUT.0 = IN transaction occurred after SETUP/OUT.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UCR2 R 0 TX1ST 0ENABLE2 ENABLE1 STALL2 STALL1
$0037 W TX1STR
reset: - - 0 - 0 0 0 0
= Unimplemented
Figure 10-25. USB Control Register 2 (UCR2)
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-24 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
ENABLE2 — Endpoint 2 EnableThis read/write bit enables Endpoint 2 and allows the USB to respond to INpackets addressed to Endpoint 2. Reset clears this bit.
1 = Endpoint 2 is enabled and can respond to an IN token.0 = Endpoint 2 is disabled.
ENABLE1 — Endpoint 1 EnableThis read/write bit enables Endpoint 1 and allows the USB to respond to INpackets addressed to Endpoint 1. Reset clears this bit.
1 = Endpoint 1 is enabled and can respond to an IN token.0 = Endpoint 1 is disabled.
STALL2 — Endpoint 2 Force Stall BitThis read/write bit causes Endpoint 2 to return a STALL handshake whenpolled by either an IN or OUT token by the USB Host Controller. Reset clearsthis bit.
1 = Send STALL handshake.0 = Default.
STALL1 — Endpoint 1 Force Stall BitThis read/write bit causes Endpoint 1 to return a STALL handshake whenpolled by either an IN or OUT token by the USB Host Controller. Reset clearsthis bit.
1 = Send STALL handshake.0 = Default.
10.5.7 USB Status Register (USR)
RSEQ — Endpoint 0 Receive Sequence BitThis read only bit indicates the type of data packet last received for Endpoint 0(DATA0 or DATA1).
1 = DATA1 Token received in last Endpoint 0 receive.0 = DATA0 Token received in last Endpoint 0 receive.
SETUP — SETUP Token Detect BitThis read only bit indicates that a valid SETUP token has been received.
1 = Last token received for Endpoint 0 was a SETUP token.0 = Last token received for Endpoint 0 was not a SETUP token.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
USR R RSEQ SETUP 0 0RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0
$003D W
reset: U U U U U U U U
= Unimplemented
Figure 10-26. USB Status Register (USR)
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-25
GENERAL RELEASE SPECIFICATION November 5, 1998
RPSIZ3-RPSIZ0 — Endpoint 0 Receive Data Packet SizeThese read only bits store the number of data bytes received for the last OUTor SETUP transaction for Endpoint 0. These bits are not affected by reset.
10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)
UE0RD7 - UE0RD0 — Endpoint 0 Receive Data BufferThese read only bits are serially loaded with OUT token or SETUP token datareceived over the USB’s D+ and D– pins.
UE0TD7 - UE0TD0 — Endpoint 0 Transmit Data BufferThese write only buffers are loaded by software with data to be sent on theUSB bus on the next IN token directed at Endpoint 0.
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)
UE1TD7 - UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data BufferThese write only buffers are loaded by software with data to be sent on theUSB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These buff-ers are shared by Endpoints 1 and 2 and depend on proper configuration of theENDADD bit.
10.6 USB INTERRUPTS
The USB module is capable of generating interrupts and causing the CPU toexecute the USB interrupt service routine. There are three types of USBinterrupts:
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UE0D0 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
$0020 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
to: : : : : : : :
: : : : : : : :
UE0D7 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
$0027 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
reset: X X X X X X X X
Figure 10-27. USB Endpoint 0 Data Register (UE0D0-UE0D7)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UE1D0 R
$0028 W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
to: : : : : : : :
: : : : : : : :
UE1D7 R
$002F W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
reset: X X X X X X X X
Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-26 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
• End of Transaction interrupts signify a completed transaction (receive ortransmit)
• Resume interrupts signify that the USB bus is reactivated after havingbeen suspended
• End of Packet interrupts signify that a low speed end of packet signalwas detected
All USB interrupts share the same interrupt vector. Firmware is responsible fordetermining which interrupt is active.
10.6.1 USB End of Transaction Interrupt
There are three possible end of transaction interrupts: Endpoint 0 Receive,Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End oftransaction interrupts occur as detailed in the following sections.
10.6.1.1 Receive Control Endpoint 0
For a Control OUT transaction directed at Endpoint 0, the USB module willgenerate an interrupt by setting the RXD0F flag in the UIR0 register. Theconditions necessary for the interrupt to occur are shown in the flowchart ofFigure 10-29.
SETUP transactions cannot be stalled by the USB function. A SETUP received bya control endpoint will clear the STALL0 bit if it is set. The conditions for receivinga SETUP interrupt are shown in Figure 10-30.
10.6.1.2 Transmit Control Endpoint 0
For a Control IN transaction directed at Endpoint 0, the USB module will generatean interrupt by setting the TXD0F flag in the UIR0 register. The conditionsnecessary for the interrupt to occur are shown in the flowchart of Figure 10-31.
10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2
Transmit Endpoints 1 and 2 share their interrupt flag. For an IN transactiondirected at Endpoint 1 or 2, the USB module will generate an interrupt by settingthe TXD1F flag in the UIR1 register. The conditions necessary for the interrupt tooccur are shown in the flowchart of Figure 10-32.
10.6.2 Resume Interrupt
The USB module will generate a USB interrupt if low speed bus activity isdetected after entering the suspend state. A transition of the USB data lines to thenon-idle state (“K” state) while in the suspend mode will set the RESUMF flag inthe UIR1 register. There is no interrupt enable bit for this interrupt source and aninterrupt will be executed if the I bit in the CCR is cleared. A resume interrupt canonly occur while the MC68HC05JB3 is in the suspend mode.
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-27
GENERAL RELEASE SPECIFICATION November 5, 1998
10.6.3 End of Packet Interrupt
The USB module can generate a USB interrupt upon detection of an end ofpacket signal (a single ended 0) for low speed devices. Upon detection of an SE0sequence, the USB module sets the EOPF bit and will generate an interrupt if theEOPIE bit in the UIR1 register is set.
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-28 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 10-29. OUT Token Data Flow for Receive Endpoint 0
Valid OUT token received for Endpoint 0
Endpoint 0 Receive Enabled?(USBEN = 1)
Endpoint 0 Receive Ready to Receive?(RX0E = 1) && (RXD0F = 0)
Error free DATA packet?
No Responsefrom USB function
Send NAK Handshake
Ignore transactionNo response from
USB function
Set RXD0F to 1
Receive Control EndpointInterrupt Enabled?
(RXD0IE = 1)
No InterruptValid transaction
Interrupt generated
Endpoint 0 Receive Not Stalled?(STALL0 = 0)
Send STALL Handshake
Accept Data
Valid DATA token received for Endpoint 0? No Response
from USB function
Time-outN
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Set/clear RSEQ bit
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-29
GENERAL RELEASE SPECIFICATION November 5, 1998
Figure 10-30. SETUP Token Data Flow for Receive Endpoint 0
Valid SETUP token received for Endpoint 0
Endpoint 0 Receive Enabled?(USBEN = 1)
Error free DATA packet?
No Responsefrom USB function
Ignore transactionNo response from
USB function
Set RXD0F to 1
Receive Control EndpointInterrupt Enabled?
(RXD0IE = 1)
No InterruptValid transaction
Interrupt generated
Accept Data
Set SETUP to 1
N
N
N
Y
Y
Y
Y
Y
Y
STALL0 = 0?N
Clear STALL0 bit
Endpoint 0 Receive Ready to Receive?(RX0E = 1) && (RXD0F = 0)
N
Y
set/clear RSEQ bit
No Responsefrom USB function
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-30 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure 10-31. IN Token Data Flow for Transmit Endpoint 0Transmit Endpoint Enabled?(USBEN = 1)
Transmit Endpoint ready to Transfer?(TX0E = 1) && (TXD0F = 0)
No Responsefrom USB function
Send NAK Handshake
ACK received and no
Set TXD0F to 1
Transmit EndpointInterrupt Enabled?
(TXD0IE = 1)
No Interrupt
Valid transaction Interrupt generated
Transmit Endpoint not Stalled by firmware?(STALL0 = 0)
Send STALL Handshake
Send DATAData PID set by T0SEQ
Valid IN token received for Endpoint 0
N
Y
N
N
Y
Y
Y
No Responsefrom USB function
N
Y
Time-out condition occur?
N
MC68HC05JB3 UNIVERSAL SERIAL BUS MODULE MOTOROLAREV 1 10-31
GENERAL RELEASE SPECIFICATION November 5, 1998
Figure 10-32. IN Token Data Flow for Transmit Endpoint 1/2
Transmit Endpoint Enabled?(USBEN = 1)
Transmit Endpoint ready to Transfer?(TX1E = 1) && (TXD1F = 0) &
No Responsefrom USB function
Send NAK Handshake
Set TXD1F to 1
Transmit EndpointInterrupt Enabled?
(TXD1IE = 1) No Interrupt
Valid transaction Interrupt generated
Transmit Endpoint not Stalled by firmware?(STALL1 & ENDP1) + (STALL2 & ENDP2)
Send STALL Handshake
Send DATAData PID set by T1SEQ
Valid IN token received for Endpoints 1 or 2
N
N
N
Y
Y
Y
ACK received and noTime-out condition occurs?
No Responsefrom USB function
N
Y
((ENDP2 & ENDADD) + (ENDP1 & ENDADD))
ENDP1 is Endpoint 1 directed trafficENDP2 is Endpoint 2 directed traffic
Note:
MOTOROLA UNIVERSAL SERIAL BUS MODULE MC68HC05JB310-32 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 11OPTICAL INTERFACE
The MC68HC05JB3 MCU has four pairs of Optical Interfaces, configured throughPort-A. This port has built-in optical coupler interface devices, which can bedirectly connected to IR displacement encoders, such as in optical mouse andoptical joystick applications.
11.1 OVERVIEW
In practical designs, each axis requires two optical couplers to detect the displace-ment. Hence, the eight optical interfaces on port-A are enabled in pairs, with eachpair enabled by a bit in the Optical Interface Enable Register ($0E). Figure 11-1shows a one pair of the optical interface. Table 11-1 shows the port-A configura-tion for the four pairs.
Table 11-1. Port-A Optical Interface Pairs
For optimal performance, the reference voltage used in the optical interfacemodule is selectable from eight predefined values, as shown in Figure 11-2. andTable 11-2. This allows the optical interface to be easily configured by software tomatch the IR displacement encoders. The reference voltage is selected using thebits VREF0-VREF2 in the OIER.
Optical Coupler Port pin used Enable bit in OIER
Pair 1 PA0 and PA1 OIE0
Pair 2 PA2 and PA3 OIE1
Pair 3 PA4 and PA5 OIE2
Pair 4 PA6 and PA7 OIE3
MC68HC05JB3 OPTICAL INTERFACE MOTOROLAREV 1 11-1
GENERAL RELEASE SPECIFICATION November 5, 1998
Figure 11-1. A pair of Optical Coupler InterfaceFigure 11-2. Optical Interface Comparator
MC
U In
tern
al B
us
PAxPort LogicPAx
OpticalInterface
OutputBuffer
MUX
select
PA(x+1)Port Logic
PA(x+1)
OpticalInterface
OutputBuffer
OPTI_EN
VREF
OIEn
0
1
MUX
select
0
1
Voltage DividerOIE0
OIE1
OIE2
OIE3enable
VREFVoltage Selector
enable
VREF2
VREF1
VREF0
OPTI_EN
–
+
DynamicInput
Impedance
To MUX
OPTICALINTERFACE
PAx
MOTOROLA OPTICAL INTERFACE MC68HC05JB311-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
11.2 OPTICAL INTERFACE ENABLE REGISTER
The OIER register controls the operation of the optical interface devices onPort-A. This register is located at address $0E.
Figure 11-3. Optical Interface Enable Register (TCSR)
OIE0 — Optical Interface pair 0 Enable 1 = PA0 and PA1 optical interface are enabled.0 = PA0 and PA1 optical interface are disabled.
OIE1 — Optical Interface pair 1 Enable 1 = PA2 and PA3 optical interface are enabled.0 = PA2 and PA3 optical interface are disabled.
OIE2 — Optical Interface pair 2 Enable 1 = PA4 and PA5 optical interface are enabled.0 = PA4 and PA5 optical interface are disabled.
OIE3 — Optical Interface pair 3 Enable 1 = PA6 and PA7 optical interface are enabled.0 = PA6 and PA7 optical interface are disabled.
VREF[0:2] — Reference Voltage SelectionThese 3 bits are used to select the optical interface reference voltage.
Table 11-2. Optical Interface Reference Voltage Selection
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OIER RTCMPE VREF2 VREF1 VREF0 OIE3 OIE2 OIE1 OIE0
$000E W
reset: 0 0 0 0 0 0 0 0
VREF2 VREF1 VREF0 Reference Voltage (mV), VDD= 5V
0 0 0 300
0 0 1 430
0 1 0 560
0 1 1 690
1 0 0 820
1 0 1 950
1 1 0 1080
1 1 1 1210
MC68HC05JB3 OPTICAL INTERFACE MOTOROLAREV 1 11-3
GENERAL RELEASE SPECIFICATION November 5, 1998
TCMPE — Timer Input Capture Comparator EnableThis bit is used to enable the comparator in the 16-bit timer input capturecircuit. Please refer to 16-BIT TIMER section.
1 = Timer input capture comparator is selected.0 = Timer input capture comparator schmitt trigger is selected.
MOTOROLA OPTICAL INTERFACE MC68HC05JB311-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 12INSTRUCTION SET
This section describes the addressing modes and instruction types.
12.1 ADDRESSING MODES
The CPU uses eight addressing modes for flexibility in accessing data. Theaddressing modes define the manner in which the CPU finds the data required toexecute an instruction. The eight addressing modes are the following:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, No Offset
• Indexed, 8-Bit Offset
• Indexed, 16-Bit Offset
• Relative
12.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPUregisters, such as set carry flag (SEC) and increment accumulator (INCA).Inherent instructions require no memory address and are one byte long.
12.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operationwith the value in the accumulator or index register. Immediate instructions requireno memory address and are two bytes long. The opcode is the first byte, and theimmediate data value is the second byte.
MC68HC05JB3 INSTRUCTION SET MOTOROLAREV 1 12-1
GENERAL RELEASE SPECIFICATION November 5, 1998
12.1.3 Direct
Direct instructions can access any of the first 256 memory addresses with twobytes. The first byte is the opcode, and the second is the low byte of the operandaddress. In direct addressing, the CPU automatically uses $00 as the high byte ofthe operand address. BRSET and BRCLR are three-byte instructions that usedirect addressing to access the operand and relative addressing to specify abranch destination.
12.1.4 Extended
Extended instructions use only three bytes to access any address in memory. Thefirst byte is the opcode; the second and third bytes are the high and low bytes ofthe operand address.
When using the Motorola assembler, the programmer does not need to specifywhether an instruction is direct or extended. The assembler automatically selectsthe shortest form of the instruction.
12.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access datawith variable addresses within the first 256 memory locations. The index registercontains the low byte of the conditional address of the operand. The CPUautomatically uses $00 as the high byte, so these instructions can addresslocations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table orto hold the address of a frequently used RAM or I/O location.
12.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access datawith variable addresses within the first 511 memory locations. The CPU adds theunsigned byte in the index register to the unsigned byte following the opcode. Thesum is the conditional address of the operand. These instructions can accesslocations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in ann-element table. The table can begin anywhere within the first 256 memorylocations and could extend as far as location 510 ($01FE). The k value is typicallyin the index register, and the address of the beginning of the table is in the bytefollowing the opcode.
MOTOROLA INSTRUCTION SET MC68HC05JB312-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
12.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access datawith variable addresses at any location in memory. The CPU adds the unsignedbyte in the index register to the two unsigned bytes following the opcode. The sumis the conditional address of the operand. The first byte after the opcode is thehigh byte of the 16-bit offset; the second byte is the low byte of the offset. Theseinstructions can address any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element in ann-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines theshortest form of indexed addressing.
12.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,the CPU finds the conditional branch destination by adding the signed bytefollowing the opcode to the contents of the program counter. If the branchcondition is not true, the CPU goes to the next instruction. The offset is a signed,two’s complement byte that gives a branching range of –128 to +127 bytes fromthe address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculatethe offset, because the assembler determines the proper offset and verifies that itis within the span of the branch.
12.1.9 Instruction Types
The MCU instructions fall into the following five categories:
• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions
MC68HC05JB3 INSTRUCTION SET MOTOROLAREV 1 12-3
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12.1.10 Register/Memory Instructions
Most of these instructions use two operands. One operand is in either theaccumulator or the index register. The CPU finds the other operand in memory.Table 12-1 lists the register/memory instructions.
Table 12-1. Register/Memory Instructions
Instruction Mnemonic
Add Memory Byte and Carry Bit to Accumulator ADC
Add Memory Byte to Accumulator ADD
AND Memory Byte with Accumulator AND
Bit Test Accumulator BIT
Compare Accumulator CMP
Compare Index Register with Memory Byte CPX
EXCLUSIVE OR Accumulator with Memory Byte EOR
Load Accumulator with Memory Byte LDA
Load Index Register with Memory Byte LDX
Multiply MUL
OR Accumulator with Memory Byte ORA
Subtract Memory Byte and Carry Bit from Accumulator SBC
Store Accumulator in Memory STA
Store Index Register in Memory STX
Subtract Memory Byte from Accumulator SUB
MOTOROLA INSTRUCTION SET MC68HC05JB312-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
12.1.11 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, andwrite the modified value back to the memory location or to the register. The test fornegative or zero instruction (TST) is an exception to the read-modify-writesequence because it does not write a replacement value. Table 12-2 lists theread-modify-write instructions.
12.1.12 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the programcounter. The unconditional jump instruction (JMP) and the jump to subroutineinstruction (JSR) have no register operand. Branch instructions allow the CPU tointerrupt the normal sequence of the program counter when a test condition ismet. If the test condition is not met, the branch is not performed. All branchinstructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of anyreadable bit in the first 256 memory locations. These three-byte instructions use acombination of direct addressing and relative addressing. The direct address ofthe byte to be tested is in the byte following the opcode. The third byte is thesigned offset byte. The CPU finds the conditional branch destination by adding the
Table 12-2. Read-Modify-Write Instructions
Instruction Mnemonic
Arithmetic Shift Left ASL
Arithmetic Shift Right ASR
Clear Bit in Memory BCLR
Set Bit in Memory BSET
Clear CLR
Complement (One’s Complement) COM
Decrement DEC
Increment INC
Logical Shift Left LSL
Logical Shift Right LSR
Negate (Two’s Complement) NEG
Rotate Left through Carry Bit ROL
Rotate Right through Carry Bit ROR
Test for Negative or Zero TST
MC68HC05JB3 INSTRUCTION SET MOTOROLAREV 1 12-5
GENERAL RELEASE SPECIFICATION November 5, 1998
third byte to the program counter if the specified bit tests true. The bit to be testedand its condition (set or clear) is part of the opcode. The span of branching is from–128 to +127 from the address of the next location after the branch instruction.The CPU also transfers the tested bit to the carry/borrow bit of the condition coderegister. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
Instruction Mnemonic
Branch if Carry Bit Clear BCC
Branch if Carry Bit Set BCS
Branch if Equal BEQ
Branch if Half-Carry Bit Clear BHCC
Branch if Half-Carry Bit Set BHCS
Branch if Higher BHI
Branch if Higher or Same BHS
Branch if IRQ Pin High BIH
Branch if IRQ Pin Low BIL
Branch if Lower BLO
Branch if Lower or Same BLS
Branch if Interrupt Mask Clear BMC
Branch if Minus BMI
Branch if Interrupt Mask Set BMS
Branch if Not Equal BNE
Branch if Plus BPL
Branch Always BRA
Branch if Bit Clear BRCLR
Branch Never BRN
Branch if Bit Set BRSET
Branch to Subroutine BSR
Unconditional Jump JMP
Jump to Subroutine JSR
MOTOROLA INSTRUCTION SET MC68HC05JB312-6 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
12.1.13 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Portregisters, port data direction registers, timer registers, and on-chip RAM locationsare in the first 256 bytes of memory. The CPU can also test and branch based onthe state of any bit in any of the first 256 memory locations. Bit manipulationinstructions use direct addressing. Table 12-4 lists these instructions.
12.1.14 Control Instructions
These register reference instructions control CPU operation during programexecution. Control instructions, listed in Table 12-5, use inherent addressing.
Table 12-4. Bit Manipulation Instructions
Instruction Mnemonic
Clear Bit BCLR
Branch if Bit Clear BRCLR
Branch if Bit Set BRSET
Set Bit BSET
Table 12-5. Control Instructions
Instruction Mnemonic
Clear Carry Bit CLC
Clear Interrupt Mask CLI
No Operation NOP
Reset Stack Pointer RSP
Return from Interrupt RTI
Return from Subroutine RTS
Set Carry Bit SEC
Set Interrupt Mask SEI
Stop Oscillator and Enable IRQ Pin STOP
Software Interrupt SWI
Transfer Accumulator to Index Register TAX
Transfer Index Register to Accumulator TXA
Stop CPU Clock and Enable Interrupts WAIT
MC68HC05JB3 INSTRUCTION SET MOTOROLAREV 1 12-7
GENERAL RELEASE SPECIFICATION November 5, 1998
12.1.15 Instruction Set Summary
Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effectof each instruction on the condition code register.
Table 12-6. Instruction Set Summary
SourceForm
Operation Description
Effect onCCR
Ad
dre
ssM
od
e
Op
cod
e
Op
eran
d
Cyc
les
H I N Z C
ADC #oprADC oprADC oprADC opr,XADC opr,XADC ,X
Add with Carry A ← (A) + (M) + (C) —
IMMDIREXTIX2IX1IX
A9B9C9D9E9F9
iidd
hh llee ff
ff
234543
ADD #oprADD oprADD oprADD opr,XADD opr,XADD ,X
Add without Carry A ← (A) + (M) —
IMMDIREXTIX2IX1IX
ABBBCBDBEBFB
iidd
hh llee ff
ff
234543
AND #oprAND oprAND oprAND opr,XAND opr,XAND ,X
Logical AND A ← (A) ∧ (M) — — —
IMMDIREXTIX2IX1IX
A4B4C4D4E4F4
iidd
hh llee ff
ff
234543
ASL oprASLAASLXASL opr,XASL ,X
Arithmetic Shift Left (Same as LSL)
— —
3848586878
dd
ff
53365
ASR oprASRAASRXASR opr,XASR ,X
Arithmetic Shift Right — —
DIRINHINHIX1IX
3747576777
dd
ff
53365
BCC relBranch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3
BCLR n opr Clear Bit n Mn ← 0 — — — — —
DIR (b0)DIR (b1)DIR (b2)DIR (b3)DIR (b4)DIR (b5)DIR (b6)DIR (b7)
11131517191B1D1F
dddddddddddddddd
55555555
BCS relBranch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? Z = 1 — — — — — REL 27 rr 3
C
b0b7
0
b0b7
C
MOTOROLA INSTRUCTION SET MC68HC05JB312-8 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
BHCC relBranch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0 — — — — — REL 28 rr 3
BHCS relBranch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1 — — — — — REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — REL 22 rr 3
BHS relBranch if Higher or Same
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3
BIH relBranch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr 3
BIL relBranch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr 3
BIT #oprBIT oprBIT oprBIT opr,XBIT opr,XBIT ,X
Bit Test Accumulator with Memory Byte
(A) ∧ (M) — — —
IMMDIREXTIX2IX1IX
A5B5C5D5E5F5
iidd
hh llee ff
ffp
234543
BLO relBranch if Lower(Same as BCS)
PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3
BLS relBranch if Lower or Same
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — REL 23 rr 3
BMC relBranch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0 — — — — — REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? N = 1 — — — — — REL 2B rr 3
BMS relBranch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1 — — — — — REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? Z = 0 — — — — — REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? N = 0 — — — — — REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ? 1 = 1 — — — — — REL 20 rr 3
BRCLR n opr rel Branch if bit n clear PC ← (PC) + 2 + rel ? Mn = 0 — — — —
DIR (b0)DIR (b1)DIR (b2)DIR (b3)DIR (b4)DIR (b5)DIR (b6)DIR (b7)
01030507090B0D0F
dd rrdd rrdd rrdd rrdd rrdd rrdd rrdd rr
55555555
BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 — — — —
DIR (b0)DIR (b1)DIR (b2)DIR (b3)DIR (b4)DIR (b5)DIR (b6)DIR (b7)
00020406080A0C0E
dd rrdd rrdd rrdd rrdd rrdd rrdd rrdd rr
55555555
BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 — — — — — REL 21 rr 3
Table 12-6. Instruction Set Summary (Continued)
SourceForm
Operation Description
Effect onCCR
Ad
dre
ssM
od
e
Op
cod
e
Op
eran
d
Cyc
les
H I N Z C
MC68HC05JB3 INSTRUCTION SET MOTOROLAREV 1 12-9
GENERAL RELEASE SPECIFICATION November 5, 1998
BSET n opr Set Bit n Mn ← 1 — — — — —
DIR (b0)DIR (b1)DIR (b2)DIR (b3)DIR (b4)DIR (b5)DIR (b6)DIR (b7)
10121416181A1C1E
dddddddddddddddd
55555555
BSR relBranch to Subroutine
PC ← (PC) + 2; push (PCL)SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1PC ← (PC) + rel
— — — — — REL AD rr 6
CLC Clear Carry Bit C ← 0 — — — — 0 INH 98 2
CLI Clear Interrupt Mask I ← 0 — 0 — — — INH 9A 2
CLR oprCLRACLRXCLR opr,XCLR ,X
Clear Byte
M ← $00A ← $00X ← $00M ← $00M ← $00
— — 0 1 —
DIRINHINHIX1IX
3F4F5F6F7F
dd
ff
53365
CMP #oprCMP oprCMP oprCMP opr,XCMP opr,XCMP ,X
Compare Accumulator with Memory Byte
(A) – (M) — —
IMMDIREXTIX2IX1IX
A1B1C1D1E1F1
iidd
hh llee ff
ff
234543
COM oprCOMACOMXCOM opr,XCOM ,X
Complement Byte(One’s Complement)
M ← ( ) = $FF – (M)A ← ( ) = $FF – (M)X ← ( ) = $FF – (M)M ← ( ) = $FF – (M)M ← ( ) = $FF – (M)
— — 1
DIRINHINHIX1IX
3343536373
dd
ff
53365
CPX #oprCPX oprCPX oprCPX opr,XCPX opr,XCPX ,X
Compare Index Register with Memory Byte
(X) – (M) — —
IMMDIREXTIX2IX1IX
A3B3C3D3E3F3
iidd
hh llee ff
ff
234543
DEC oprDECADECXDEC opr,XDEC ,X
Decrement Byte
M ← (M) – 1A ← (A) – 1X ← (X) – 1M ← (M) – 1M ← (M) – 1
— — —
DIRINHINHIX1IX
3A4A5A6A7A
dd
ff
53365
EOR #oprEOR oprEOR oprEOR opr,XEOR opr,XEOR ,X
EXCLUSIVE OR Accumulator with Memory Byte
A ← (A) ⊕ (M) — — —
IMMDIREXTIX2IX1IX
A8B8C8D8E8F8
iidd
hh llee ff
ff
234543
Table 12-6. Instruction Set Summary (Continued)
SourceForm
Operation Description
Effect onCCR
Ad
dre
ssM
od
e
Op
cod
e
Op
eran
d
Cyc
les
H I N Z C
MAXMM
MOTOROLA INSTRUCTION SET MC68HC05JB312-10 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
INC oprINCAINCXINC opr,XINC ,X
Increment Byte
M ← (M) + 1A ← (A) + 1X ← (X) + 1M ← (M) + 1M ← (M) + 1
— — —
DIRINHINHIX1IX
3C4C5C6C7C
dd
ff
53365
JMP oprJMP oprJMP opr,XJMP opr,XJMP ,X
Unconditional Jump PC ← Jump Address — — — — —
DIREXTIX2IX1IX
BCCCDCECFC
ddhh llee ff
ff
23432
JSR oprJSR oprJSR opr,XJSR opr,XJSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)Push (PCL); SP ← (SP) – 1Push (PCH); SP ← (SP) – 1PC ← Conditional Address
— — — — —
DIREXTIX2IX1IX
BDCDDDEDFD
ddhh llee ff
ff
56765
LDA #oprLDA oprLDA oprLDA opr,XLDA opr,XLDA ,X
Load Accumulator with Memory Byte
A ← (M) — — —
IMMDIREXTIX2IX1IX
A6B6C6D6E6F6
iidd
hh llee ff
ff
234543
LDX #oprLDX oprLDX oprLDX opr,XLDX opr,XLDX ,X
Load Index Register with Memory Byte
X ← (M) — — —
IMMDIREXTIX2IX1IX
AEBECEDEEEFE
iidd
hh llee ff
ff
234543
LSL oprLSLALSLXLSL opr,XLSL ,X
Logical Shift Left(Same as ASL)
— —
DIRINHINHIX1IX
3848586878
dd
ff
53365
LSR oprLSRALSRXLSR opr,XLSR ,X
Logical Shift Right — — 0
DIRINHINHIX1IX
3444546474
dd
ff
53365
MUL Unsigned Multiply X : A ← (X) × (A) 0 — — — 0 INH 42 11
NEG oprNEGANEGXNEG opr,XNEG ,X
Negate Byte(Two’s Complement)
M ← –(M) = $00 – (M)A ← –(A) = $00 – (A)X ← –(X) = $00 – (X)M ← –(M) = $00 – (M)M ← –(M) = $00 – (M)
— —
DIRINHINHIX1IX
3040506070
ii
ff
53365
NOP No Operation — — — — — INH 9D 2
Table 12-6. Instruction Set Summary (Continued)
SourceForm
Operation Description
Effect onCCR
Ad
dre
ssM
od
e
Op
cod
e
Op
eran
d
Cyc
les
H I N Z C
C
b0b7
0
b0b7
C0
MC68HC05JB3 INSTRUCTION SET MOTOROLAREV 1 12-11
GENERAL RELEASE SPECIFICATION November 5, 1998
ORA #oprORA oprORA oprORA opr,XORA opr,XORA ,X
Logical OR Accumulator with Memory
A ← (A) ∨ (M) — — —
IMMDIREXTIX2IX1IX
AABACADAEAFA
iidd
hh llee ff
ff
234543
ROL oprROLAROLXROL opr,XROL ,X
Rotate Byte Left through Carry Bit
— —
DIRINHINHIX1IX
3949596979
dd
ff
53365
ROR oprRORARORXROR opr,XROR ,X
Rotate Byte Right through Carry Bit
— —
DIRINHINHIX1IX
3646566676
dd
ff
53365
RSP Reset Stack Pointer SP ← $00FF — — — — — INH 9C 2
RTI Return from Interrupt
SP ← (SP) + 1; Pull (CCR)SP ← (SP) + 1; Pull (A)SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)SP ← (SP) + 1; Pull (PCL)
INH 80 9
RTSReturn from Subroutine
SP ← (SP) + 1; Pull (PCH)SP ← (SP) + 1; Pull (PCL)
— — — — — INH 81 6
SBC #oprSBC oprSBC oprSBC opr,XSBC opr,XSBC ,X
Subtract Memory Byte and Carry Bit from Accumulator
A ← (A) – (M) – (C) — —
IMMDIREXTIX2IX1IX
A2B2C2D2E2F2
iidd
hh llee ff
ff
234543
SEC Set Carry Bit C ← 1 — — — — 1 INH 99 2
SEI Set Interrupt Mask I ← 1 — 1 — — — INH 9B 2
STA oprSTA oprSTA opr,XSTA opr,XSTA ,X
Store Accumulator in Memory
M ← (A) — — —
DIREXTIX2IX1IX
B7C7D7E7F7
ddhh llee ff
ff
45654
STOPStop Oscillator and Enable IRQ Pin
— 0 — — — INH 8E 2
STX oprSTX oprSTX opr,XSTX opr,XSTX ,X
Store Index Register In Memory
M ← (X) — — —
DIREXTIX2IX1IX
BFCFDFEFFF
ddhh llee ff
ff
45654
Table 12-6. Instruction Set Summary (Continued)
SourceForm
Operation Description
Effect onCCR
Ad
dre
ssM
od
e
Op
cod
e
Op
eran
d
Cyc
les
H I N Z C
C
b0b7
b0b7
C
MOTOROLA INSTRUCTION SET MC68HC05JB312-12 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SUB #oprSUB oprSUB oprSUB opr,XSUB opr,XSUB ,X
Subtract Memory Byte from Accumulator
A ← (A) – (M) — —
IMMDIREXTIX2IX1IX
A0B0C0D0E0F0
iidd
hh llee ff
ff
234543
SWI Software Interrupt
PC ← (PC) + 1; Push (PCL)SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High BytePCL ← Interrupt Vector Low Byte
— 1 — — — INH 83 10
TAXTransfer Accumulator to Index Register
X ← (A) — — — — — INH 97 2
TST oprTSTATSTXTST opr,XTST ,X
Test Memory Byte for Negative or Zero
(M) – $00 — — —
DIRINHINHIX1IX
3D4D5D6D7D
dd
ff
43354
TXATransfer Index Register to Accumulator
A ← (X) — — — — — INH 9F 2
WAITStop CPU Clock and Enable Interrupts
— 0 — — — INH 8F 2
A Accumulator opr Operand (one or two bytes)C Carry/borrow flag PC Program counterCCR Condition code register PCH Program counter high bytedd Direct address of operand PCL Program counter low bytedd rr Direct address of operand and relative offset of branch instruction REL Relative addressing modeDIR Direct addressing mode rel Relative program counter offset byteee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byteEXT Extended addressing mode SP Stack pointerff Offset byte in indexed, 8-bit offset addressing X Index registerH Half-carry flag Z Zero flaghh ll High and low bytes of operand address in extended addressing # Immediate valueI Interrupt mask ∧ Logical ANDii Immediate operand byte ∨ Logical ORIMM Immediate addressing mode ⊕ Logical EXCLUSIVE ORINH Inherent addressing mode ( ) Contents ofIX Indexed, no offset addressing mode –( ) Negation (two’s complement)IX1 Indexed, 8-bit offset addressing mode ← Loaded withIX2 Indexed, 16-bit offset addressing mode ? IfM Memory location : Concatenated withN Negative flag Set or clearedn Any bit — Not affected
Table 12-6. Instruction Set Summary (Continued)
SourceForm
Operation Description
Effect onCCR
Ad
dre
ssM
od
e
Op
cod
e
Op
eran
d
Cyc
les
H I N Z C
MC68HC05JB3 INSTRUCTION SET MOTOROLAREV 1 12-13
MO
TO
RO
LAIN
ST
RU
CT
ION
SE
TM
C68H
C05JB
312-14
RE
V 1
Table 12-7. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX
0 1 2 3 4 5 6 7 8 9 A B C D E F
05
BRSET03 DIR
5BSET0
2 DIR
3BRA
2 REL
5NEG
2 DIR
3NEGA
1 INH
3NEGX
1 INH
6NEG
2 IX1
5NEG
1 IX
9RTI
1 INH
2SUB
2 IMM
3SUB
2 DIR
4SUB
3 EXT
5SUB
3 IX2
4SUB
2 IX1
3SUB
1 IX0
15
BRCLR03 DIR
5BCLR0
2 DIR
3BRN
2 REL
6RTS
1 INH
2CMP
2 IMM
3CMP
2 DIR
4CMP
3 EXT
5CMP
3 IX2
4CMP
2 IX1
3CMP
1 IX1
25
BRSET13 DIR
5BSET1
2 DIR
3BHI
2 REL
11MUL
1 INH
2SBC
2 IMM
3SBC
2 DIR
4SBC
3 EXT
5SBC
3 IX2
4SBC
2 IX1
3SBC
1 IX2
35
BRCLR13 DIR
5BCLR1
2 DIR
3BLS
2 REL
5COM
2 DIR
3COMA
1 INH
3COMX
1 INH
6COM
2 IX1
5COM
1 IX
10SWI
1 INH
2CPX
2 IMM
3CPX
2 DIR
4CPX
3 EXT
5CPX
3 IX2
4CPX
2 IX1
3CPX
1 IX3
45
BRSET23 DIR
5BSET2
2 DIR
3BCC
2 REL
5LSR
2 DIR
3LSRA
1 INH
3LSRX
1 INH
6LSR
2 IX1
5LSR
1 IX
2AND
2 IMM
3AND
2 DIR
4AND
3 EXT
5AND
3 IX2
4AND
2 IX1
3AND
1 IX4
55
BRCLR23 DIR
5BCLR2
2 DIR
3BCS/BLO2 REL
2BIT
2 IMM
3BIT
2 DIR
4BIT
3 EXT
5BIT
3 IX2
4BIT
2 IX1
3BIT
1 IX5
65
BRSET33 DIR
5BSET3
2 DIR
3BNE
2 REL
5ROR
2 DIR
3RORA
1 INH
3RORX
1 INH
6ROR
2 IX1
5ROR
1 IX
2LDA
2 IMM
3LDA
2 DIR
4LDA
3 EXT
5LDA
3 IX2
4LDA
2 IX1
3LDA
1 IX6
75
BRCLR33 DIR
5BCLR3
2 DIR
3BEQ
2 REL
5ASR
2 DIR
3ASRA
1 INH
3ASRX
1 INH
6ASR
2 IX1
5ASR
1 IX
2TAX
1 INH
4STA
2 DIR
5STA
3 EXT
6STA
3 IX2
5STA
2 IX1
4STA
1 IX7
85
BRSET43 DIR
5BSET4
2 DIR
3BHCC
2 REL
5ASL/LSL
2 DIR
3ASLA/LSLA1 INH
3ASLX/LSLX1 INH
6ASL/LSL
2 IX1
5ASL/LSL
1 IX
2CLC
1 INH
2EOR
2 IMM
3EOR
2 DIR
4EOR
3 EXT
5EOR
3 IX2
4EOR
2 IX1
3EOR
1 IX8
95
BRCLR43 DIR
5BCLR4
2 DIR
3BHCS
2 REL
5ROL
2 DIR
3ROLA
1 INH
3ROLX
1 INH
6ROL
2 IX1
5ROL
1 IX
2SEC
1 INH
2ADC
2 IMM
3ADC
2 DIR
4ADC
3 EXT
5ADC
3 IX2
4ADC
2 IX1
3ADC
1 IX9
A5
BRSET53 DIR
5BSET5
2 DIR
3BPL
2 REL
5DEC
2 DIR
3DECA
1 INH
3DECX
1 INH
6DEC
2 IX1
5DEC
1 IX
2CLI
1 INH
2ORA
2 IMM
3ORA
2 DIR
4ORA
3 EXT
5ORA
3 IX2
4ORA
2 IX1
3ORA
1 IXA
B5
BRCLR53 DIR
5BCLR5
2 DIR
3BMI
2 REL
2SEI
1 INH
2ADD
2 IMM
3ADD
2 DIR
4ADD
3 EXT
5ADD
3 IX2
4ADD
2 IX1
3ADD
1 IXB
C5
BRSET63 DIR
5BSET6
2 DIR
3BMC
2 REL
5INC
2 DIR
3INCA
1 INH
3INCX
1 INH
6INC
2 IX1
5INC
1 IX
2RSP
1 INH
2JMP
2 DIR
3JMP
3 EXT
4JMP
3 IX2
3JMP
2 IX1
2JMP
1 IXC
D5
BRCLR63 DIR
5BCLR6
2 DIR
3BMS
2 REL
4TST
2 DIR
3TSTA
1 INH
3TSTX
1 INH
5TST
2 IX1
4TST
1 IX
2NOP
1 INH
6BSR
2 REL
5JSR
2 DIR
6JSR
3 EXT
7JSR
3 IX2
6JSR
2 IX1
5JSR
1 IXD
E5
BRSET73 DIR
5BSET7
2 DIR
3BIL
2 REL
2STOP
1 INH
2LDX
2 IMM
3LDX
2 DIR
4LDX
3 EXT
5LDX
3 IX2
4LDX
2 IX1
3LDX
1 IXE
F5
BRCLR73 DIR
5BCLR7
2 DIR
3BIH
2 REL
5CLR
2 DIR
3CLRA
1 INH
3CLRX
1 INH
6CLR
2 IX1
5CLR
1 IX
2WAIT
1 INH
2TXA
1 INH
4STX
2 DIR
5STX
3 EXT
6STX
3 IX2
5STX
2 IX1
4STX
1 IXF
INH = Inherent REL = RelativeIMM = Immediate IX = Indexed, No OffsetDIR = Direct IX1 = Indexed, 8-Bit OffsetEXT = Extended IX2 = Indexed, 16-Bit Offset
0 MSB of Opcode in Hexadecimal
LSB of Opcode in Hexadecimal 05
BRSET03 DIR
Number of CyclesOpcode MnemonicNumber of Bytes/Addressing Mode
LSB
MSBLSB
MSB
LSB
MSB
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 13ELECTRICAL SPECIFICATIONS
This section provides the electrical and timing specifications for theMC68HC05JB3.
13.1 MAXIMUM RATINGS
NOTE
Maximum ratings are the extreme limits the device can be exposed to withoutcausing permanent damage to the chip. The device is not intended to operate atthese conditions.
The MCU contains circuitry that protect the inputs against damage from highstatic voltages; however, do not apply voltages higher than those shown in thetable below. Keep VIN and VOUT within the range from VSS ≤ (VIN or VOUT) ≤ VDD.Connect unused inputs to the appropriate voltage level, either VSS or VDD.
13.2 THERMAL CHARACTERISTICS
(Voltages referenced to VSS)
Rating Symbol Value Unit
Supply Voltage VDD –0.3 to +7.0 V
Bootloader Mode (IRQ/VPP Pin Only) VIN VSS – 0.3 to 17 V
Current Drain Per Pin Excluding VDD and VSS I 25 mA
Operating Junction Temperature TJ +150 °C
Operating Temperature RangeMC68HC05JB3 (Standard)MC68HC05JB3 (Extended)
TATA
TL to TH0 to +70
–40 to +85°C°C
Storage Temperature Range Tstg –65 to +150 °C
Characteristic Symbol Value Unit
Thermal Resistance20-pin PDIP20-pin SOIC28-pin PDIP28-pin SOIC
θJA
θJA
θJA
θJA
°C/W°C/W°C/W°C/W
MC68HC05JB3 ELECTRICAL SPECIFICATIONS MOTOROLAREV 1 13-1
GENERAL RELEASE SPECIFICATION November 5, 1998
13.3 DC ELECTRICAL CHARACTERISTICS
Table 13-1. DC Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Output VoltageILoad = 10.0 µA
VOLVOH
—VDD – 0.1
——
0.1—
V
Output High Voltage(ILoad =–0.8 mA) PA0-7, PB0-2, PB4-7, PC0-3 VOH VDD – 0.8 — — V
Output Low Voltage(ILoad = 1.6mA) PA0-3, PB0, PB4-7, PC0-3(ILoad = 8mA) PA4-7(ILoad = 25mA) PB1, PB2 (see note 8)
VOL———
———
0.40.40.5
V
Input High VoltagePA0-7, PB0-2, PB4-7, PC0-3, IRQ, RESET, OSC1 VIH 0.7×VDD — VDD V
Input Low VoltagePA0-7, PB0-2, PB4-7, PC0-3, IRQ, RESET, OSC1 VIL VSS — 0.2×VDD V
Supply Current (see Notes)Run (USB active)Run (USB suspended)Wait (USB active)Wait (USB suspended)Stop (USB suspended)
3.3V regulator on
IDD
87.53
2.5
40
10954
100
mAmAmAmA
µA
I/O Ports Hi-Z Leakage CurrentPA0-7, PB0-2, PB4-7, PC0-3(without individual pull-down/up activated)
IZ — — ±10 µA
Input Pull-down CurrentPA0-7, PB0, PB4-7, PC0-3(with individual pull-down activated)
IIL 50 100 200 µA
Input CurrentRESET, IRQ, OSC1 Iin — — 5 µA
CapacitancePorts (as Input or Output)RESET, IRQ, OSC1, OSC2
CoutCin
——
——
128
pFpF
Crystal/Ceramic Resonator Oscillator ModeInternal Resistor
OSC1 to OSC2 ROSC 1 2 3 MΩ
MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05JB313-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
NOTES:1. All values shown reflect average measurements.2. Typical values at midpoint of voltage range, 25°C only.3. Wait IDD: Only MFT and Timer1 active.4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC = 6.0
MHz), all inputs 0.2 VDC from rail; no DC loads, less than 50pF on all outputs, CL = 20 pF on OSC2.5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD–0.2 VDC.6. Stop IDD measured with OSC1 = VSS.7. Wait IDD is affected linearly by the OSC2 capacitance.8. TA = 0°C to +40°C.9. These are preliminary specifications.
13.4 USB DC ELECTRICAL CHARACTERISTICS
Pullup ResistorPB1, PB2 RPULLUP 30 50 75 KΩ
LVR Inhibit (see note 9) VLVRI 3.3 V
LVR Recover (see note 9) VLVRR 3.5 V
TCAP Input Threshold Voltage VTCAP VDD/2 V
Table 13-2. USB DC Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic Symbol Conditions Min Typ Max Unit
Hi-Z State Data Line Leakage ILO 0V<Vin<3.3V –10 +10 µA
Differential Input Sensitivity VDI |(D+)–(D–)| 0.2 V
Differential Common Mode Range
VCMIncludes VDI
range0.8 2.5 V
Single Ended Receiver Threshold
VSE 0.8 2.0 V
Static Output Low VOLRL of 1.5k to
3.6V0.3 V
Static Output High VOHRL of 15k to
GND2.8 3.6 V
3.3V External Reference Pin V3.3 IL=200µA 3.0 3.3 3.6 V
Table 13-1. DC Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
MC68HC05JB3 ELECTRICAL SPECIFICATIONS MOTOROLAREV 1 13-3
GENERAL RELEASE SPECIFICATION November 5, 1998
13.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS
NOTES:1. All voltages measured from local ground, unless otherwise specified.2. All timings use a capacitive load of 50pF, unless otherwise specified.3. Low speed timings have a 1.5k pull-up to 2.8V on the D– data line.4. Measured from 10% to 90% of the data signal.5. The rising and falling edges should be smooth transitions (monotonic).6. Timing differences between the differential data signals.7. Measured at crossover point of differential data signals.8. Capacitive loading includes 50pF of tester capacitance.
Table 13-3. USB Low Speed Source Electrical Characteristics
Parameter SymbolConditions
(Notes 1,2,3)Min Typ Max Unit
Transition time:Rise Time
Fall Time
TR
TF
Notes 4, 5, 8CL=50pFCL=350pFCL=50pFCL=350pF
75
75300
300
nsnsnsns
Rise/Fall Time Matching TRFM TR/TF 80 120 %
Output Signal CrossoverVoltage
VCRS 1.3 2.0 V
Low Speed Data Rate TDRATE 1.5Mbs ±1.5%1.4775676.8
1.500666.0
1.5225656.8
Mbsns
Source Differential Driver JitterTo Next TransitionFor Paired Transitions
TUDJ1TUDJ2
CL=350pFNotes 6 and 7
–25–10
2510
nsns
Receiver Data Jitter ToleranceTo Next TransitionFor Paired Transitions
TDJR1TDJR2
CL=350pFNotes 7
–75–45
7545
nsns
Source EOP Width TEOPT Note 7 1.25 1.50 µs
Differential to EOP Transition Skew
TDEOP Note 7 –40 100 ns
Receiver EOP WidthMust Reject as EOPMust Accept
TEOPR1TEOPR2
Note 7 330675
nsns
MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05JB313-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
13.6 CONTROL TIMING
NOTES:1. The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the
interrupt service routine plus 19 tCYC.2. Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C)3. tslow is a parameter dependent on fOSC and loading. Typical value of tslow is TENTATIVELY set at 170 ns
with minimal value of 130ns and maximal value of 185ns under the SIMULATION conditions that fOSCis 6.0 MHz and slow output transition feature is enabled. Actual transition time will be specified toreplace the TBDs when enough characterization has been done on various wafers from different lots.The values listed here represent data off simulation runs under the specified conditions. Under no cir-cumstances should they be treated as the final specification.
Table 13-4. Control Timing
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic Symbol Min Max Units
Frequency of OperationCrystal Oscillator OptionExternal Clock Source
fOSCfOSC
—DC
66
MHzMHz
Internal Operating FrequencyCrystal Oscillator (fOSC ÷ 2)External Clock (fOSC ÷ 2)
fOPfOP
—DC
33
MHzMHz
Cycle Time (1/fOP) tCYC 330 — ns
RESET Pulse Width Low tRL 1.5 — tCYC
IRQ Interrupt Pulse Width Low (Edge-Triggered) tILIH 0.5 — tCYC
IRQ Interrupt Pulse Period tILIL note 1 — tCYC
PA0 to PA3 Interrupt Pulse Width High(Edge-Triggered)
tIHIL 0.5 — tCYC
PA0 to PA3 Interrupt Pulse Period tIHIH note 1 — tCYC
OSC1 Pulse Width tOH, tOL — — ns
Output High to Low Transition Period onPA6, PA7, PB0-4
tSLOW ns
MC68HC05JB3 ELECTRICAL SPECIFICATIONS MOTOROLAREV 1 13-5
GENERAL RELEASE SPECIFICATION November 5, 1998
MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05JB313-6 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
SECTION 14MECHANICAL SPECIFICATIONS
This section provides the mechanical dimensions for the 20-pin SDIP, and28-pin SDIP, 20-pin SOIC, and 28-pin SOIC packages.
14.1 20-PIN PDIP (CASE 738)
Figure 14-1. 20-Pin PDIP Mechanical Dimensions
14.2 28-PIN PDIP (CASE 710)
Figure 14-2. 28-Pin PDIP Mechanical Dimensions
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J 20 PL
MBM0.25 (0.010) T
DIM MIN MAX MIN MAXMILLIMETERSINCHES
A 25.66 27.171.010 1.070B 6.10 6.600.240 0.260C 3.81 4.570.150 0.180D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSCJ 0.21 0.380.008 0.015K 2.80 3.550.110 0.140L 7.62 BSC0.300 BSCM 0 15 0 15 N 0.51 1.010.020 0.040
E1.27 1.770.050 0.070
1
11
10
20
–A–
SEATINGPLANE
K
N
FG
D 20 PL
–T–
MAM0.25 (0.010) T
E
B
C
F1.27 BSC0.050 BSC
°
°
°
°
! ! !
#! %% !$" ! ! ! ! ! !
! ! #
! "
1 14
1528
B
A C
N
K MJ
D
FH G
L
MC68HC05JB3 MECHANICAL SPECIFICATIONS MOTOROLAREV 1 14-1
GENERAL RELEASE SPECIFICATION November 5, 1998
14.3 20-PIN SOIC (CASE 751D)
Figure 14-3. 20-Pin SOIC Mechanical Dimensions
14.4 28-PIN SOIC (CASE 751F)
Figure 14-4. 28-Pin SOIC Mechanical Dimensions
NOTES:1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.13(0.005) TOTAL IN EXCESS OF D DIMENSIONAT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
SAM0.010 (0.25) B ST
D20X
MBM0.010 (0.25)P10X
J
F
G18X K
C
–T– SEATINGPLANE
M
R X 45
DIM MIN MAX MIN MAXINCHESMILLIMETERS
A 12.65 12.95 0.499 0.510B 7.40 7.60 0.292 0.299C 2.35 2.65 0.093 0.104D 0.35 0.49 0.014 0.019F 0.50 0.90 0.020 0.035G 1.27 BSC 0.050 BSCJ 0.25 0.32 0.010 0.012K 0.10 0.25 0.004 0.009M 0 7 0 7 P 10.05 10.55 0.395 0.415R 0.25 0.75 0.010 0.029
°
°
°
°
! !
% ! ! ! "
!" $" !"
! "
!" # !" !! $ ! $" !!
-A-
-B-
1 14
1528
-T- C
M
J
-T-
K
26X G
28X D
14X P
R X 45°
F
!
MOTOROLA MECHANICAL SPECIFICATIONS MC68HC05JB314-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
APPENDIX AMC68HC705JB3
This appendix describes the MC68HC705JB3, the emulation part forMC68HC05JB3. The entire MC68HC05JB3 data sheet applies to theMC68HC705JB3, with exceptions outlined in this appendix.
A.1 INTRODUCTION
The MC68HC705JB3 is an EPROM version of the MC68HC05JB3, and is avail-able for user system evaluation and debugging. The MC68HC705JB3 is function-ally identical to the MC68HC05JB3 with the exception of the 2560 bytes userROM is replaced by 2560 bytes user EPROM. Also, the mask options available onthe MC68HC05JB3 are implemented using the Mask Option Register (MOR) inthe MC68HC705JB3.
The MC68HC705JB3 is not available in the 20-pin SOIC package.
A.2 MEMORY
The MC68HC705JB3 memory map is shown in Figure A-1.
A.3 MASK OPTION REGISTER (MOR)
The Mask Option Register (MOR) is a byte of EPROM used to select the featurescontrolled by mask options on the MC68HC05JB3. In order to program this regis-ter the MORON bit in PCR need to be set to “1” before doing the EPROM pro-gramming process.
COPEN – COP Enable1 = COP watchdog function disabled.0 = COP watchdog function enabled.
IRQTRIG – IRQ, PA0-PA3 Interrupt Option1 = Edge-triggered only.0 = Edge-and-level-triggered.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MOR RCOPEN IRQTRIG PULLREN PAINTEN OSCDLY LVREN
$01FF W
reset: 0 0 1 1 1 1 1 1
MC68HC05JB3 MOTOROLAREV 1 A-1
GENERAL RELEASE SPECIFICATION November 5, 1998
PULLREN – Port A, B, and C Pull-up/down Option1 = Connected.0 = Disconnected
PAINTEN – PA0-PA3 External Interrupt Option1 = External interrupt capability on PA0-PA3 disabled.0 = External interrupt capability on PA0-PA3 enabled.
OSCDLY – Oscillator Delay Option1 = 224 internal clock cycles.0 = 4064 internal clock cycles.
LVREN – LVR Option1 = Low Voltage Reset circuit enabled.0 = Low Voltage Reset circuit disabled.
Figure A-1. MC68HC705JB3 Memory Map
$003F
$0000
I/O Registers
64 Bytes
EPROM Program Control Register $003E
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
$1FF6
$1FF3
$1FF4
$1FF5
$1FF2
$1FF1
Reserved
USB Vector (Low Byte)
Timer1 Vector (Low Byte)
USB Vector (High Byte)
Timer1 Vector (High Byte)
MFT Vector (Low Byte)
MFT Vector (High Byte)
Reserved
$1FF0Reserved
Reserved
IRQ Vector (High Byte)
IRQ Vector (Low Byte)
SWI Vector (High Byte)
SWI Vector (Low Byte)
Reset Vector (High Byte)
Reset Vector (Low Byte)
I/O Registers64 Bytes
$0000
$003F $0040
$006F
Unused48 Bytes
User RAM144 Bytes
64 Byte Stack
$0070
$00C0
$00FF
$13FF
Unused4608 Bytes
$1400
$1DFF$1E00
$1FEF
User EPROM2560 Bytes
Bootloader ROM496 Bytes
User Vectors16 Bytes
$1FF0
$1FFF
Mask Option Register$01FF
Unused: 256 Bytes
MOTOROLA MC68HC05JB3A-2 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
A.4 BOOTSTRAP MODE
Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin isat VTST and the PB0 pin is at logic zero. The Bootloader program is masked in theROM area from $1E00 to $1FEF. This program handles copying of user code froman external EPROM into the on-chip EPROM. The bootload function has to bedone from an external EPROM. The bootloader performs one programming passat 1ms per byte then does a verify pass.
The user code must be a one-to-one correspondence with the internal EPROMaddresses.
A.5 EPROM PROGRAMMING
Programming the on-chip EPROM is achieved by using the Program Control Reg-ister located at address $3E.
Please contact Motorola for programming board availability.
A.5.1 EPROM Program Control Register (PCR)
This register is provided for programming the on-chip EPROM in theMC68HC705JB3.
MORON – Mask Option Register ON0 = Disable programming to Mask Option Register ($01FF)1 = Enable programming to Mask Option Register ($01FF)
ELAT – EPROM LATch control0 = EPROM address and data bus configured for normal reads1 = EPROM address and data bus configured for programming (writes
to EPROM cause address and data to be latched). EPROM is inprogramming mode and cannot be read if ELAT is 1. This bit shouldnot be set when no programming voltage is applied to the Vpp pin.
PGM – EPROM ProGraM command0 = Programming power is switched OFF from EPROM array.1 = Programming power is switched ON to EPROM array. If ELAT≠1,
then PGM=0.
Bits [7:3] – ReservedThese are reserved bits and should remain zero.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PCR R 0 0 0 0 0MORON ELAT PGM
$003E W R R R R R
reset: 0 0 0 0 0 0 0 0
R = Reserved
MC68HC05JB3 MOTOROLAREV 1 A-3
GENERAL RELEASE SPECIFICATION November 5, 1998
A.5.2 Programming Sequence
The EPROM programming sequence is:
1. Set the ELAT bit
2. Write the data to the address to be programmed
3. Set the PGM bit
4. Delay for a time tPGMR
5. Clear the PGM bit
6. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
CAUTION
It is important to remember that an external programming voltage must be appliedto the VPP pin while programming, but it should be equal to VDD during normaloperations.
Figure A-2 shows the flow required to successfully program the EPROM.
MOTOROLA MC68HC05JB3A-4 REV 1
November 5, 1998 GENERAL RELEASE SPECIFICATION
Figure A-2. EPROM Programming Sequence
A.6 EPROM PROGRAMMING SPECIFICATIONS
Table A-1. EPROM Programming Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Programming VoltageIRQ/VPP VPP 10 12 15 V
Programming CurrentIRQ/VPP IPP — 3 — mA
Programming Timeper byte tEPGM 1 4 — ms
START
ELAT=1
Write EPROM byte
PGM=1
Wait 1ms
PGM=0
ELAT=0
Writeadditional
byte?
N
Y
END
MC68HC05JB3 MOTOROLAREV 1 A-5
GENERAL RELEASE SPECIFICATION November 5, 1998
MOTOROLA MC68HC05JB3A-6 REV 1
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