HCC OverviewMitch Newcomer

for Francis Anghinolfi, Michelle Key Charriere, Joel Dewitt, Nandor Dressnandt, Amogh Halgeri,

Paul Keener, Daniel Lamarra, Aditya Narayan

HCC Block Diagram (2012)

2 bits GPIO

HCC ASIC• Interface ASIC between:

• ABC130 front end readout ASICs grouped in sensor determined units (Hybrid)• High speed control/readout provided by the GBT servicing groups of Hybrids.

• GBT generated Control Signals - differential signals delivered over multi-drop bus.• BC 40MHz clock BC Phase encoded control signals• CMD_L0 - ‘CMD’ (rising edge) and ‘L0’ (falling edge) on common diff. pair.

CMD - (40MHz data Rate) - used internally to set operational modes and control readback of status information and regenerated to send to ABC.L0 - (40MHz data rate)Received and regenerated, delayed to ABC130’s.

• R3_L1 - ‘R3’ Rising edge and ‘L1’ falling edge on common diff. pair.

R3 – Regional Readout Request 26 bits - 3bits start, 14 bits module pos.,8bits L0ID, 1bit trailL1 -- Readout L1 12 bits- 3bits start, 8bits L0ID, 1bit trail

HCC ASIC Hybrid Side Control Signals

• BC Hybrid – Delayed version of BC that may be ePll synthesized • CMD_L0 - Delayed, otherwise unchanged, broadcast to ABC130’s on hybrid.• R3s_L1 - Module selection bits stripped from R3 to make R3s and L1 R3s_L1 delayed, Broadcast to ABC130’s on Hybrid. • DRC - ePLL synthesized 80 or 160MHz Data Rate Clock

• HCC Data Out - Point to point, programmable current differential drive with pre-emphasis.

160Mbps baseline Barrel (26hybrids*160Mbps ~4.2GBPS/GBT)

320Mbps upgraded or multiple GBT’s

Pad ring collaboratively designed with hybrid designersHCC Layout (2014)

Sides Mirrored for symmetric Bonding

Sides Mirrored for symmetric Bonding

4700um x 2860um 83 I/O padsDual pad-ring

List of major Blocks Digital• Command Decoder / R, W, read&clear registers• Data Concentrator• Coarse / Fine Delay, Half Fine delay

Mixed Analog and Digital• ePll (CERN GBT) – Heart of HCC design • BandGap (CERN GBT) – Unresolved extracted NL( powerup ~1.2V) issue. • Voltage Regulator (CERN/Penn) • Analog Monitor

I/O • Receiver with Hysteresis• 160MHz Driver• Pre Emphasis Driver ( Extracted NL shows good perf to 800MHz )

ePll

8

ePll Block diagram

Filip Tavernier - CERN

0° *0°22.5°45°67.5°90°112.5°135°157.5°180°202.5°225°247.5°270°292.5°315°337.5°

VCO 320 MHz

PFD

ePllR

efer

ence

(0/

40/8

0/16

0 M

Hz)

CP LPF

40/80/160 MHz

ePll320MHzA/B/C

ePllPhase320MHzA/B/C[3:0]

ePllEnablePhaseA/B/C[7:0]

ePllPhase160MHzA/B/C[4:0]

ePllResetA/B/C

ePllCapA/B/C[1:0]

ePllResA/B/C[3:0]

ePllIcpA/B/C[3:0]

LockDetector

ePll Instant Lock

ePllReferenceFrequencyA/B/C[1:0]

ePllPhaseShifter

Feedback Clock

ePll160MHz AePll160MHz B

ePll160MHz C

Measurements of ePll @CERNGuidance to HCC group for choice ofDefault Setup

Guidance to HCC group for choice ofDefault Setup

Design Team: Sandro Bonacini, Rui Reancisco, Paulo Moriera, Karolina Poltorak

ePll measurements Filip Tavernier

Design Specific VerificationFunctional Test Bench created by Joel Dewitt (UCSC)

HCC instantiated with wires (named nets) Initialized and run through a task driven input file.

• Generalized investigation using graphics interface eg. “simvision”• Function Specific tests results listed in output stream.

Design Verification using the Test Bench

L0 sampled at the falling edge of the clk.

The CMD signal is sampled at the rising edge of the clk

BC

BC

L0L0 Registered

CMD Registered

CMD

HCC Hybrid Level Verification Michelle Key Charriere (RAL)

Test Bench generated Command Signals

Hybrid

ABC130

HCC

HCC DATA OUT

Verification Engine

• Compatibility of Control Signals?• Margin? Clock / PLL phasing • Delay Generation • Data thru-put? Congestion?• Data Fidelity

Data, Delays, Pileup

Test Bench input

BC, CMD_L0,R3_L1

BC, DRC CMD_L0, R3s_L1

Data Out

LoopData, Xon/off

BC_Stave Jitter Study Pointed out the benefit of a PLL synth. BC to Hybrid…

Project File Management (SVN)• All official project files are stored in a CERN-hosted SVN code

repository• RTL verilog, test benches, synthesis / P&R scripts• Cadence libraries for macro cells, placeholder verilog blocks, .lib file etc.

• Enables designers to work in parallel with common base design• Enables change tracking and backtracking

Expanded HCC Features/Description

Nandor Dressnandt

HCC Functionality• Receive data/clock from GBT (Stave Side BC_STAVE clock, phase encoded data L0_CMD, R3_L1)• Adjust data/clock delays to account for physics - particle time of flight differences at different locations in the detector.

• Programming delay macros and ePLL can achieve more than a full period delay for all clocks (40MHz, 160MHz, 320MHz, 640MHz)• Remove Hybrid address from R3_L1 data packet to generate R3s_L1 only when hybrid is addressed• Provide BC (40MHz) clock and data (R3s_L1, L0_CMD) to Hybrid chips (ABC130’s)• Provide ePll generated 160MHz Data Readout Clock (DRC) to Hybrid chips• Receive data from Hybrid chips with Xoff mechanism• Encode data into serial stream and send back to GBT at 320MHz• Provide debugging start-up mode at 40MHz

• Implement Fail-Safe Interlock to protect Hybrid chips – Autonomous Monitor• Monitor Temp, Voltage, Current• Automatically turn off clocks and/or power to ABC130 chips if necessary

• Provide two (programmable) clocking modes: • Use received 40MHz GBT clock (BC_STAVE) to sample data and pass along to Hybrids

• Ok if have high quality GBT clock/data – missing pulse or glitch will invalidate data• Never any start-up phasing issues w.r.t GBT data

• Use ePLL- generated clock to resample data and pass along to Hybrids• Tolerant to corrupted GBT clock (missing pulses or glitches)• But Sensitive to phasing issues w.r.t. GBT data – phase checking/correction logic required• NOTE: Command Decoder must always run on BC_STAVE. (ePLL clock is not available during startup)• Unclear how Data Concentrator performs when missing 160/320MHz clock??

HCC• Features

• Common Chip Ground Reference (GND – 9 pads)• Unregulated Voltage DVDD – 4 pads• Regulated Voltage VDD – 5 pads (Used to bypass regulator for testing)• Digital comparator (DFF) to test analog part of delay-chain in Delay Macros• Pad to monitor PCB ground-reference (weakly coupled to HCC ground GND)• 6 Test pads: Bandgap voltage, maybe ePll control voltage, other?? • Duplicated pads left/right to fit onto left/right flavor Hybrids• SEU tolerance: Key registers are triplicated• BF Moat free –except for one Macros: prompt circuit (Detects Nuclear detonation)• Pre-emphasis driver to compensate for data degradation over Stave transmissionline to GBT - programmable• Stave-side data receivers have hysteresis to permit AC coupling of Stave signals. • No hysteresis in stave clock receiver (BC_STAVE) – avoids duty cycled degradation• ABC130 Data receivers have programmable (2x40) 80 Ohms termination to accommodate adding external termination

if desired.• Components (* = used in ABC130 chip)

• Delay elements (coarse/fine, fine, very-fine)• I/O Drivers/Receivers *• ePLL• Autonomous Monitor• BandGap, RC filter, and Regulator * • HV monitoring OpAmp (4 scales to monitor leakage)• Temperature monitoring OpAmp (Diode based)• Power-on Reset *• Prompt circuits *

Penn 18

Hybrid Controller Chip (HCC) • Size: 4700um x 2860um; I/O pads: 83• Dual pad-ring structure to fit onto Hybrid• IBM Standard Cells: ~20,000 + 727 Decoupling caps (200pF total)• Nets: 22,942• Macros:

• Voltage Regulator• Band Gap• PLL /w 160, 320, and 640MHz (Modified GBT ePLL)• Delay Macos:

• Synchronous coarse delays (6.25ns/steps )• Asynchronous fine delays (1.2ns/steps)• Asynchronous half-fine delays (600ps/step)• Asynchronous very fine delay (200ps steps)

• “Coarse + fine” delays used for Hybrid-side signals (BC_Hybrid, R3sL1, CMDL0)• “half-fine” delays used for Data Readout Clock (DRC) and returning ABC130 Data • “Very fine” delay used for Phase delay of 640MHz Fast Cluster Finder Clock

• Autonomous Monitor (monitors chip health)• Power-on Reset• Prompt event circuit (USA export regulations)

• TCL script driven PnR (based on CERN code ) ~ 3600 lines of code• Verification: Verilog, STA (RC, Encounter), Spectre