hdl-based design methodology of 16-bit risc microprocessor.pdf

8/14/2019 HDL-Based Design Methodology of 16-bit RISC Microprocessor.pdf

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3rdInternational Conference on Advanced Manufacturing Technology (ICAMT 2004),11-13 May, Kuala Lumpur, Malaysia

HDL-BASED DESIGN METHODOLOGY OF 16-bit RISC MICROPROCESSOR

Ismail Saad1, Pukhraj Vaya

1, Abu Bakar Abd Rahman

2

1Lecturer,

2MSc Student School of Engineering and Information Technology

University Malaysia Sabah, Locked Bag 2073, 88999 Kota Kinabalu, Sabah, MalaysiaTel: +60-8-832-0000 x 3147/3066, Fax: +60-8-832-0348

(e-mail: [email protected], [email protected], [email protected])

Abstract

This paper presents the design and simulation of 16-bit RISC processor architecture behavioral model based onHDL methodology using Verilog-HDL software. The processor system consists of ROM, RAM, I/O and CPU.The CPU module is merely a shell which instances the real processor definition in cpu_core.v, control.v,datapath.v and alsu.v file. Behavioral model of control module which comprises of controller state machine,Instruction Register (IR) and a group of Control Signals are explained thoroughly. The tasks of modeling Read,

Write and Tristate buffer operation for datapath module are also deeply being explained. The functionality of theprocessor design was tested by executing three instructions type. Thus, it is shown that Verilog-HDL can be usedto improve the design process of new microprocessor architecture.

Keywords: Verilog- HDL, RISC, Behavioral Model, Register, Microprocessor

1. Introduction

Microprocessor application is not limited topersonal computer but also used in a specific fieldsuch as robotics, communications, control systems, etc[1-5]. However, the process of designing a newprocessor for such application is very complicated, asit involves million transistors in single chips [6-9].

Therefore, in order to improve the design process andthus minimizing error, time and cost, VerilogHardware Description Language (Verilog-HDL) is asoftware tool that can be used to simulate and verifythe functionality of the microprocessor componentsbefore the real device were fabricated [9-13]. Thus,

the paper presents a design and simulation of 16-bitsRISC processor based on HDL methodology usingVerilog-HDL on Synopys Front-end Compiler.

2. Processor Architecture

The processor has a multiplexed 16-bit data and

address path. The instructions has a variable length, asit take one word for instruction that operates withinRegisters only and two words for instructions operateson Registers/Memory and Register/Immediate . The16-bits instruction fields consists of 2-Mode bit, 1-biteach for Set Condition (set_bit) and Test Condition(test_bit), 3-bit ALU Function (ALU_func) and 3-bit

each for Destination Register (Rd), Source- 1 Register(Rs1) and Source-2 Register (Rs2). The processor canexecute 36 instructions, which are grouped into 2instruction type; Arithmetic/Logical and Load/StoreInstructions. There are six registers in the processorwhere 3 of them are general purpose while the other 3

are dedicated register that is PC (Program Counter),IR (Instruction Register) and DR (Direct Register). Ontop of that, a dummy register (always zero) is alsoincluded in the register file.

3. Verilog-HDLModel forProcessor SystemThe system of processor consists of 256 words of

ROM (addresses 0-255), 256 words of RAM(addresses 256-511) and I/O consisting of a bank of 16switches (mapped at address 512) and a bank of 16LEDs (mapped at address 513). The cpu.v file is

merely a shell which simulates the pad ring and whichinstances the real processor definition in the followingfiles:

cpu_core.v

d tapath.va

control.v

4. Verilog HDL Module Codes4.1 Cpu_Core Module

This module has a single internal systemaddress/data bus. Because of a single bus system, all

the data from memory, Data_inmust pass through atri-state, TrisMemcontrol signal before connection tosystem bus. Furthermore, this module instances thedefinition of control and datapath modules ofprocessor.

4.2 Control Module

Two main functions of control module is toexecute operations in proper sequence by means ofcontroller state machine and to generates the controlsignals that cause each instructions to be executed.

alsu.v

1
mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]


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The control module consists of 16-bit InstructionRegister (IR), 1-bit zero flag register the controllerstate machines and sub states of memory cycles andthe different type of generated control signals asillustrated in figure 1 below.

4.2.1 Controller State Machine

The controller state machine has three states:

Fetch1 (00),Fetch2 (11) and Execute (01)that codedby using gray code. Furthermore, it also has 4 memory

cycles sub states: address_setup (00), address_hold

(01), data_setup (11) and data_hold (10). Fordistinguish transitions of operation from one state toanother, the data_holdsub state of memory cycle andthe 2-mode bit fields of instruction has been used.Generally, Fetch1 state is for Register + Register

instruction type, which use 4 clock cycle or 1 memorycycle to be executed. Execute state is for Register +Immediate instruction type, that use 8 clock cycle or 2memory cycles to be executed. For Load and Storeinstruction type, which is the longest instruction to beexecuting, Fetch2 and Execute state is used for 3

memory cycles or 12 clock cycles. Hence, allinstructions are complete in exactly 12 clock cycles.

This controller state machine has been coded inverilog by using case statement and in general thealgorithm can be view as below.

4.2.2 Instruction Register and Zero Flag Register

Any instructions that stored in rom.v file will betaken into system bus if the tri-state buffer, TrisMemgoes high. This instruction from the system bus will

be taken into Instruction Register (IR) during the

Fetch1state and data_setupsub state of memory cycleand sequentially the IR will be updated. This operationwill only occur in the positive edge of the clock cycle.For behaviourally model the task of taken instructionfrom system bus to IR in control module, the ifstatementof verilog code has been used as below.

State :

0: Fetch1

always @(posedge Clock)begin

if ((state == `Fetch1) && (sub_state == `data_setup ))IR


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The behavioural model of the first group of controlsignals is written in verilog using assignment asfollow:

assign memory_write = (Opcode == `ST) && (state ==Èxecute);assign nME = ( sub_state == address_setup ) || (

sub_state == data_hold );assign nALE = ( sub_state == address_setup );assign RnW = ( sub_state == address_setup ) || (

sub_state == àddress_hold )|| ~memory_write;assign nOE = ( sub_state == àddress_setup ) || (

sub_state == address_hold ) || memory_write;assign ENB = ~nOE;

For the second group of control signals, there are 5tri-state buffers (TrisALU, TrisPC, TrisRs2, TrisRdand nTrisRd) for datapath unit and only 1 (TrisMem)

for memory. The behavioural model for each of thesesignals is carried out in verilog by using a continuousassignment statement. Following are the conditions ofa continuous assignment statementfor each of the tri-state buffer control signals for System bus assignment:

1.TrisMem: sub state is either data_setup ordata_hold and state is either Fetch1 or Fetch2 orExecutewithModeBit is either 10 or 01.

2.TrisALU: sub state is either address_setup oraddress_hold and state is Executewith ModeBit iseither 11 or 10.

3.TrisPC: sub state is either address_setup oraddress_holdand state is eitherFetch1orFetch2or

ExecutewithModeBit of 01.4. TrisRs2: sub state is either data_setup or

data_holdand on memory_writeandModeBit is 11.5.TrisRd:sub state is data_setupand state isExecute

andModeBit is 10.6.nTrisRd:inverse of TrisRd (~TrisRd).

As for example, the behavioral model of TrisMemTri-state buffers is return as follow:

assign TrisMem = ( (sub_state == `data_setup ||

sub_state == `data_hold ) && (state == `Fetch1 || state ==`Fetch2 || ( state == Èxecute && (ModeBit == 2'b10 ||ModeBit == 2'b01))));

For behaviourally model the third groups ofcontrol signals, which is the datapath unit control

signals, 2 decoder for read and write control signals isneeded. This decoder is required as a control for read

the contents of any one of 5 general-purpose registersin datapath unit (PC, R0, R1, R2 and R3) and forwrites any results or computed data into any one of 4general-purpose register (R1, R2, R3 and PC). A

continuous assignment statementof verilog is used tocode the two-decoder signal (En_read_dec and

En_wrt_dec) and the multiplexors using continuousassignmentis used to select which signals for read andwrite from and to selected registers in datapath unit

respectively. Following is the condition for astatement of En_read_dec and En_wrt_dec controlsignals:

1. En_read_dec: state isFetch1andModeBit is 00 orstate isExecute andModeBitis either 01 or 10 or 11

or state isFetch2andModeBitis either 11 or 10.2. En_wrt_dec: state is Fetch1 and sub state is

data_hold andModeBit is 00 or state is Execute and

sub state is data_setup andModeBitis 10 or state isExecute and sub state is data_hold and ModeBit is01 andzero_flag reg is TRUE and testbitis either 1

or 0.

As for example, the behavioral model of decoder(En_read_dec) is return in verilog as below:

assign En_read_dec = ((state == `Fetch1 && ModeBit ==

2'b00) || (state == Èxecute && (ModeBit == 2'b01 ||ModeBit == 2'b10 || ModeBit == 2'b11)) || (state ==`Fetch2 && (ModeBit == 2'b11 || ModeBit == 2'b10)));

Both read and write operation that coded by using

the multiplexors using continuous assignment mustsatisfied the En_read_dec and En_wrt_dec control

signals respectively together with the source1 register(Rs1) and source2 register (Rs2) instruction field forread and destination register (Rd) field for writeoperation. The control signals for read operation forsource1 register (Rs1) are named as: ReadR0_1,ReadR1_1, ReadR2_1, ReadR3_1 and ReadPC_1and

for source2 register (Rs2) is called as: ReadR0_2,ReadR1_2, ReadR2_2, ReadR3_2 and ReadPC_2. Incontrast, the control signals for write operation areidentify as: WriteR1, WriteR2, WriteR3 and WritePC.For example, the behavioral model of multiplexors ofverilog code for read (read from R0_1) and write

(write to R1) operation is given below:

assign WriteR1 = (En_wrt_dec && Rd == 3'b001 ? 1 : 0;assign ReadR0_1=( En_read_dec && Rs1 == 3'b000 ?1: 0;

Another control signals for datapath that generatedin control unit are Rs2_sel, PC_inc, LoadDR and

LoadPC. All of this control signals is behaviourallycoded in verilog by using continuous assignmentstatement. As for example, following is the behavioralmodel ofPC_inc:

assign PC_inc = ((sub_state == address_hold ) &&(( state == `Fetch1 ) || ( state == `Fetch2 ) || (state

== Èxecute && ModeBit == 2'b01 ) ));

The control signal for alsu function, called asFunction is coded as ALUfunc or the 3-bit of alsufunction in instruction field format that define byusing a continuous assignment statement of verilogcode as follows:

assign Function = ALUfunc;

The asynchronous reset assign that overrides thesynchronous action ofstate, sub state, IR and zero flagregister must be included in this system of control unitas a normal method for the description of an

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asynchronous reset within synchronous sequentiallysystem as follow:

always @(nReset)if (!nReset) begin

assign state = 0; assign sub_state = 0;

assign IR = 0; assign zero_flag_reg = 0;

endelse begin

deassign state; deassign sub_state;deassign IR; deassign zero_flag_reg;

end

4.3 Datapath Module

The following are the main task of datapath unit

that has to be behaviourally model by verilog code tosuit the definition of design processor as can be view

in figure 2:

1.To model the read operation for both Rs1 (source1register) and Rs2 (source2 register) from any one of5 available register (R0, R1, R2, R3, PC).

2.To model the write operation for Rd (destinationregister) from any one of 4 available register (R1,R2, R3, PC).

To model the write operation for Rd (destination

register) from any one of 4 available register (R1,R2, R3, PC).

3.To model the tri-state buffer (TrisALU, TrisPC,TrisRs2, TrisRd) for system bus.

3.To model the tri-state buffer (TrisALU, TrisPC,TrisRs2, TrisRd) for system bus.

For the first task, the multiplexors using

continuous assignment structure of tri-state is used.All of the previously defined control signals fordatapath from control unit specifically for readoperation have been used in this structure. As can be

seen from figure2, each register for read is control bytri-state, thus if the register (Rs1 or Rs2) is not

selected it will be in high impedance state. For

example, the continuous assignment for Rs1 that willselects R2 if the control signal ReadR2_1 is 1 and ifReadR2_1 is 0 Rs1 will be in high impedance stateis coded in verilog as follow:

For the first task, the multiplexors usingcontinuous assignment structure of tri-state is used.All of the previously defined control signals fordatapath from control unit specifically for readoperation have been used in this structure. As can be

seen from figure2, each register for read is control bytri-state, thus if the register (Rs1 or Rs2) is notselected it will be in high impedance state. For

example, the continuous assignment for Rs1 that willselects R2 if the control signal ReadR2_1 is 1 and ifReadR2_1 is 0 Rs1 will be in high impedance stateis coded in verilog as follow:

assign Rs1 = ( ReadR2_1 ) ? R2 : 16bz;assign Rs1 = ( ReadR2_1 ) ? R2 : 16bz;

The same structure applied for all others register

(R0, R1, R3, and PC) both for Rs1 and Rs2.

The same structure applied for all others register

(R0, R1, R3, and PC) both for Rs1 and Rs2.

In second tasks, the Procedural Block and if

statementof verilog is used. For write operation, it canonly happen in the rising or positive edge of clock,thus the procedural block used here. For write to

destination register (Rd), all the generated controlsignals from control unit specifically for this operation(LoadPC, WriteR1, WriteR2, WriteR3 and LoadDR) isused as a condition inside the if statement. Thecomplete verilog code of this task is return as below:

In second tasks, the Procedural Block and if

statementof verilog is used. For write operation, it canonly happen in the rising or positive edge of clock,

thus the procedural block used here. For write todestination register (Rd), all the generated controlsignals from control unit specifically for this operation(LoadPC, WriteR1, WriteR2, WriteR3 and LoadDR) isused as a condition inside the if statement. Thecomplete verilog code of this task is return as below:

always @(posedge Clock)always @(posedge Clock)beginbeginif (LoadPC) PC = Mux1_out;if (LoadPC) PC = Mux1_out;

if (WriteR1) R1 = Rd;if (WriteR1) R1 = Rd;if (WriteR2) R2 = Rd;if (WriteR2) R2 = Rd;

if (WriteR3) R3 = Rd;if (WriteR3) R3 = Rd;if (LoadDR) DR = Sysbus;if (LoadDR) DR = Sysbus;endend

Note that, LoadPCand LoadDRcontrol signals isnot directly use for destination register, (Rd). LoadDRis for controlling a write operation from system bus to

Data Register (DR), whileLoadPCis use for control awrite operation from the multiplexor1 output

(Mux1_out) toProgram Counter, PC.LoadPCcontrolsignal is necessary because of the architecture of thedesign processor that allow any value to be write intoPC, thus a multiplexor is needed for selecting between

2 of the PC functions: automatically increased oraccept value that write to it as a destination register

(Rd). From figure 2, there are 2 multiplexors, one isfor selecting PC function, called as Mux1_outand theother is for selecting between Rs2 (source2 register)and DR (Data Register) data value, called as

Mux2_out. Mux2_out multiplexor used Rs2_selcontrol signal generated from control unit for

accomplish the task of selecting Rs2 or DR, whileMux1_outusedPC_inccontrol signal. ThisMux2_outis necessary for distinguish between an execution ofR+R instruction (Rs2 is selected) or R+I instruction(DR is selected). Both multiplexors have been coded

in verilog by using continuous assignment formultiplexoras below:

Note that, LoadPCand LoadDRcontrol signals isnot directly use for destination register, (Rd). LoadDRis for controlling a write operation from system bus toData Register (DR), whileLoadPCis use for control awrite operation from the multiplexor1 output(Mux1_out) toProgram Counter, PC.LoadPCcontrol

signal is necessary because of the architecture of thedesign processor that allow any value to be write into

PC, thus a multiplexor is needed for selecting between

2 of the PC functions: automatically increased oraccept value that write to it as a destination register(Rd). From figure 2, there are 2 multiplexors, one is

for selecting PC function, called as Mux1_outand theother is for selecting between Rs2 (source2 register)

and DR (Data Register) data value, called asMux2_out. Mux2_out multiplexor used Rs2_selcontrol signal generated from control unit foraccomplish the task of selecting Rs2 or DR, while

Mux1_outusedPC_inccontrol signal. ThisMux2_outis necessary for distinguish between an execution of

R+R instruction (Rs2 is selected) or R+I instruction(DR is selected). Both multiplexors have been coded

in verilog by using continuous assignment formultiplexoras below:

assign Mux1_out = (PC_inc) ? PC + 1:Rd;assign Mux1_out = (PC_inc) ? PC + 1:Rd;assign Mux2_out = (Rs2_sel) ? Rs2 : DR;assign Mux2_out = (Rs2_sel) ? Rs2 : DR;

For the third tasks, the same structure ofmultiplexor using continuous assignment for tri-state

that previously used for behaviourally model the firsttask is used. The following are the verilog code foreach of the tri-state buffer in datapath unit:

For the third tasks, the same structure ofmultiplexor using continuous assignment for tri-state

that previously used for behaviourally model the firsttask is used. The following are the verilog code foreach of the tri-state buffer in datapath unit:

assign Sysbus = (TrisALU) ? result:16bz;assign Sysbus = (TrisALU) ? result:16bz;

assign Sysbus = (TrisPC) ? PC:16bz;assign Sysbus = (TrisPC) ? PC:16bz;assign Sysbus = (TrisRs2) ? Rs2:16bz;assign Sysbus = (TrisRs2) ? Rs2:16bz;assign Sysbus = (TrisRd) ? Rd:16bz;assign Sysbus = (TrisRd) ? Rd:16bz;

assign Rd = (nTrisRd) ? result:16bz;assign Rd = (nTrisRd) ? result:16bz;

PC

R0

R1

R2

R3

DR

0

1

0

RsRs

ALU

Rd

Zero

16

16

1616

16

16

16

1

Rs2_sel

TrisRd

nTris

PC_inc

TrisRs2

Function

TrisALU

TrisPC

ReadPC_1

ReadPC_2

ReadR0_1ReadR0_2

ReadR1_1ReadR1_2

ReadR2_1ReadR2_2

ReadR3_1

ReadR3 2

WriteR1

WriteR2

WriteR3

LoadDR

Mux1_out

PC+1

Mux2_out

WritePC

Fig. 2. Processor Datapath Module Architecture

result

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Lastly, the asynchronous reset assign thatoverrides the synchronous action of all register indatapath unit must be included in this system as anormal method for the description of an asynchronous

reset within synchronous sequentially system.

4.3 ALSU Module

The final module in the Microprocessor is ALSU(Arithmetic & Logic Shift Unit) where basically it will

perform seven basic arithmetic & logic shift operation.On top of that, there is one Zero flag register included.The Zero flag was modeled using assignstatement asbelow:

ncluded.The Zero flag was modeled using assignstatement asbelow:

assign Zero = (result =0);assign Zero = (result =0);

The arithmetic & shift logic operation been codedusing procedural assignment with sequential logic

case statementas below ;

The arithmetic & shift logic operation been codedusing procedural assignment with sequential logic

case statementas below ;

always @(input1 or input2 or Function)always @(input1 or input2 or Function)

case (Function)case (Function)ÀDD : result = input1 + input2;ÀDD : result = input1 + input2;`SUB : result = input1 - input2;`SUB : result = input1 - input2;

ÀND : result = input1 & input2;ÀND : result = input1 & input2;ÒR : result = input1 | input2;ÒR : result = input1 | input2;`XOR : result = input1 input2;`XOR : result = input1 input2;

`NOT : result = ~input1;`NOT : result = ~input1;`SRA : result = input1 >> 1;`SRA : result = input1 >> 1;default : result = input1;default : result = input1;

endcaseendcase

5. Processor Functionality5. Processor Functionality

Verification of processor functionalities has beendone for the basic operation which includes arithmetic,logic and shift operation. The processor architecture

offers 36 types of instruction available to be used. Atthe simulation level the functionalities of the processor

been verified through timing diagram in every module.As for example only 3 types of instructions showedhere i.e: Register + Immediate, Register + Registerand Load Instructions.

Verification of processor functionalities has beendone for the basic operation which includes arithmetic,logic and shift operation. The processor architecture

offers 36 types of instruction available to be used. Atthe simulation level the functionalities of the processorbeen verified through timing diagram in every module.As for example only 3 types of instructions showedhere i.e: Register + Immediate, Register + Registerand Load Instructions.

5.1Register + Immediate Value operation5.1Register + Immediate Value operationRdRs1 (R1) Addi Imm16 (259 / 103hex); RdRs1 (R1) Addi Imm

This instruction perform add operation withinRegister1 (R1) and Immediate value (259) where theimmediate value 259 will be stored into Register 1.

Details of the process as shown in the figure 3 below:

This instruction perform add operation within

Register1 (R1) and Immediate value (259) where theimmediate value 259 will be stored into Register 1.

Details of the process as shown in the figure 3 below:

5.2Register + Register operation5.2Register + Register operationRd (R3)Rs1 (R1) ADDr Rs2 (R2)Rd (R3)Rs1 (R1) ADDr Rs2 (R2)

This instruction is used to perform add operationwithin Registers. In this example the instruction

involves arithmetic ADD operation between Register1 and Register 2 then output will be stored in theRegister 3. The immediate value 259(103hex) in theRegister 1 will be added with immediate value in theRegister 2: 93(5Dhex) that have been stored initiallythen result: 352(160hex) will be stored in the Register

3. Details of the process shown in the figure 4 below:

This instruction is used to perform add operation

within Registers. In this example the instruction

involves arithmetic ADD operation between Register1 and Register 2 then output will be stored in theRegister 3. The immediate value 259(103hex) in theRegister 1 will be added with immediate value in theRegister 2: 93(5Dhex) that have been stored initially

then result: 352(160hex) will be stored in the Register3. Details of the process shown in the figure 4 below:

Fig. 4. Timing Diagram of Register + Register

operation

5.3Load operation5.3Load operationRd (R2)mem[Rs1 (R0)+ SWITCHES]Rd (R2)mem[Rs1 (R0)+ SWITCHES]

This instruction is used to perform load operation.In this example the instruction involves load from`SWITCHES to Register 2. The content of memorylocations addresses at [`SWITCHES + Register

0(always zero)] will be loaded into destination register(Register 2). In the processor system the memorylocation for SWITCHES is mapped at address 512 and

the contents of SWITCHES is unsigned value 7.Details of the process shown in the figure 5 below:

This instruction is used to perform load operation.In this example the instruction involves load from`SWITCHES to Register 2. The content of memorylocations addresses at [`SWITCHES + Register

0(always zero)] will be loaded into destination register(Register 2). In the processor system the memory

location for SWITCHES is mapped at address 512 andthe contents of SWITCHES is unsigned value 7.Details of the process shown in the figure 5 below:

6. Conclusions6. Conclusions

A new and simple 16-bit RISC processor architecturehas successfully been design based on HDLmethodology and also a simulation with verification ofprocessor functionalities has been effectively doneusing Verilog-HDL software on Synopsys Compiler.This simple processor model can be used as a basic

platform in designing any specific-application inspecific field. The advantage of using HDLmethodology i.e Verilog-HDL software for designingany system such that it will improve the design

A new and simple 16-bit RISC processor architecturehas successfully been design based on HDLmethodology and also a simulation with verification ofprocessor functionalities has been effectively doneusing Verilog-HDL software on Synopsys Compiler.

This simple processor model can be used as a basic

platform in designing any specific-application inspecific field. The advantage of using HDLmethodology i.e Verilog-HDL software for designingany system such that it will improve the design

16 (259 / 103hex);

Fig. 5. Timing Diagram of Load operation

5

Fig. 3. Timing Diagram of Register + Immediate

operation


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6

process by minimizing error, time and cost and alsothe design system model are fully reusable as the codecan be changes accordingly for any specific need ofapplication.

7. References

[1] D.D Gajski, Principles of Digital Design, PrenticeHall, 1997

[2] M. Zwolinski, Digital System Design With VHDL,Prentice Hall, 2000

[3] D. A. Patterson & J.L. Hennesy, ComputerOrganization and Design - The Hardware/Software Interface, Morgan Kaufmann, 1999

[4] M. Morris Mano, Digital Logic and ComputerDesign, Prentice Hall, 1997

[5] I. McNally, EZ431/631 VLSI Group DesignProject-Microprocessor Specification Document,

University of Southampton, 2000

[6] Dally, W-J. Chang, A. The Role of Custom DesignIn ASIC Chips, Proceedings of the 37thconference on design automation, ACM Press, pg

643-647, 2000.[7] Flynn, M-J. Winner, R-I. ASIC microprocessor,

Proceedings of the 22nd annual internationalworkshop on microprogramming andmicroarchitecture, ACM Press, pg 237-243, 1989.

[8] Samir Palnitkar, Verilog HDL A Guide to DigitalDesign and Synthesis, Printice Hall, 1995

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International symposium on hardware/software

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Zamboni, M, Design and validation with HDL of

a complex input/output processor for an ATMswitch : the CMC, Verilog HDL conference,

Proceedings, pg 67-71, 1995.[11] Mahdi, A-E. Grout, I-A, PLL based ASIC system

for DSP real-time analogue interface,www.ece.ul.ie/hompage/ian_grout/publications.html ,2002.

[12] Arnold, M-G. Bailey, T-A. Cowles, J-R. Cupal, J-

J. Wallace, A-W., A purely data structure foraccurate high level timing simulation of

synchronous designs, Verilog HDL Conference,pg 101-107, 1994.

[13] Hebert, O. Kraljic, I-C. Savaria, Y., A Method toDerive Application-Specific Embedded

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