heat (hardware enabled algorithmic tester) for … 9, 2016 1 heat (hardware enabled algorithmic...
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May 9, 2016 1
HEAT (Hardware enabled Algorithmic tester)
for 2.5D HBM Solution
May 9, 2016
Kunal Varshney, Open-Silicon Ganesh Venkatkrishnan, Open-Silicon Pankaj Prajapati, Open-Silicon
May 9, 2016 2
Agenda
• High Bandwidth Memory (HBM) Basics
• Chip Introduction & Motivation
• Challenges
• HEAT Features
• Conclusion
May 9, 2016 3
Understanding HBM • JEDEC standard
• DRAM embedded in ASIC Package (Stacked Memory Dies)
• Backed by AMD, SK-Hynix, Samsung, nVidia
• 2.5D Interposer based ASIC implementation
• Initial adoption expected in GPU & HPC markets, now followed by Networking
• HBM Gen2 JEDEC specifications:
– 8 Gb per DRAM die
– 2 Gbps/pin (DDR)
– 4/8 High stack for 4GB/8GB density
– 256 GB/s total bandwidth
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Understanding HBM
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From Memory Vendor
Developed at Open-Silicon
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Chip Introduction & Motivation
• HBM Test Chip
• Technology node : 16nm FF from TSMC
• 2.5D Interposer technology
• HBM Memory : SK-Hynix
• Key Motivation: On-chip Silicon Validation of in-house HBM capabilities • HBM Protocol Controller
• HBM PHY
• D2D IOs
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Chip Block Diagram
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hbm_top.vHBM PHY
HBM Controller IO
PADS
PLL
HEAT
TapController
TAPSEL_ENJtag_2_csr(C)
Reset De-assertion
Reset De-assertion
HBM D2D Channel 0
HBM D2D Channel 1
IEEE 1500
clk_reset_ctrl.v
Clk_CNTRL/ DEBUG
PLL
Clock/Reset Signals
Reset Chatter
ControllerCSR i/f
UIF 0
UIF 1
UIF 2
UIF 3
Jtag_2_uif
AUTO
BISTAUTO
BISTAUTO
BISTAUTO
BIST
Padring.v
GPIO
Logic Die
HBM reset to memory
Soc reset
HBM_clk
HBM Memory DIE
Package
JTAG 5
5
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7
DA
60
DFT Speed Test Module/ IO
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Challenges • At speed Functional Testing (1Ghz)
– At speed Traffic Generation ( mimicking system traffic)
– Single cycle data integrity check
• Performance Measurement
• Power aware Design
• Minimal Package IO Count
• Fall-back chip booting options
• Functional Debug
• User Interface Debug
• Testing Logic die before Assembly
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HEAT Architecture
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Functional Testing • Traffic generation
– Galois LFSRs used
– Modes of operation: • BW: WWWW…..
• BR: RRRRR…...
• RAW: WRWRWR….
WWRRWWRR….
– Control on DATA/ADDR • Constant, INC/DEC by N, Random, W0, W1, CB
• Scenarios: Memory sweep, Bank Switching, Max Latency, Max BW etc.
• Data Integrity – Wr_data stored in 16 deep CAM. ID used as addr of CAM
– Single cycle data comparator when rd response is received.
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Challenges • At speed Functional Testing (1Ghz)
– At speed Traffic Generation ( mimicking system traffic)
– Single cycle data integrity check
• Performance Measurement
• Power aware Design
• Minimal Package IO Count
• Fall-back chip booting options
• Functional Debug
• User Interface Debug
• Testing Logic die before Assembly
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Performance Measurement • Latency:
– Min latency with transaction details
– Max latency with transaction details
– Avg Latency
• Bandwidth:
– Total number of clks taken by a sequence.
• Configurable Timeout Value and Timeout status.
• Byte wise Granularity in LFSR to reduce Power consumption
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May 9, 2016 12
Challenges • At speed Functional Testing (1Ghz)
– At speed Traffic Generation ( mimicking system traffic)
– Single cycle data integrity check
• Performance Measurement
• Power aware Design
• Minimal Package IO Count
• Fall-back chip booting options
• Functional Debug
• User Interface Debug
• Testing Logic die before Assembly
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Package IO Count
• Test Chip : Limited Package IO availability
• JTAG Selected as i/f for Programming the HEAT
• Functional JTAG and DFT JTAG Muxed
• Functional IO Muxing. – Same IO used as i/p during chip reset and o/p after chip reset
– Inputs from board used for fall-back chip booting options.
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May 9, 2016 14
Challenges • At speed Functional Testing (1Ghz)
– At speed Traffic Generation ( mimicking system traffic)
– Single cycle data integrity check
• Performance Measurement
• Power aware Design
• Minimal Package IO Count
• Fall-back chip booting options
• Functional Debug
• User Interface Debug
• Testing Logic die before Assembly
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Functional Debug • Number of UIF read/write errors received
• Number of Data Mismatch errors with Expected data and actual data received on UIF
• Info of first failed transaction
• Directed Mode – Single or upto 4 transactions (read or write)
– User can create it’s own transaction
• Bitwise Data masking to pin-point single bit errors in data stream
• Option of stop/continue on error.
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May 9, 2016 16
Challenges • At speed Functional Testing (1Ghz)
– At speed Traffic Generation ( mimicking system traffic)
– Single cycle data integrity check
• Performance Measurement
• Power aware Design
• Minimal Package IO Count
• Fall-back chip booting options
• Functional Debug
• User Interface Debug
• Testing Logic die before Assembly
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User Interface Debug
• Bus Monitor design – Monitors HEAT engine output and UIF Bus
– Helpful in Debugging on-chip failures
• Multiple mode of operations – Bus Capture
– Transaction recorder
– Error recorder
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Challenges • At speed Functional Testing (1Ghz)
– At speed Traffic Generation ( mimicking system traffic)
– Single cycle data integrity check
• Performance Measurement
• Power aware Design
• Minimal Package IO Count
• Fall-back chip booting options
• Functional Debug
• User Interface Debug
• Testing Logic die before Assembly
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Testing Logic Die before Assembly
• Loopback Handles for testing without memory – Point of Loopback :
» Core Side Loopback (before D2D IO)
» IO loopback (Loopback using D2D IO)
– Loopback Transaction generation:
» UIF level Loopback
» DFI-i (input of PHY) level Address loopback
» DFI-i (input of PHY) level Data loopback
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Conclusion • At speed Functional Testing (1Ghz)
– At speed Traffic Generation ( mimicking system traffic)
– Single cycle data integrity check
• Performance Measurement
• Power aware Design
• Minimal Package IO Count
• Fall-back chip booting options
• Functional Debug
• User Interface Debug
• Testing Logic die before Assembly
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