herschel pacs - ibdr signal processing unit - spu - hw unit, start-up sw and low-level sw drivers

Herschel PACS SPU - IAC 1

PACS IBDR 27/28 Feb 2002

Herschel PACS - IBDR

SIGNAL PROCESSING UNIT- SPU -

HW Unit, Start-up SW and Low-level SW Drivers

José M. HerrerosINSTITUTO DE ASTROFÍSICA DE

CANARIAS- IAC -



CONTENTS

1. Electrical Design Evolution 2. Budgets.3. Box Outlines and Block Diagrams.4. Software5. Model Philosophy.6. CRISA Status Report.7. Critical / Problem Areas.8. Schedule.



ELECTRICAL DESIGN EVOLUTION

• CPU BOARD:

– Program and Data Memory sizes increase due to:• PACS data reduction/compression requirements• UTMC memories instead of WhiteElectronics

– PSC ASIC Design consolidation (TEMIC manufacturer)

• DC/DC CONVERTER:

– Removal of external synchronization



New MEMORY ORGANIZATIONFeature LFI-REBA

DPU LFI-REBA

SPU PACS-SPU SWL-LWL

Program ROM Size 32 KW x 48 32 KW x 48 32 KW x 48 Program RAM Size 128 KW x 48

512 KW x 48 128 KW x 48 512 KW x 48

256 KW x 48 512 KW x 48

EEPROM Size 256 KW x 48 Not implemented 256 KW x 48 Data RAM Size 128 KW x 32

512 KW x 32 128 KW x 32 512 KW x 32

128 KW x 32 512 KW x 32

Expansion Data RAM Size Not implemented 512 KW x 32 512 KW x 32 Interface to MIL BUS Included in Auxiliary Board Not implemented Not implemented OBT timer PMPSC PMPSC (Not used) PMPSC (Not used)

DMPSC (Not used) Watchdog timer DMPSC DMPSC Not implemented Interface to DAU - End of Acquisition Interrupt

- Internal analog acquisitions - 1Hz Interrupt - OBT Clock Sync status - 1Hz signal control

Not implemented Not implemented

Interface to DAE - DAE Power Status input - DAE reset SMCS1 output - DAE reset SMCS2 output

- DAE Data ready Interrupt

Not implemented

Interface to SPU - Reset to SPU - Reset from SPU Not implemented



SPU UNIT BUDGETS

IIDR

(01-03-01) IBDR

(27-02-02)

DIMENSIONS (mm) (LENGTH X DEPTH X HEIGHT) (WITHOUT AND WITH FEET)

242 X 183 X 102 242 X 213 X 102

238 X 205 X 97 270 X 215 X 97

POWER (W)

20

(20% CONTINGENCY INCLUDED)

30,29 (AVERAGE)

35,04 (PEAK)

MASS (KG)

5,546


3,757




PACS SPU BOX OUTLINE

LFI-REBA

PACS-SPU



SPU FUNCTIONAL BLOCK DIAGRAMThe CPU board is designed to include as maximum: One DSP working at 18 MHz One 32 KW x 48 Boot PROM bank Three EDAC protected SRAM memory banks:

512 KW x 48 for Program RAM 512 KW x 32 for Data RAM 512 KW x 32 for expansion of Data RAM

One EDAC protected up to 256 KW x 48 EEPROM memory bank.

Three IEEE1355 DS links including one common 8KWx32 Dual Port RAM buffer

Two PSC ASICs including: Watchdog, OBT and 32 bit GP Timers. EDAC logic and Interrupt management. Programmable Address decoding and Wait

State generator. One Auxiliary Board Interface, including:

One redundant interface to the MIL-STD-1553 bus including one 8KWx16 Dual Port RAM buffer.

One Mother Board Interface

Each CPU board executes its own specific Start Up and Application Software.

DC/DCCONVERTER S/C PRIMARY PWR

ANALOG HKDATA

PSU

DAU

SPU

IEEE1355

IEEE1355

DSP21020

MEM

SPU_SWL_LVDS_2

SPU_SWL_LVDS_3 IEEE1355

SPU_SWL JTAG

SPU-SWL

SPU_SWL_LVDS_1

IEEE1355

IEEE1355

DSP21020

MEM

SPU_LWL_LVDS_2

SPU_LWL_LVDS_3 IEEE1355

SPU_LWL JTAG

SPU-LWL

SPU_LWL_LVDS_1

INTERNACQ



CPU BLOCK DIAGRAM



DC/DC CHARACTERISTICS

• Input Voltage Operation from 26 to 32 Volts• Use of a SMART Converter

(Buck / Push-Pull with conductance Control)• Buck Switching Frequency Operating around 130kHz• Outputs Voltages as follow :

– +5 Volts – +/- 15 Volts



DC/DC BLOCK DIAGRAM

GND

GND

GND

GND

GND

F006 : OUTPUT STAGEF005 : BUCK STAGE F006 : PUSH-PULL STAGE

F003 : APS

F002 : PROTECTION & RESETOver-Voltage ProtectionUnder-Voltage Protection

F004 : CONTROL STAGEBuck Conductance Control

Push-Pull Control

F001 : INPUT FILTERCommon & Differential Mode



DAUBLOCK

DIAGRAM

INTE

RNAL

CON

NECT

OR

TH_PSUa

TH_PSUb

DGNDVCC

TH_SPU_SWLa

DAU BLOCK DIAGRAMHERSCHEL-PACS-SPU

VCC CURRENTCONDITIONING CIRCUIT

CURR

ENT

SENS

ING

VCC

DGND

VCC VOLTAGECONDITIONING CIRCUIT

TH_SPU_SWLbTH_SPU_LWLaTH_SPU_LWLb

ANALOG TELEMETRY CONDITIONING

EXTE

RNAL

CON

NECT

OR

THERMISTOR

VCC_CUR_HK_P

VCC_CUR_HK_N

VCC_VOLT_HK

+15V

AGND

+15V VOLTAGECONDITIONING CIRCUIT

15VP_VOLT_HK

+15V CURRENTCONDITIONING CIRCUIT

CURR

ENT

SENS

ING

15VP_CUR_HK_P

15VP_CUR_HK_N

AGND

+15V_AUX+15V



ASICBLOCK

DIAGRAM



START-UP SW AND LOW-LEVEL SW DRIVERS

• Both SWL-SPU and LWL-SPU contain their own separate but identical PROM SW activated simultaneously during the switch-on of the SPU or under a SW reset.

• The Start-Up SW will perform the necessary functions to boot the unit at power up, perform a health self-test and start the Application SW giving it the control.

• The Low-Level SW drivers is a set of primitives (source/object code) to be compiled/linked with the different application software package.

DPU_ASWSPU_SUSW

Responses

Commands

CONTEXT DIAGRAM



PACS SPUSTART-UP SWARCHITECTUR

E

SPU Start up SW

Power up init

Reset source discrimination

Hardware tests

Configuration for command loopexecution

Command loop

Control transfer to APSW

Hardware Reset

Application SW

Warm Reset

LLSW_DRV

Uses



SPU MODEL PHILOSOPHY

MODEL LFI-REBA -NUMBER-

PACS-SPU -NUMBER- NOTES

ENGINEERING MODEL (EM) 1 1 COMMERCIAL COMPONENTES

AVIONICS MODEL (AVM) 1 1 COMMERCIAL COMPONENTES

QUALIFICATION MODEL (QM) 1 0 MILITARY COMPONENTS

FLIGHT MODEL (PFM) 2 2 HI-REL COMPONENTS

FLIGHT SPARE (FS) (x) (x) HI-REL COMPONENTS

Note (x): Only one board for each type.



MODEL BUILT STANDARD

EM

NON REDUNDANT UNIT (SINGLE BOX) ELECTRICAL AND FUNCTIONAL REPRESENTATIVE OF THE FLIGHT MODEL NON REPRESENTATIVE IN FIT AND FORM OF THE FLIGHT MODEL COMMERCIAL HYBRID DC/DC CONVERTER PROCESSOR SUPPORT CHIP (PSC) IN FPGA COMMERCIAL GRADE COMPONENTS SOFTWARE FLIGHT STANDARD (VERSION 1) NON DELIVERABLE MODEL

AVM

NON REDUNDANT UNIT (SINGLE BOX) ELECTRICAL AND FUNCTIONAL REPRESENTATIVE OF THE FLIGHT MODEL NON REPRESENTATIVE IN FIT AND FORM OF THE FLIGHT MODEL FLIGHT DC/DC CONVERTER DESIGN PROCESSOR SUPPORT CHIP (PSC) IN FPGA COMMERCIAL GRADE COMPONENTS SOFTWARE FLIGHT STANDARD (VERSION 1) EMC CONDUCTIVE EMISSIONS TEST TO SUPPORT INSTRUMENT AND SYSTEM LEVEL TEST

FM

FULL REDUNDANT (TWO IDENTICAL BOXES) FULL FLIGHT STANDARD PROCESSOR SUPPORT CHIP (PSC) IN ASIC HI-REL GRADE COMPONENTS UNITS (NOM + RED) TO BE SUBMITTED TO ACCEPTANCE LEVEL TESTS

VIBRATION, THERMAL/VAC AND EMC



CRISA STATUS REPORT (1/4)

1. Contract / Commercial / Management• Phase 1 - conditioned final milestone - achieved on W51• Phase 2 - 2nd progress Milestone - took place on W51.• Phase 3 ITT not set.2. HW & System Engineering• System engineering activity: Production of revised

system documents for the system BDR (HW/SW ICD).• Design engineering activity: DC/DC Electrical design

consolidated. PCB design finished.3. SW Engineering• Integration under way. Little adaptations being

implemented in parallel with the tests.




4. ASIC Development• ASIC tests and integration fully completed in

representative FPGA. Now working in the ‘coberture’ (failure simulations) as part of the industrial file for procurement. This activity resulting more complex than expected will be finished beginning W10. The complete dossier is expected to be ready by end March 2002.

5. Physical & Verification Engineering• None.6. Unit Tester Engineering• Unit tester HW & SW (1st) in work area.• Complementary ‘test set’ ready in work area.




7. Procurement & Parts Engineering• DC/DC CV PCB for AvMs ordered week #8.• Last steps of the Procurement for AvM going on

compatible with schedule. No critical conflict still envisaged.

• Changes to DCL (coming from DC/DC design) to be reported on February 22nd 2002 to TLG and IAC.

8. MAI Activities• New CPUs set under MAI, about 60% achieved. No

conflict envisaged up to now in plant to fulfil delivery dates. Two boards already waiting to be tested.

• 1st DAU and AUX ready for tests.




9. Tests activities• 1st CPU under HW Characterisation. Timing problems detected

outside the CPU, concretely within the NAIS test board (an auxiliary I/F board with the logic analyser used in test). Once confirmed this fact, tests have been normally resumed. They are satisfactorily running at good rhythm by now.

• SW (version 1) integration under way. Last steps performed consisting on the successful initiation of the 1355 / SCMS tests.

10. EMs / AvMs Delivery Schedule - no margin included -• EM SPU ready for delivery: 15/03/02• EM REBA ready for delivery: 04/04/02 • AvM SPU ready for delivery: 16/04/02 • AvM SPU ready for delivery: 04/04/02



CRITICAL / PROBLEM AREAS

• Financing for PACS-SPU and LFI-REBA Qualification stage:Confirmed un-officially.

• Funds expected for end of December not received.Negotiations in progress.

• ITT for Phase III: Qualification and QM Not started pending of receiving funds.

• Request for financing Phase IV: Flight ModelsTo be made before 15 of March.

herschel pacs - ibdr signal processing unit - spu - hw unit, start-up sw and low-level sw drivers

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