heterogeneous noc router -...

Heterogeneous NoC Router

Final Presentation

06.03.2012

Moti Mor

Tomer Gal

Instructor: Yaniv Ben Itzhak

Background – Bus On Chip

• Busses are commonly used on SoC as the main

communication protocol

• Slow transfer rates

• High power consumption

• Only 2 units communicate simultaneously

Conventional Bus on Chip

C C C C C C C

C = Client

BUS

Background – Homogeneous NoC

• The SoC units communicate through a

network of routers

• Each router is assigned for a single unit

• Supports many simultaneously connections

• Cons:

– Loaded router may still have bottle-necks

– Resources are not assigned to the highly loaded

areas

Background – XY mesh NoC

C C C

C C C

C C C

R R R

R R R

R R R

C = Client

R = Router

Project Definition & Goals

• Learning the NoC basics and particularly the

Heterogeneous NoC router

• Design the architecture and implementation of:

– A single Heterogeneous Router

– A network of Heterogeneous Routers

• Measurements of the Heterogeneous NoC

– Latency

– Throughput

Project Development Stages

• NoC & Het NoC concept learning

• Architecture and Logic Design

• HDL Implementation

– Building a NoC & Source/Sink (With VHDL

Implementation)

• Functional Simulation

– Measurements

1 VC

1 VC

1 VC 1 VC

3 VCs

3 VCs 3 VCs

3 VCs

1 VC

1 VC

1 VC3VCs

1 VC

1 VC

1 VC 3VCs

(a) Base-line: Uniform

capacity and number of

VCs approach.

(b) Non-uniform link

capacities approach

].12) [Redundant VCs(

(c) Non-uniform number of

Redundant VC approach (

].15, 13) [capacity

: Our approach(d)

Non-uniform link capacities

and number of VCs.

Possible Solutions

Architectural Design of the selected Solution

• Parametric controlled XY-Based

Heterogeneous NoC routers

• Attributes controlled by the parameter:

– Number of virtual channels per port

– Port bandwidth

– Buffer size (Capacity robustness)

Router VC AllocatorR O P CG

R O P CG

R O P CG

R O P CG

R O P CG

Packet

Decoder

In - ports

Out- ports

Switch

Allocator

Switch

Traversing

H

Decodes the flit and stores in the desired buffer

Determines the requested output port

Determines the virtual channel in the next router

Allocates a route from the input port to the output

port

Sends the flit across the allocated route

Special Problems:Problem 1

• Packet representation in HDL:

– HDL language is based on signals and physical

components - difficult to represent an abstract

structure like a ‘Packet’

– Makes data tracking in simulation more difficult

– No robustness - Protocol changes, packet size,

fields, bandwidth

Special Problems:

Problem 1

Solution:

• The use of ‘Records’ (Data structures)

– Implementing the in/out ports as ‘record’ type

– Enables protocol robustness in packet size, fields,

bandwidth

– Enables packet & flit tracking throughout the

simulation

– Enables simple adding/removing debug fields

Packet

Head Flit

Destination

X Y

Flit ID VCDebug

Fields

Source IDPacket

S/NNo. Of

Flits

Body Flit 1..N

Data Flit ID VCDebug

Fields

Source IDPacket

S/NNo. Of

Flits

Tail Flit

Data Flit ID VCDebug

Fields

Source IDPacket

S/NNo. Of

Flits

Solution Implementation

Switch allocation tasks:

• Allocate all inputs to all outputs

• Prevent conflicts

• fairness


2 dimensional ripple carry arbiter

Problems:

• Feedback is not synthesizable!


2 dimensional ripple carry arbiter

Solution:

• Diagonal wave-front

• round-robin priority rotation

scheme – prevents feedback


Diagonal propagation arbiter

Project Summary

• NoC concept learned:

– Computer network basics

– Router basics

– Homogeneous NoC

– Article reading about Q.NoC

• Design of Heterogeneous NoC Router Architecture

• HDL implementation

– Client implementation (source and sink)

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