1

High gain FEC and CDR Locking

For 25G NRZ

Public

Vincent Houtsma & Dora van Veen

Optical Access Research, Bell- Labs -Murray Hill, NJ

May, 2017

2

High gain FEC is proposed for improved power budget(effenberger_3ca_1_1116, houtsma_3ca_1_0916, laubach_3ca_01_0117)

Question can CDR lock to signal and recover data at BER= 10-2 ?

Input BERs before FEC of 10-2 are considered

To do this we used offline data for different received powers and calculated the FEC input BER offline without need for CDR to lock

How do we know we have recovered data with BER= 10-2 to investigate CDR locking ? (since CDR needs to lock to recover the data)

3

Measured 25G BER curve (with offline data recovery) :10

-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12

Bit E

rro

r R

ate

[-

]

-32 -30 -28 -26 -24 -22 -20

Received Optical Power [dBm]

Measured 25G NRZ

Offfline BER (no CDR)

We used this data to investigate clock recovery for different received optical power (and hence different BERs)

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How does CDR lock ?

The receiver generates a clock from an approximate frequency reference, and then phase-aligns the clock to the transitions in the data stream with a phase-locked loop (PLL).

data in

ref clk in

recovered

clk out

freq adjust

5

Real time measurement using CDR of storage scope at BER~10-4

CDR loop bandwidth =15.2 MHz and damping factor=0.707 (2nd order PLL)

6

At BER~10-3

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At BER~10-2

Recovered clock starts to deviate from 25G transmitter clock (loss of lock?)

8

We assume our data is SNR limited at high BER

To ensure CDR sees transitions for locking we implemented an ‘ideal’ limiting amplifier to clip the signals, so CDR is not SNR limited

This means we can’t use any equalization (like FFEs) to improve signal quality before the clock and data is recovered

Measured Eye Clipped Eye using LA0 1 2 3 4 5 6 7

x 10-11

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

In-phase Signal

Time (s)

Am

plit

ude (

AU

)

0 1 2 3 4 5 6 7

x 10-11

-1

-0.5

0

0.5

1In-phase Signal

Time (s)

Am

plit

ude (

AU

)

Investigate clock recovery for different optical powers with offline data :

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CDR locking will depend on how much the recovered clock will deviate from ‘ideal’ 25G clock as function of time

We investigated offline recovered clock with ‘ideal’ 25G clock to investigate if CDR will be able to lock at high BER

For SNR limited signals the voltage noise will translate into increase of recovered clock jitter which will make it more difficult to recover the ‘ideal’ 25G clock.

Recovered clock jitter is the deviation of the recovered clock from its ideal location in time. Or simply how early or late a transition is with reference to when it should transition.

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Voltage Noise and Recovered clock jitter :

-1-0

.50

0.5

10

2000

4000

6000

8000

10000

12000 BER=10-3BER=10-12 -1

-0.5

00.5

10

2000

4000

6000

8000

10000

12000

For high BERs voltage noise will cause increase in jitter due to the fact that bit probability distributions start to overlap

This simply relates to the bit error probability and thus BER

Bit errors at high BERs are caused by voltage noise. If momentary noise voltage exceeds the noise margin, a wrong value can be sampled even if the sampling takes place at the correct moment in time.

0 1 2 3 4 5 6 7

x 10-11

-1

-0.5

0

0.5

1In-phase Signal

Time (s)

Am

plit

ude (

AU

)

0 1 2 3 4 5 6 7

x 10-11

-1

-0.5

0

0.5

1In-phase Signal

Time (s)

Am

plit

ude (

AU

)

11

0 1 2 3 4 5 6 7

x 10-11

-1

-0.5

0

0.5

1In-phase Signal

Time (s)

Am

plit

ude (

AU

)

Plots BER with jitter for good quality eye by changing sampling point

Jitter

Decision window

=CDR retiming zone

This is different from bathtub curve jitter measurementB

ER

10-8

10-12

-0.5 UI 0 0.5 UI

proper lock

false lock

JitterJitter

Ideal sampling

time

Middle of eye

0.5

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Bathtub measurement at 25G NRZ with 25G APD

1 UI= 40 ps

For 25G :

Tj (10-12) = 33.16 ps

sampling margin < 7 ps

Tj (10-3) = 14.6 ps

sampling margin ~25 ps

(0.63 UI)

(for 10G: 67 ps, same Tj)

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0 1 2 3 4 5 6 7

x 10-11

-1

-0.5

0

0.5

1In-phase Signal

Time (s)

Am

plit

ude (

AU

)

Jitter for BER=10-12

Jitter (time domain)

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Eye diagram

Jitter distributionJitter

Tb

itMiddle of eye

0 0.2 0.4 0.6 0.8 1

x 10-9

0

0.2

0.4

0.6

0.8

1

14

Condition : BER=10-3

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Condition : BER=10-2

0 1 2 3 4 5 6 7

x 10-11

-1

-0.5

0

0.5

1In-phase Signal

Time (s)

Am

plit

ude (

AU

)

0 0.2 0.4 0.6 0.8 1

x 10-9

0

0.2

0.4

0.6

0.8

1

0 1 2 3 4 5 6 7

x 10-11

-1.5

-1

-0.5

0

0.5

1

1.5In-phase Signal

Time (s)

Am

plit

ude (

AU

)

0 0.2 0.4 0.6 0.8 1

x 10-9

0

0.2

0.4

0.6

0.8

1

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Clock recovery at BER=10-12

Data and recovered clock 25G(black) and recovered clock(red)

0 0.2 0.4 0.6 0.8 1

x 10-9

-1

-0.5

0

0.5

1

0 0.2 0.4 0.6 0.8 1

x 10-9

-1

-0.5

0

0.5

1

16

BER=10-3

BER=10-2

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10-9

-1

-0.5

0

0.5

1

0 0.2 0.4 0.6 0.8 1

x 10-9

-1

-0.5

0

0.5

1

0 0.2 0.4 0.6 0.8 1

x 10-9

-1

-0.5

0

0.5

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10-9

-1

-0.5

0

0.5

1

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Frequency of recovered clock at different received powers (BERs)

BER=10-12 BER=10-3 BER=10-2

For BER =10-2 recovered clock frequency is very dispersive

making it hard for CDR to acquire lock

12.4 12.45 12.5 12.55 12.60

0.2

0.4

0.6

0.8

1Amplitude Spectrum

Frequency (GHz)|Y

(f)|

12.4 12.45 12.5 12.55 12.60

0.2

0.4

0.6

0.8

1Amplitude Spectrum

Frequency (GHz)

|Y(f

)|

12 12.5 130

0.2

0.4

0.6

0.8

1Amplitude Spectrum

Frequency (GHz)

|Y(f

)|

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Up to BER= 10-4 recovered clock is ‘very’ similar to 25G clock, so proper locking of CDR is likely possible

For BER> 10-2 recovered clock starts to deviate significantly from 25G clock and proper CDR locking might not be guaranteed anymore

Conclusions :

For BER= 10-3 recovered clock starts to deviate from 25G clock, however CDR locking might still be possible

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Up till now no other 25G standards proposes FECs with BERin of 10-2

Conclusions :

Physical layer

Linerate Standard FEC BERin

100GEBackplane

25G IEEE 802.3bjRS(528,514)RS(544,514)

3.92E-053.09E-04

100GE Fiber

25G IEEE 802.3bmRS(528,514)RS(544,514)

3.92E-053.09E-04

10GE PON 10G 802.3av RS(255,223) 1.1E-03

Table of other standards with FECs

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The abilities of a CDR circuit to deal with noisy signals will be primarily determined by the characteristics of its PLL

Recommendations :

Also locking at 25G is more difficult than at 10G, so increasing loop bandwidth of PLL (~10 MHZ) would be benifitial (10G CDRs ~ 4 MHz)

Wider bandwidth PLL is needed for noisy signals which will do better job of tracking the data as the recovered clock data will more accurately match each individual bit.

CDR locking at 25G for high BER needs more study especially in BM !

Unfortunately wider BW PLL leads to degraded output BER of CDR (due to reduced output SNR and higher output phase noise).