high-level synthesis : an efficient solution to design hardware accelerators in soc

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Workshop - November 2011 - Toulouse Université de Bretagne-Sud Lab-STICC Philippe COUSSY, Dominique HELLER

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High-Level Synthesis : An efficient solution to design hardware accelerators in SoC. Université de Bretagne-Sud Lab-STICC Philippe COUSSY, Dominique HELLER. HLS in the flow. Starting from a functional description, automatically generate an RTL architecture. #define N 2 - PowerPoint PPT Presentation

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Page 1: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

Workshop - November 2011 - Toulouse

Université de Bretagne-SudLab-STICC

Philippe COUSSY, Dominique HELLER

Page 2: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

HLS in the flowStarting from a functional description, automatically

generate an RTL architecture

RTL

Logic synthesis

Gate level netlist

Layout

GDSII

Algorithm#define N 2

typedef int matrix[N][N];

int main(const matrix A, matrix C){

const matrice B ={{1, 2},{ 3, 4}}; int tmp; int i,j,k; for (i=0;i<N;i++) for (j=0;j<N;j++){ tmp = A[i][0]*B[0][j]; for (k=1;k<N - 1;k++) tmp = tmp + A[i][k] * B[k][j];

C[i][j] = tmp + A[i][N-1] * B[N-1][j]; }

return 0;}

High-Level synthesis

SystemC simulation models (CABA/TLM)

Virtual prototyping

Page 3: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

GAUTAn academic, free and open source HLS tool Dedicated to DSP applications

Data-dominated algorithm 1D, 2D Filters Transforms (Fourrier, Hadamar, DCT…) Channel Coding, source coding algorithms

Input : bit-accurate C/C++ algorithmbit-accurate integer and fixed-point from Mentor

Graphics

Page 4: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

GAUTOutput : RTL Architecture

VHDL SystemC

CABA: Cycle accurate and Bit accurate TLM: Transaction level model Compatible with both SocLib and MPARM virtual

prototyping platforms

Automated Test-bench generationAutomated operators characterization

Page 5: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

GAUT: Constraints

GALS/LISinterface Data

Path

Controller

Clock enable

Bus

co

ntro

ller

Data(i)Req(i)

Ack(i)

GAUT

Internalbuses

Bit accurate Algorithm in bit-accurate C/C++

Specificlinks &

protocols

MemoryUnit

Synthesis constraints - Initiation Interval (Data average throughput ) - Clock frequency - FPGA/ASIC target technology - Memory architecture and mapping - I/O Timing diagram (scheduling + ports) - GALS/LIS Interface (FIFO protocol)

Page 6: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

Integration of HW accelerator

CPU IP

RAM

Bus

on the Bus

CPU IP

RAM

Bus

on the CPU

Page 7: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

Sobel filtering: Hardware prototyping Image processing

Sobel : 4 parallel I/O ports, 166- cycle latency (tile 25x25), Freq. 66,6 Mhz

Compared to a pure SW implementation 6x speed-up for the complete

application

Microblaze (125 Mhz, 8 ko cache)Plb bus

Tft Controller

Memory Controller

FSL

DDR OffChip

Plb bus

SysAce

Local Memory

Sobel66.6 Mhz

SoC design on a FPGA Xilinx Virtex 5 LX110 (XUPV5) board

Page 8: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

MJPEG: Hardware prototypingReal time decoding: 24 QCIF images/sec

IDCT: 4 parallel I/O ports, 168-cycle Latency, Freq. 70 Mhz

YUV2RGB: 14-cycle latency, Freq. 225 Mhz

Compared to a pure SW implementation 10x speed-up for the IDCT function 5x speed-up for the yuv2rgb function

SoC design on a FPGA Xilinx Virtex 5 LX110 (XUPV5) board

Page 9: High-Level Synthesis : An efficient solution to design hardware accelerators in SoC

Workshop - November 2011 - Toulouse

Université de Bretagne-SudLab-STICC

Philippe COUSSY, Dominique HELLER

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