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HIGH - LEVEL SYNTHESIS Introduction to
Chip and System Design
HIGH - LEVEL SYNTHESIS Introduction to
Chip and System Design
by'
Daniel D. Gajski Nikil D. Dutt
AllenC-HWu University of CalifomialIrvine
Steve Y -L Lin Tsing Hua University
l1li....
" Springer Science+Business Media, LLC
Library of Congress Cataloging-in-Publication Data
High-Ievel synthesis : introduction to chip and system design / by Daniel D. Gajski ... [et al.].
p. cm Includes bibliographical references and index. ISBN 978-1-4613-6617-1 ISBN 978-1-4615-3636-9 (eBook) DOI 10.1007/978-1-4615-3636-9 1. Integrated circuits -- Very large scale integration -- Design and
construction -- Data processing. 2. Computer-aided design. 3. Silicon compilers. 1. Gajski, Daniel D. TK7874.H5242 1992 621.39'5 -- dc20 91-41308
CIP
Copyright © 1992 by Springer Science+Business Media New York OriginaIly published by Kluwer Academic Publishers in 1992 Softcover reprint ofthe hardcover Ist edition 1992
AII rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+ Business Media. LLC.
Printed on acid-free paper.
Contents
Preface xi
Acknowledgements xv
1 Introduction 1
1.1 The Need for Design Automation on Higher Abstraction Levels 1
1.2 Levels of Abstraction . 3
1.3 Definition of Synthesis 8
1.4 Languages, Designs and Technologies . 9
1.5 Essential Issues in Synthesis . . 13
1.5.1 High-level Formulation. 13
1.5.2 Languages and Representations 15
1.5.3 Design Modeling ..... 16
1.5.4 Design Quality-Measures 17
1.5.5 High-Level Synthesis Algorithms 17
1.5.6 Component Sets and Technology Mapping . 18
1.5.7 Databases and Environments ... 19
1.6 Status and Future of High-Level Synthesis 21
1.7 Summary 24
1.8 Exercises 24
2 Architectural Models in Synthesis 27
vi HIGH-LEVEL SYNTHESIS
2.1 Design Styles and Target Architectures.
2.2 Combinatorial Logic
2.3 Finite State Machines
2.3.1 Autonomous FSMs .
2.3.2 State-Based and Transition-Based FSM
2.4 Finite State Machine with a Datapath
2.5 System Architecture ....
2.6 Engineering Considerations
2.6.1 Clocking.
2.6.2
2.6.3
Busing ..
Pipelining .
2.7 Summary and Future Directions
2.8 Exercises
3 Quality Measures
3.1 Introduction ..
27
30
34
35
38
41
47
51
51
54
56
57
59
63
63
3.2 The Relationship between Structural and Physical Designs. 64
3.3 Area Measures 66
3.3.1 Datapath
3.3.2 Control Unit
3.4 Performance Measures
3.4.1 Electrical Models
3.4.2 The Delay of Combinational Circuits.
3.4.3 The Delay of Storage Elements
3.4.4 System Clock Cycle
3.5 Other Measures ...... .
3.6 Summary and Future Directions
3.7 Exercises
4 Design Description Languages
67
71
77
78
79
80
83
88
89
91
93
CONTENTS
4.1 Introduction to HDLs .......... .
4.2 Language Models vs. Architectural Styles
4.3 Programming Language Features for HDLs
4.3.1 Data Types ............. .
4.3.2 Operators and Assignment Statements
4.3.3 Control Constructs .
4.3.4 Execution Ordering
4.4 Hardware-Specific HDL Features
4.4.1 Interface Declarations
4.4.2 Structural Declarations
4.4.3 RT and Logic Operators
4.4.4 Asynchrony
4.4.5 Hierarchy
4.4.6 Interprocess Communication
4.4.7 Constraints..........
4.4.8 User Allocation and Bindings
4.5 HDL Formats .....
4.5.1 Textual HDLs .
4.5.2
4.5.3
Graphical HDLs
Tabular HDLs
4.5.4 Waveform-Based HDLs
4.6 A Discussion of Some HDLs ..
4.6.1
4.6.2
4.6.3
4.6.4
Instruction Set Processor Languages
Programming-language-Based HDLs .
HDLs for Digital Signal Processing
Simulation-Based HDLs ..... .
4.7 Matching Languages to Target Architectures
4.8 Modeling Guidelines for HDLs
4.8.1 Combinatorial Designs
4.8.2 Functional Designs . .
vii
93
96
97
98
98
98
99
100
101
101
101
102
103
105
107
108
109
110
111
111
112
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117
119
125
127
128
viii
4.8.3 Register-Transfer Designs
4.8.4 Behavioral Designs ....
4.9 Summary and Future Directions
4.10 Exercises
HIGH-LEVEL SYNTHESIS
129
131
132
133
5 Design Representation and Transformations 137
137
139
5.1 Introduction. . . . . . . . . . . . . .
5.2 Design Flow in High-Level Synthesis: An Example
5.3 HDL Compilation. . . . .....
5.4 Representation of HDL Behavior
· 144
· 147
5.4.1 Control-Flow Representation 148
5.4.2 Representation of Sequencing and Timing 150
5.4.3 Disjoint Control and Data-Flow Representations . 154
5.4.4 Hybrid Control and Data-Flow Representations. 154
5.4.5 Parse-Tree Representations 157
5.5 Representation of HLS Outputs .. 157
5.6 Design Views and Complete Representation Schemes for High-Level Synthesis . 158
5.7 Transformations .......... 164
5.7.1 Compiler Transformations.
5.7.2 Flow-Graph Transformations
5.7.3 Hardware-Specific Transformations.
5.8 Summary and Future Directions
5.9 Exercises
6 Partitioning
6.1 Introduction .
6.2 Basic Partitioning Methods
6.2.1 Problem Formulation
6.2.2 Random Selection
6.2.3 Cluster Growth ..
165
167
169
174
175
179
179
180
· 180
· 184
· 184
CONTENTS ix
6,2.4 Hierarchical Clustering, , , 185
6,2,5 The Min-Cut Partitioning 190
6,2,6 Simulated Annealing , , , 195
6,3 Partitioning in High-Level Synthesis 197
6,3,1 Unit Selection for Scheduling and Binding, 199
6,3,2 Chip Partitioning, , , , , ,204
6.4 Summary and Future Directions ,209
6,5 Exercises ............. , 210
7 Scheduling 213
7,1 Problem Definition ...... , 213
7,2 Basic Scheduling Algorithms ,214
7,2,1 Time-Constrained Scheduling , 220
7,2,2 Resource-Constrained Scheduling , 232
7,3 Scheduling with Relaxed Assumptions , 237
7,3,1 Functional Units with Varying Delays , 239
7,3,2 Multi-functional Units , , , , ,240
7,3,3 Realistic Design Descriptions , 241
7.4 Other Scheduling Formulations ,247
7.4,1 Simulated Annealing , , , 248
7.4,2 Path-Based Scheduling, · 248
7.4,3 DFG Restructuring. , , · 252
7,5 Summary and Future Directions , 254
7.6 Exercises ............. · 255
8 Allocation 259
8,1 Problem Definition .259
8,2 Datapath Architectures · 261 8.3 Allocation Tasks ... , 269
8.3,1 Unit Selection. ,269
x HIGH-LEVEL SYNTHESIS
8.3.2 Functional-Unit Binding. · 269
8.3.3 Storage Binding .... · 270
8.3.4 Interconnection Binding .270
8.3.5 Interdependence and Ordering .270
8.4 Greedy Constructive Approaches · 272
8.5 Decomposition Approaches .277
8.5.1 Clique Partitioning . .277
8.5.2 Left-Edge Algorithm. · 283
8.5.3 Weighted Bipartite-Matching Algorithm · 286
8.6 Iterative Refinement Approach · 290
8.7 Summary and Future Directions · 292
8.8 Exercises ............. · 294
9 Design Methodology for High-Level Synthesis 297
9.1 Basic Concepts in Design Methodology. · 297
9.2 Generic Synthesis System · 305
9.3 System Synthesis · 308
9.4 Chip Synthesis · 311
9.5 Logic and Sequential Synthesis · 314
9.6 Physical-Design Methodology · 319
9.7 System Database . . . · 320
9.8 Component Database · 324
9.9 Conceptualization environment .326
9.10 Summary and Further Research . .332
9.11 Exercises ............. .334
Bibliography 337
Index 353
Preface
Rationale
Computer-aided design (CAD) research, and the CAD industry in particular, has been very successful and has enjoyed exceptional growth, paralleled only by the advances in IC fabrication. Since problems at lower levels of design became humanly intractable and time consuming earlier than on higher abstraction levels, CAD researchers and the industry first turned to problems such as circuit simulation, placement, routing and floorplanning. CAD tools for logic simulation and synthesis came later. As design complexities grew and time-to-market requirements shrank drastically, industry and academia started focusing on even higher levels of design than logic and layout. A higher level of abstraction reduces the number of objects that a designer needs to consider by an order of magnitude, which in turn allows the design and manufacture of larger systems in shorter periods of time. High-level synthesis is thus the natural next step in the design methodology of VLSI systems.
Another reason for the emphasis on high-level design methodologies is that high-level abstractions are closer to a designer's way of thinking. It is difficult to imagine a designer specifying, documenting and communicating a chip design in terms of a circuit schematic with 100,000 gates, or a logic description with 100,000 Boolean expressions. With increasing design complexity, it becomes impossible for a designer to comprehend the functionality of a chip or a system specified completely with circuit or logic schematics. A system described in terms of higher level components (e.g., memories, registers, ALUs and buses) and specified using higher level operations on data values over time exposes the design's functionality and allows a designer to consider alternative implementations with
xii HIGH-LEVEL SYNTHESIS
ease.
Research on high-level synthesis started over twenty years ago, but did not come into focus since lower level tools were not available to seriously support the insertion of high-level synthesis into the mainstream design methodology. Since then, substantial progress has been made in formulating and understanding the basic concepts in high-level synthesis. Although many open problems remain, the two most important problems are the lack of a universally accepted theoretical framework and a CAD environment supporting both automatic and manual high-level synthesis. In spite of these deficiencies, high-level synthesis has matured to the point that a book is necessary to summarize the basic concepts and results developed so far and to define the remaining open problems. Such a reference text will allow the high-level synthesis community to grow and prosper in the future.
Audience
This book in intended for three different groups in the CAD community.
First, it is intended for CAD managers and system designers who may be interested in the methodology of chip and system design and in the capabilities and limitations of high-level synthesis tools.
Second, this book can be used by CAD tool developers who may want to implement or modify algorithms for high-level synthesis. Complementary books by Camposano and Wolf [CaW091] and Walker and Camposano [WaCa91] discuss specific research approaches to high-level synthesis.
Finally, since this book surveys basic concepts in high-level design and algorithms for automatic synthesis, it is also intended for graduate students and seniors specializing in design automation and system design.
Textbook Organization
The book is organized into nine chapters that can be divided into five parts. Chapters 1 and 2 present the basic concepts and the system design process. Chapters 2 and 3 deal with design models and quality
PREFACE xiii
metrics for those models. Chapters 4 and 5 deal with design description languages and design representation. Chapters 6, 7 and 8 provide a survey of algorithms for partitioning, scheduling and allocation, while Chapter 9 covers the issues of design methodology and frameworks for high-level synthesis.
Given an understanding of the concepts defined in Chapters 1 and 2, each chapter is self-contained and can be read independently. We used the same writing style and organization in each chapter of the book. A typical chapter starts with an introductory example, defines the basic concepts and describes the main problems to be solved. It follows with a description of several well known algorithms or solutions to the posed problems and explains the advantages and disadvantages of each approach. Each chapter ends with a short survey of other work in the field and some open problems.
The book is designed for use in two different courses. One course would be on system design and methodology, omitting the synthesis algorithms in Chapters 6, 7 and 8; a second course would emphasize high-level synthesis techniques and omit the material on languages and frameworks in Chapters 4 and 9.
We have included several exercises at the end of each chapter. These exercises are divided into three categories: homework problems, project problems and thesis problems. Homework problems test the understanding of the basic material in the chapter. Project problems, indicated by an asterisk, require some literature research and a good understanding of the topic; they may require several weeks of student work. Thesis problems, indicated by a double asterisk are open problems that may result in an M.S. or even a Ph.D. thesis if researched thoroughly.
We hope that this book fills the need for a unifying body of material on high-level synthesis; we welcome your comments and corrections.
Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin Irvine, CA
September 1991
Acknowledgements
We would like to thank all of our colleagues and students with whom we discussed the basic issues in high-level synthesis over the last ten years. Without them, many issues would never be clarified and many ideas would go unchallenged.
We would also like to thank those individuals who helped us formulate the issues and focus on the material to be presented in this book. In particular, we thank Bob Grafton of NSF for encouraging research in this area, and Bob Larsen, who over the years helped us in developing quality measures and objective methods for comparative analysis.
We extend our gratitude to the following members of the U .C. Irvine CAD LAB without whom this book would not have been possible: Sanjiv Narayan and Loganath Ramachandran for rewording and editing parts of and reformulating algorithms in Chapters 7 and 8; Elke Rundensteiner and Frank Vahid for help in writing three sections and editing parts of Chapters 5, 6 and 9; Roger Ang and Jim Kipps for editing and proofreading of Chapters 2 and 4; Viraphol Chaiyakul and Tedd Hadley for typing and proofreading of and figure drawing in Chapters 1, 5 and 9; and Indraneel Ghosh, Jie Gong and Pradip Jha for help with figure drawing. In addition, all of these people carefully read drafts of chapters, suggested organizational and conceptual changes and helped with corrections to make the book more understandable. We thank Tedd Hadley for his assistance in formatting and overall production of the camera-ready manuscript.
This work was partially supported by the National Science Foundation (grants MIP-8922851 and MIP-9009239) and by the Semiconductor Research Corporation (grant 90-DJ-146). The authors are grateful for their support.