high-performance, ieee 802.15.4 wireless system-on-chip with up … · 2013. 9. 5. · datasheet...

This is information on a product in full production.

September 2012 Doc ID 16252 Rev 14 1/278

1

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory

Datasheet − production data

Features■ Complete system-on-chip

– 32-bit ARM® Cortex™-M3 processor– 2.4 GHz IEEE 802.15.4 transceiver & lower

MAC– 128/192/256-Kbyte Flash, 8/12/16-Kbyte

RAM memory– AES128 encryption accelerator– Flexible ADC, SPI/UART/I2C serial

communications, and general-purpose timers

– 24 highly configurable GPIOs with Schmitt trigger inputs

■ Industry-leading ARM® Cortex™-M3 processor– Leading 32-bit processing performance– Highly efficient Thumb®-2 instruction set– Operation at 6, 12 or 24 MHz– Flexible nested vectored interrupt controller

■ Low power consumption, advanced management– Receive current (w/ CPU): 27 mA– Transmit current (w/ CPU, +3 dBm TX):

31 mA – Low deep sleep current, with retained RAM

and GPIO: 400 nA/800 nA with/without sleep timer

– Low-frequency internal RC oscillator for low-power sleep timing

– High-frequency internal RC oscillator for fast (100 µs) processor start-up from sleep

■ Exceptional RF performance– Normal mode link budget up to 102 dB;

configurable up to 107 dB – -99 dBm normal RX sensitivity;

configurable to -100 dBm (1% PER, 20 byte packet)

– +3 dB normal mode output power; configurable up to +8 dBm

VFQFPN48(7 x 7 mm)

VFQFPN40(6 x 6 mm)

UFQFPN48(7 x 7 mm)

– Robust WiFi and Bluetooth coexistence

■ Innovative network and processor debug – Non-intrusive hardware packet trace – Serial wire/JTAG interface– Standard ARM debug capabilities: Flash

patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell

■ Application flexibility– Single voltage operation: 2.1-3.6 V with

internal 1.8 V and 1.25 V regulators– Optional 32.768 kHz crystal for higher timer

accuracy– Low external component count with single

24 MHz crystal– Support for external power amplifier– Small 7x7 mm 48-pin VFQFPN package or

6x6 mm 40-pin VFQFPN package

Applications■ Smart energy

■ Building automation and control

■ Home automation and control

■ Security and monitoring

■ ZigBee® Pro wireless sensor networking

■ RF4CE products and remote controls

■ 6LoWPAN and custom protocols

www.st.com

http://www.st.com

Contents STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.2 ARM® Cortex™-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 Memory organization and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3 Random-access memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.1 Direct memory access (DMA) to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.2 RAM memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.3 Memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.4 Memory controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5 Radio frequency module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1 Receive (Rx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.1 Rx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.2 RSSI and CCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.2 Transmit (Tx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2.1 Tx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2.2 TX_ACTIVE and nTX_ACTIVE signals . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4 Integrated MAC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.5 Packet trace interface (PTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.6 Random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6 System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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6.1 Power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1.1 Internally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1.2 Externally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2.1 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2.2 Reset recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.2.3 Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2.4 Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.3.1 High-frequency internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . 50

6.3.2 High-frequency crystal oscillator (HSE OSC) . . . . . . . . . . . . . . . . . . . . 50

6.3.3 Low-frequency internal RC oscillator (LSI10K) . . . . . . . . . . . . . . . . . . . 50

6.3.4 Low-frequency crystal oscillator (LSE OSC) . . . . . . . . . . . . . . . . . . . . . 50

6.3.5 Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3.6 Clock switching registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.4 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.4.1 MAC timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.4.2 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.4.3 Sleep timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.4.4 Event timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.4.5 Slow timer (MAC timer, Watchdog, and Sleeptimer) control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.5.1 Wake sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.5.2 Basic sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.5.3 Further options for deep sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.5.4 Use of debugger with sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.5.5 Power management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.6 Security accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

7 Integrated voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8 General-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.1.1 GPIO ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.1.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.1.3 Forced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90


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8.1.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.1.5 nBOOTMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.1.6 GPIO modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.1.7 Wake monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.3 Debug control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.4 GPIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.5 General-purpose input/output (GPIO) registers . . . . . . . . . . . . . . . . . . . . 96

8.5.1 Port x configuration register (Low) (GPIOx_CRL) . . . . . . . . . . . . . . . . . 96

8.5.2 Port x configuration register (High) (GPIOx_CRH) . . . . . . . . . . . . . . . . 97

8.5.3 Port x input data register (GPIOx_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 98

8.5.4 Port x output data register (GPIOx_ODR) . . . . . . . . . . . . . . . . . . . . . . . 98

8.5.5 Port x output set register (GPIOx_BSR) . . . . . . . . . . . . . . . . . . . . . . . . 99

8.5.6 Port x output clear register (GPIOx_BRR) . . . . . . . . . . . . . . . . . . . . . . . 99

8.5.7 External interrupt pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . 100

8.5.8 External interrupt x trigger selection register (EXTIx_TSR) . . . . . . . . . 100

8.5.9 External interrupt x configuration register (EXTIx_CR) . . . . . . . . . . . . 101

8.5.10 PC TRACE or debug select register (GPIO_PCTRACECR) . . . . . . . . 101

8.5.11 GPIO debug configuration register (GPIO_DBGCR) . . . . . . . . . . . . . . 102

8.5.12 GPIO debug status register (GPIO_DBGSR) . . . . . . . . . . . . . . . . . . . 102

8.5.13 General-purpose input/output (GPIO) register map . . . . . . . . . . . . . . . 103

9 Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

9.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

9.3.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

9.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

9.3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

9.4 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111


9.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.4.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

9.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

9.5 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . 114



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9.5.2 Constructing frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

9.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9.6 Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . 118


9.6.2 FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

9.6.3 RTS/CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

9.6.4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

9.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . 122

9.8 Serial controller common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.8.1 Serial controller interrupt status register (SCx_ISR) . . . . . . . . . . . . . . 124

9.8.2 Serial controller interrupt enable register (SCx_IER) . . . . . . . . . . . . . . 126

9.8.3 Serial controller interrupt control register 1 (SCx_ICR) . . . . . . . . . . . . 128

9.8.4 Serial controller data register (SCx_DR) . . . . . . . . . . . . . . . . . . . . . . . 129

9.8.5 Serial controller control register 2 (SCx_CR) . . . . . . . . . . . . . . . . . . . . 129

9.8.6 Serial controller clock rate register 1 (SCx_CRR1) . . . . . . . . . . . . . . . 130

9.8.7 Serial controller clock rate register 2 (SCx_CRR2) . . . . . . . . . . . . . . . 130

9.9 Serial controller: Serial peripheral interface (SPI) registers . . . . . . . . . . 131

9.9.1 Serial controller SPI status register (SCx_SPISR) . . . . . . . . . . . . . . . 131

9.9.2 Serial controller SPI control register (SCx_SPICR) . . . . . . . . . . . . . . . 132

9.10 Serial controller: Inter-integrated circuit (I2C) registers . . . . . . . . . . . . . 133

9.10.1 Serial controller I2C status register (SCx_I2CSR) . . . . . . . . . . . . . . . . 133

9.10.2 Serial controller I2C control register 1 (SCx_I2CCR1) . . . . . . . . . . . . 134

9.10.3 Serial controller I2C control register 2 (SCx_I2CCR2) . . . . . . . . . . . . 135

9.11 Serial controller: Universal asynchronous receiver/ transmitter (UART) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.11.1 Serial controller UART status register (SC1_UARTSR) . . . . . . . . . . . . 136

9.11.2 Serial controller UART control register (SC1_UARTCR) . . . . . . . . . . . 137

9.11.3 Serial controller UART baud rate register 1 (SC1_UARTBRR1) . . . . . 138

9.11.4 Serial controller UART baud rate register 2 (SC1_UARTBRR2) . . . . . 139

9.12 Serial controller: Direct memory access (DMA) registers . . . . . . . . . . . 140

9.12.1 Serial controller receive DMA begin address channel A register (SCx_DMARXBEGADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

9.12.2 Serial controller receive DMA end address channel A register (SCx_DMARXENDADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

9.12.3 Serial controller receive DMA begin address channel B register (SCx_ DMARXBEGADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141


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9.12.4 Serial controller receive DMA end address channel B register (SCx_DMARXENDADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

9.12.5 Serial controller transmit DMA begin address channel A register (SCx_DMATXBEGADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9.12.6 Serial controller transmit DMA end address channel A register (SCx_DMATXENDADDAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9.12.7 Serial controller transmit DMA begin address channel B register (SCx_DMATXBEGADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.12.8 Serial controller transmit DMA end address channel B register (SCx_DMATXENDADDBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.12.9 Serial controller receive DMA counter channel A register (SCx_DMARXCNTAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.12.10 Serial controller receive DMA count channel B register (SCx_DMARXCNTBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.12.11 Serial controller transmit DMA counter register (SCx_DMATXCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

9.12.12 Serial controller DMA status register (SCx_DMASR) . . . . . . . . . . . . . 146

9.12.13 Serial controller DMA control register (SCx_DMACR) . . . . . . . . . . . . . 148

9.12.14 Serial controller receive DMA channel A first error register (SCx_DMARXERRAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.12.15 Serial controller receive DMA channel B first error register (SCx_DMARXERRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.12.16 Serial controller receive DMA saved counter channel B register (SCx_DMARXCNTSAVEDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

9.12.17 Serial interface (SC1/SC2) register map . . . . . . . . . . . . . . . . . . . . . . . 150

10 General-purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155


10.1.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

10.1.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

10.1.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

10.1.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10.1.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

10.1.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

10.1.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

10.1.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

10.1.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.1.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

10.1.11 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

10.1.12 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180


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10.1.13 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 181

10.1.14 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

10.1.15 Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

10.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

10.3 General-purpose timers 1 and 2 registers . . . . . . . . . . . . . . . . . . . . . . . 192

10.3.1 Timer x interrupt and status register (TIMx_ISR) . . . . . . . . . . . . . . . . . 192

10.3.2 Timer x interrupt missed register (TIMx_MISSR) . . . . . . . . . . . . . . . . 193

10.3.3 Timer x interrupt enable register (TIMx_IER) . . . . . . . . . . . . . . . . . . . 193

10.3.4 Timer x control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 194

10.3.5 Timer x control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 196

10.3.6 Timer x slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . 197

10.3.7 Timer x event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 200

10.3.8 Timer x capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . 201

10.3.9 Timer x capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . 205

10.3.10 Timer x capture/compare enable register (TIMx_CCER) . . . . . . . . . . . 209

10.3.11 Timer x counter register (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 210

10.3.12 Timer x prescaler register (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 210

10.3.13 Timer x auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 211

10.3.14 Timer x capture/compare 1 register (TIMx_CCR1) . . . . . . . . . . . . . . . 211




10.3.18 Timer 1 option register (TIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

10.3.19 Timer 2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

10.3.20 General-purpose timers 1 and 2 (TIM1/TIM2) register map . . . . . . . . 214

11 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218



11.1.2 GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

11.1.3 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

11.1.4 Offset/gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

11.1.5 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

11.1.6 ADC configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

11.1.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

11.1.8 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

11.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226


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11.3 Analog-to-digital converter (ADC) registers . . . . . . . . . . . . . . . . . . . . . . 227

11.3.1 ADC interrupt status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . . . . 227

11.3.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 227

11.3.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

11.3.4 ADC offset register (ADC_OFFSETR) . . . . . . . . . . . . . . . . . . . . . . . . . 229

11.3.5 ADC gain register (ADC_GAINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

11.3.6 ADC DMA control register (ADC_DMACR) . . . . . . . . . . . . . . . . . . . . . 230

11.3.7 ADC DMA status register (ADC_DMASR) . . . . . . . . . . . . . . . . . . . . . . 230

11.3.8 ADC DMA memory start address register (ADC_DMAMSAR) . . . . . . 231

11.3.9 ADC DMA number of data to transfer register (ADC_DMANDTR) . . . 231

11.3.10 ADC DMA memory next address register (ADC_DMAMNAR) . . . . . . 232

11.3.11 ADC DMA count number of data transferred register (ADC_DMACNDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

11.3.12 Analog-to-digital converter (ADC) register map . . . . . . . . . . . . . . . . . . 233

12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 234

12.2 Management interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

12.2.1 Management interrupt source register (MGMT_ISR) . . . . . . . . . . . . . 236

12.2.2 Management interrupt mask register (MGMT_IER) . . . . . . . . . . . . . . . 237

12.2.3 Management interrupt (MGMT) register map . . . . . . . . . . . . . . . . . . . 237

13 Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

13.1 STM32W108 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

14.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

14.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

14.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

14.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

14.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

14.3.2 Operating conditions at power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

14.3.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 243


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14.4 SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

14.5 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

14.6 Clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

14.6.1 High frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 252

14.6.2 High frequency external clock characteristics . . . . . . . . . . . . . . . . . . . 252

14.6.3 Low frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 253

14.6.4 Low frequency external clock characteristics . . . . . . . . . . . . . . . . . . . . 253

14.7 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

14.8 Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

14.9 Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 260

14.10 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

14.10.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

14.10.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

14.10.3 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Description STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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1 Description

The STM32W108 is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-compliant transceiver, 32-bit ARM® Cortex™-M3 microprocessor, Flash and RAM memory, and peripherals of use to designers of 802.15.4-based systems.

The transceiver utilizes an efficient architecture that exceeds the dynamic range requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated receive channel filtering allows for robust co-existence with other communication standards in the 2.4 GHz spectrum, such as IEEE 802.11 and Bluetooth. The integrated regulator, VCO, loop filter, and power amplifier keep the external component count low. An optional high performance radio mode (boost mode) is software-selectable to boost dynamic range.

The integrated 32-bit ARM® Cortex™-M3 microprocessor is highly optimized for high performance, low power consumption, and efficient memory utilization. Including an integrated MPU, it supports two different modes of operation: Privileged mode and Unprivileged mode. This architecture could be used to separate the networking stack from the application code and prevent unwanted modification of restricted areas of memory and registers resulting in increased stability and reliability of deployed solutions.

The STM32W108 has 128/192/256 Kbytes of embedded Flash memory and 8/12/16 Kbytes of integrated RAM for data and program storage. The STM32W108 HAL software employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded Flash.

To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003 standards, the STM32W108 integrates a number of MAC functions into the hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. A packet trace interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from the STM32W108.

The STM32W108 offers a number of advanced power management features that enable long battery life. A high-frequency internal RC oscillator allows the processor core to begin code execution quickly upon waking. Various deep sleep modes are available with less than 1 µA power consumption while retaining RAM contents. To support user-defined applications, on-chip peripherals include UART, SPI, I2C, ADC and general-purpose timers, as well as up to 24 GPIOs. Additionally, an integrated voltage regulator, power-on-reset circuit, and sleep timer are available.

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Description

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Packet sniffer

ADCRF_P,N

Program Flash128 kBytes192 kBytes256 kBytes

Data SRAM8 kBytes12 kBytes16 kBytes

HF crystal OSC

LF crystal OSC

General Purpose

ADC

Serial Wire and

JTAG debug

Internal LF RC-OSC

GPIO multiplexor swtich

Chip manager

Regulator

Bias

2nd levelInterrupt controller

RF_TX_ALT_P,N

PA[7:0], PB[7:0], PC[7:0]

Encryption acclerator

IF

AlwaysPowered Domain

ARM CORTEX-M3®CPU with NVIC

and MPU

VREG_OUTWatchdog

PA select

LNA

PA

PADAC

MAC+

Baseband

Sleeptimer

BIAS_R

PORnRESET

General purpose timers

GPIO registers

UART/SPI/I2C

SYNTH

Internal HF RC-OSC

TX_ACTIVE

SWCLK, JTCK

CalibrationADC

Packet TraceCPU debug TPIU/ITM/FPB/DWT

Ai15250

OSC_OUT

OSC_IN

1.1 Development toolsThe STM32W108 implements both the ARM Serial Wire and JTAG debug interfaces. These interfaces provide real time, non-intrusive programming and debugging capabilities. Serial Wire and JTAG provide the same functionality, but are mutually exclusive. The Serial Wire interface uses two pins; the JTAG interface uses five. Serial Wire is preferred, since it uses fewer pins.

The STM32W108 also integrates the standard ARM system debug components: Flash Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace Macrocell (DWT).

Figure 1. STM32W108 block diagram

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1.2 Overview

1.2.1 Functional description

The STM32W108 radio receiver is a low-IF, super-heterodyne receiver. The architecture has been chosen to optimize co-existence with other devices in the 2.4 GHz band (namely, WIFI and Bluetooth), and to minimize power consumption. The receiver uses differential signal paths to reduce sensitivity to noise interference. Following RF amplification, the signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.

The radio transmitter uses an efficient architecture in which the data stream directly modulates the VCO frequency. An integrated power amplifier (PA) provides the output power. Digital logic controls Tx path and output power calibration. If the STM32W108 is to be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the timing of the external switching logic.

The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz crystal with its loading capacitors is required to establish the PLL local oscillator signal.

The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC provides hardware-based IEEE 802.15.4 packet-level filtering. It supplies an accurate symbol time base that minimizes the synchronization effort of the software stack and meets the protocol timing requirements. In addition, it provides timer and synchronization assistance for the IEEE 802.15.4 CSMA-CA algorithm.

The STM32W108 integrates an ARM® Cortex-M3 microprocessor, revision r1p1. This industry-leading core provides 32 bit performance and is very power efficient. It has excellent code density using the ARM® Thumb 2 instruction set. The processor can be operated at 12 MHz or 24 MHz when using the crystal oscillator, or at 6 MHz or 12 MHz when using the integrated high frequency RC oscillator.

The STM32W108 has 128/192/256 Kbytes of Flash memory, 8/12/16 Kbytes of SRAM on-chip, and the ARM configurable memory protection unit (MPU).

The STM32W108 contains 24 GPIO pins shared with other peripheral or alternate functions. Because of flexible routing within the STM32W108, external devices can use the alternate functions on a variety of different GPIOs. The integrated Serial Controller SC1 can be configured for SPI (master or slave), I2C (master-only), or UART operation, and the Serial Controller SC2 can be configured for SPI (master or slave) or I2C (master-only) operation.

The STM32W108 has a general purpose ADC which can sample analog signals from six GPIO pins in single-ended or differential modes. It can also sample the regulated supply VDD_PADSA, the voltage reference VREF, and GND. The ADC has two selectable voltage ranges: 0 V to 1.2 V for the low voltage (input buffer disabled) and 0.1 V to VDD_PADS minus 0.1 V for the high voltage supply (input buffer enabled). The ADC has a DMA mode to capture samples and automatically transfer them into RAM. The integrated voltage reference for the ADC, VREF, can be made available to external circuitry. An external voltage reference can also be driven into the ADC.

The STM32W108 contains four oscillators: a high frequency 24 MHz external crystal oscillator (24 MHz HSE OSC), a high frequency 12 MHz internal RC oscillator (12 MHz HSI RC), an optional low frequency 32.768 kHz external crystal oscillator (32 kHz HSE OSC), and a 10 kHz internal RC oscillator (10 kHz LSI RC).

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The STM32W108 has an ultra low power, deep sleep state with a choice of clocking modes. The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator or with a 1 kHz clock derived from the internal 10 kHz LSI RC oscillator. Alternatively, all clocks can be disabled for the lowest power mode. In the lowest power mode, only external events on GPIO pins will wake up the chip. The STM32W108 has a fast startup time (typically 100 µs) from deep sleep to the execution of the first ARM® Cortex-M3 instruction.

The STM32W108 contains three power domains. The always-on high voltage supply powers the GPIO pads and critical chip functions. Regulated low voltage supplies power the rest of the chip. The low voltage supplies are be disabled during deep sleep to reduce power consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8 V voltages from an unregulated supply voltage. The 1.8 V regulator output is decoupled and routed externally to supply analog blocks, RAM, and Flash memories. The 1.25 V regulator output is decoupled externally and supplies the core logic.

The digital section of the receiver uses a coherent demodulator to generate symbols for the hardware-based MAC. The digital receiver also contains the analog radio calibration routines and controls the gain within the receiver path.

In addition to 2 general-purpose timers, the STM32W108 also contains a watchdog timer to ensure protection against software crashes and CPU lockup, a 32-bit sleep timer dedicated to system timing and waking from sleep at specific times and an ARM® standard system event timer in the NVIC.

The STM32W108 integrates hardware support for a Packet Trace module, which allows robust packet-based debug.

Note: The STM32W108 is not pin-compatible with the previous generation chip, the SN250, except for the RF section of the chip. Pins 1-11 and 45-48 are compatible, to ease migration to the STM32W108.

1.2.2 ARM® Cortex™-M3 core

The STM32W108 integrates the ARM® Cortex™-M3 microprocessor, revision r1p1, developed by ARM Ltd, making the STM32W108 a true system-on-a-chip solution. The ARM® Cortex-M3 is an advanced 32-bit modified Harvard architecture processor that has separate internal program and data buses, but presents a unified program and data address space to software. The word width is 32 bits for both the program and data sides. The ARM® Cortex-M3 allows unaligned word and half-word data accesses to support efficiently-packed data structures.

The ARM® Cortex-M3 clock speed is configurable to 6 MHz, 12 MHz, or 24 MHz. For normal operation 12 MHz is preferred over 24 MHz due to its lower power consumption. The 6 MHz operation can only be used when radio operations are not required since the radio requires an accurate 12 MHz clock.

The ARM® Cortex-M3 in the STM32W108 has also been enhanced to support two separate memory protection levels. Basic protection is available without using the MPU, but the usual operation uses the MPU. The MPU protects unimplemented areas of the memory map to prevent common software bugs from interfering with software operation. The architecture could also separate the networking stack from the application code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the developer to assist in tracking down and fixing issues.

Documentation conventions STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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2 Documentation conventions

Software can read and write to these bits.

Software can only read these bits.

Software can only write to this bit. Reading returns the reset value.

Software can read and write to these bits only in Privileged mode. For more information, please refer to RAM memory protection on page 33 and Memory protection unit on page 38.

Table 1. Description of abbreviations used for bit field access

Abbreviation Description(1)

1. The conditions under which the hardware (core) sets or clears this field are explained in details in the bit field description, as well as the events that may be generated by writing to the bit.

Read/Write (rw)

Read-only (r)

Write only (w)

Read/Write in (MPU) Privileged mode only (rws)

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Pinout and pin description

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3 Pinout and pin description

Figure 2. 48-pin VFQFPN pinout

Ai15261

Ground pad on back

VDD_24MHZ

RF_P

RF_N

VDD_RF

RF_TX_ALT_P

RF_TX_ALT_N

VDD_IF

BIAS_R

VDD_PADSA

PC5, TX_ACTIVE

VD

D_PA

DS

PA1, T

IM2C

3, SC

2SD

A, S

C2M

ISO

PA0, T

IM2C

1, SC

2MO

SI

PA7, T

IM1C

4, RE

G_E

N

VD

D_C

OR

E

VR

EG

_OU

T

PC

6, OS

C32_IN

, nTX

_AC

TIV

E

VD

D_PA

DS

PA2, T

IM2C

4, SC

2SC

L, SC

2SC

LK

PB0, VREF, IRQA, TRACECLK, TIM1CLK, TIM2MSK

PC4, JTMS, SWDIO

PC3, JTDI

PC2, JTDO, SWO

SWCLK, JTCK

VDD_PADS

PA5, ADC5, PTI_DATA, nBOOTMODE, TRACEDATA3

PA4, ADC4, PTI_EN, TRACEDATA2

PA3, SC2nSSEL, TRACECLK, TIM2C2

PC

1, AD

C3, S

WO

, TR

AC

ED

ATA0

VD

D_M

EM

PB

7, AD

C2, IR

QC

, TIM

1C2

PB

5, AD

C0, T

IM2C

LK, T

IM1M

SK

VD

D_C

OR

E

VD

D_P

RE

OS

C_O

UT

PC

0, JRS

T, IRQ

Dn, T

RA

CE

DATA

1

OS

C_IN

VD

D_PA

DS

1

2

3

4

5

6

7

8

9

10

11

1213 14 15 16 17 18 19 20 21 22 23 24

36

35

34

33

32

31

30

29

28

27

26

25

48 47 46 45 44 43 42 41 40 39 38 37

VDD_VCO

nRESET

PC

7, OS

C32_O

UT, O

SC

32_EX

T

PB

3, TIM

2C3, S

C1nC

TS

, SC

1SC

LK

PB

4, TIM

2C4, S

C1nR

TS

, SC

1nSS

EL

PB1, SC1MISO, SC1MOSI, SC1SDA, SC1TXD, TIM2C1

PA6, TIM1C3

PB2, SC1MISO, SC1MOSI, SC1SCL, SC1RXD, TIM2C2

VD

D_S

YN

TH

PB

6, AD

C1, IR

Q6, T

IM1C

1

Pinout and pin description STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Figure 3. 40-pin VFQFPN pinout

Ai15260

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31

30

29

28

27

26

25

24

23

22

21Ground pad on back

VDD_VCO

RF_P

RF_N

VDD_RF

RF_TX_ALT_P

RF_TX_ALT_N

VDD_IF

BIAS_R

VDD_PADSA

PC5, TX_ACTIVE

VD

D_PA

DS

PA1, T

IM2C

3, SC

2SD

A, S

C2M

ISO

PA0, T

IM2C

1, SC

2MO

SI

PB

4, TIM

2C4, S

C1nR

TS

, SC

1nSS

EL

PB

3, TIM

2C3, S

C1nC

TS

, SC

1SC

LK

VD

D_C

OR

E

VR

EG

_OU

T

nRE

SE

T

VD

D_PA

DS

PA2, T

IM2C

4, SC

2SC

L, SC

2SC

LK

PC4, JTMS, SWDIO

PC3, JTDI

PC2, JTDO, SWO

SWCLK, JTCK

PB2, SC1MISO, SC1MOSI, SC1SCL, SC1RXD, TIM2C2

PB1, SC1MISO, SC1MOSI, SC1SDA, SC1TXD, TIM2C1

VDD_PADS

PA5, ADC5, PTI_DATA, nBOOTMODE, TRACEDATA3

PA4, ADC4, PTI_EN, TRACEDATA2

PA3, SC2nSSEL, TRACECLK, TIM2C2

VD

D_M

EM

PC

0, JRS

T, IRQ

Dn, T

RA

CE

DATA

1

PB

7, AD

C2, IR

QC

, TIM

1C2

PB

6, AD

C1, IR

Q6, T

IM1C

1

VD

D_C

OR

E

VD

D_P

RE

OS

C_O

UT

VD

D_24M

HZ

OS

C_IN

PC

1, AD

C3, S

WO

, TR

AC

ED

ATA0

Table 2. Pin descriptions

48-Pin Package Pin no.


Signal Direction Description

1 40 VDD_24MHZ Power 1.8V high-frequency oscillator supply

2 1 VDD_VCO Power 1.8V VCO supply

3 2 RF_P I/O Differential (with RF_N) receiver input/transmitter output

4 3 RF_N I/O Differential (with RF_P) receiver input/transmitter output

5 4 VDD_RF Power 1.8V RF supply (LNA and PA)

6 5 RF_TX_ALT_P O Differential (with RF_TX_ALT_N) transmitter output (optional)

7 6 RF_TX_ALT_N O Differential (with RF_TX_ALT_P) transmitter output (optional)

8 7 VDD_IF Power 1.8V IF supply (mixers and filters)

9 8 BIAS_R I Bias setting resistor


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10 9 VDD_PADSA Power Analog pad supply (1.8V)

11 10

PC5 I/O Digital I/O

TX_ACTIVE O

Logic-level control for external Rx/Tx switch. The STM32W108 baseband controls TX_ACTIVE and drives it high (VDD_PADS) when in Tx mode.Select alternate output function with GPIOC_CRH[7:4]

12 11 nRESET I Active low chip reset (internal pull-up)

13

PC6 I/O Digital I/O

OSC32_IN I/O32.768 kHz crystal oscillatorSelect analog function with GPIOC_CRH[11:8]

nTX_ACTIVE OInverted TX_ACTIVE signal (see PC5)Select alternate output function with GPIOC_CRH[11:8]

14

PC7 I/O Digital I/O

OSC32_OUT I/O32.768 kHz crystal oscillator.Select analog function with GPIOC_CRH[15:12]

OSC32_EXT I Digital 32 kHz clock input source

15 12 VREG_OUT Power Regulator output (1.8 V while awake, 0 V during deep sleep)

16 13 VDD_PADS Power Pads supply (2.1-3.6 V)

17 14 VDD_CORE Power 1.25 V digital core supply decoupling

18

PA7I/O

High current

Digital I/O. Disable REG_EN with GPIO_DBGCR[4]

TIM1_CH4O

Timer 1 Channel 4 outputEnable timer output with TIM1_CCERSelect alternate output function with GPIOA_CRH[15:12]Disable REG_EN with GPIO_DBGCR[4]

I Timer 1 Channel 4 input. (Cannot be remapped.)

REG_EN O External regulator open drain output. (Enabled after reset.)

Table 2. Pin descriptions (continued)





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19 15

PB3 I/O Digital I/O

TIM2_CH3 (see Pin 22)

O

Timer 2 channel 3 outputEnable remap with TIM2_OR[6]Enable timer output in TIM2_CCERSelect alternate output function with GPIOB_CRL[15:12]

I Timer 2 channel 3 input. Enable remap with TIM2_OR[6].

UART_CTS IUART CTS handshake of Serial Controller 1Enable with SC1_UARTCR[5]Select UART with SC1_CR

SC1SCLK

O

SPI master clock of Serial Controller 1Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[6]Enable master with SC1_SPICR[4] Select SPI with SC1_CRSelect alternate output function with GPIOB_CRL[15:12]

ISPI slave clock of Serial Controller 1Enable slave with SC1_SPICR[4] Select SPI with SC1_CR

20 16

PB4 I/O Digital I/O

TIM2_CH4 (see also Pin 24)

O

Timer 2 channel 4 outputEnable remap with TIM2_OR[7]Enable timer output in TIM2_CCERSelect alternate output function with GPIOB_CRH[3:0]


UART_RTS O

UART RTS handshake of Serial Controller 1Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[7] Enable with SC1_UARTCR[5]Select UART with SC1_CRSelect alternate output function with GPIOB_CRH[3:0]

SC1nSSEL ISPI slave select of Serial Controller 1Enable slave with SC1_SPICR[4] Select SPI with SC1_CR






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21 17

PA0 I/O Digital I/O


O

Timer 2 channel 1 outputDisable remap with TIM2_OR[4]Enable timer output in TIM2_CCERSelect alternate output function with GPIOA_CRL[3:0]

I Timer 2 channel 1 input. Disable remap with TIM2_OR[4].

SC2MOSI

O

SPI master data out of Serial Controller 2Either disable timer output in TIM2_CCER or enable remap with TIM2_OR[4]Enable master with SC2_SPICR[4] Select SPI with SC2_CRSelect alternate output function with GPIOA_CRL[3:0]

ISPI slave data in of Serial Controller 2Enable slave with SC2_SPICR[4] Select SPI with SC2_CR

22 18

PA1 I/O Digital I/O


O



SC2SDA I/O

I2C data of Serial Controller 2Either disable timer output in TIM2_CCER or enable remap with TIM2_OR[6]Select I2C with SC2_CRSelect alternate open-drain output function with GPIOA_CRL[7:4]

SC2MISO

O

SPI slave data out of Serial Controller 2Either disable timer output in TIM2_CCER or enable remap with TIM2_OR[6]Enable slave with SC2_SPICR[4] Select SPI with SC2_CRSelect alternate output function with GPIOA_CRL[7:4]

ISPI master data in of Serial Controller 2Enable slave with SC2_SPICR[4] Select SPI with SC2_CR

23 19 VDD_PADS Power Pads supply (2.1-3.6V)






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24 20

PA2 I/O Digital I/O


O



SC2SCL I/O

I2C clock of Serial Controller 2Either disable timer output in TIM2_CCER or enable remap with TIM2_OR[7]Select I2C with SC2_CRSelect alternate open-drain output function with GPIOA_CRL[11:8]

SC2SCLK

O

SPI master clock of Serial Controller 2Either disable timer output in TIM2_CCER or enable remap with TIM2_OR[7]Enable master with SC2_SPICR[4] Select SPI with SC2_CRSelect alternate output function with GPIOA_CRL[11:8]

ISPI slave clock of Serial Controller 2Enable slave with SC2_SPICR[4] Select SPI with SC2_CR

25 21

PA3 I/O Digital I/O

SC2nSSEL ISPI slave select of Serial Controller 2Enable slave with SC2_SPICR[4] Select SPI with SC2_CR

TRACECLK (see also Pin 36)

O

Synchronous CPU trace clockEither disable timer output in TIM2_CCER or enable remap with TIM2_OR[5]Enable trace interface in ARM coreSelect alternate output function with GPIOA_CRL[15:12]


O








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26 22

PA4 I/O Digital I/O

ADC4 Analog ADC Input 4. Select analog function with GPIOA_CRH[3:0].

PTI_EN OFrame signal of Packet Trace Interface (PTI).Disable trace interface in ARM core.Select alternate output function with GPIOA_CRH[3:0].

TRACEDATA2 O

Synchronous CPU trace data bit 2.Select 4-wire synchronous trace interface in ARM core.Enable trace interface in ARM core.Select alternate output function with GPIOA_CRH[3:0].

27 23

PA5 I/O Digital I/O

ADC5 Analog ADC Input 5. Select analog function with GPIOA_CRH[7:4].

PTI_DATA OData signal of Packet Trace Interface (PTI).Disable trace interface in ARM core.Select alternate output function with GPIOA_CRH[7:4].

nBOOTMODE IEmbedded serial bootloader activation out of reset.Signal is active during and immediately after a reset on NRST. See Section 6.2: Resets on page 44 for details.

TRACEDATA3 O

Synchronous CPU trace data bit 3.Select 4-wire synchronous trace interface in ARM core.Enable trace interface in ARM core.Select alternate output function with GPIOA_CRH[7:4]

28 24 VDD_PADS Power Pads supply (2.1-3.6 V)

29

PA6I/O

High current

Digital I/O

TIM1_CH3O

Timer 1 channel 3 outputEnable timer output in TIM1_CCERSelect alternate output function with GPIOA_CRH[11:8]

I Timer 1 channel 3 input (Cannot be remapped.)






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30 25

PB1 I/O Digital I/O

SC1MISO O

SPI slave data out of Serial Controller 1Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[4]Select SPI with SC1_CRSelect slave with SC1_SPICRSelect alternate output function with GPIOB_CRL[7:4]

SC1MOSI O

SPI master data out of Serial Controller 1Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[4]Select SPI with SC1_CRSelect master with SC1_SPICRSelect alternate output function with GPIOB_CRL[7:4]

SC1SDA I/O

I2C data of Serial Controller 1Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4]Select I2C with SC1_CRSelect alternate open-drain output function with GPIOB_CRL[7:4]

SC1TXD O

UART transmit data of Serial Controller 1Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[4]Select UART with SC1_CRSelect alternate output function with GPIOB_CRL[7:4]


O

Timer 2 channel 1 outputEnable remap with TIM2_OR[4]Enable timer output in TIM2_CCERSelect alternate output function with GPIOA_CRL[7:4]







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31 26

PB2 I/O Digital I/O

SC1MISO ISPI master data in of Serial Controller 1Select SPI with SC1_CRSelect master with SC1_SPICR

SC1MOSI ISPI slave data in of Serial Controller 1Select SPI with SC1_CRSelect slave with SC1_SPICR

SC1SCL I/O

I2C clock of Serial Controller 1Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[5]Select I2C with SC1_CRSelect alternate open-drain output function with GPIOB_CRL[11:8]

SC1RXD IUART receive data of Serial Controller 1Select UART with SC1_CR


O

Timer 2 channel 2 outputEnable remap with TIM2_OR[5]Enable timer output in TIM2_CCERSelect alternate output function with GPIOB_CRL[11:8]


32 27

SWCLK I/OSerial Wire clock input/output with debuggerSelected when in Serial Wire mode (see JTMS description, Pin 35)

JTCK I

JTAG clock input from debuggerSelected when in JTAG mode (default mode, see JTMS description, Pin 35)Internal pull-down is enabled

33 28

PC2 I/ODigital I/OEnable with GPIO_DBGCR[5]

JTDO OJTAG data out to debuggerSelected when in JTAG mode (default mode, see JTMS description, Pin 35)

SWO O

Serial Wire Output asynchronous trace output to debuggerSelect asynchronous trace interface in ARM coreEnable trace interface in ARM coreSelect alternate output function with GPIOC_CRL[11:8]Enable Serial Wire mode (see JTMS description, Pin 35)Internal pull-up is enabled






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34 29

PC3 I/ODigital I/OEither Enable with GPIO_DBGCR[5], or enable Serial Wire mode (see JTMS description)

JTDI I

JTAG data in from debuggerSelected when in JTAG mode (default mode, see JTMS description, Pin 35)Internal pull-up is enabled

35 30

PC4 I/ODigital I/OEnable with GPIO_DBGCR[5]

JTMS I

JTAG mode select from debuggerSelected when in JTAG mode (default mode)JTAG mode is enabled after power-up or by forcing NRST lowSelect Serial Wire mode using the ARM-defined protocol through a debuggerInternal pull-up is enabled

SWDIO I/O

Serial Wire bidirectional data to/from debuggerEnable Serial Wire mode (see JTMS description)Select Serial Wire mode using the ARM-defined protocol through a debuggerInternal pull-up is enabled

36

PB0 I/O Digital I/O

VREF Analog OADC reference output.Enable analog function with GPIOB_CRL[3:0].

VREF Analog IADC reference input.Enable analog function with GPIOB_CRL[3:0].Enable reference output with an ST system function.

IRQA I External interrupt source A.

TRACECLK (see also Pin 25)

OSynchronous CPU trace clock.Enable trace interface in ARM core.Select alternate output function with GPIOB_CRL[3:0].

TIM1CLK I Timer 1 external clock input.

TIM2MSK I Timer 2 external clock mask input.

37 VDD_PADS Power Pads supply (2.1 to 3.6 V).






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38 31

PC1 I/O Digital I/O

ADC3 AnalogADC Input 3Enable analog function with GPIOC_CRL[7:4]

SWO (see also Pin 33)

O

Serial Wire Output asynchronous trace output to debuggerSelect asynchronous trace interface in ARM coreEnable trace interface in ARM coreSelect alternate output function with GPIOC_CRL[7:4]

TRACEDATA0 O

Synchronous CPU trace data bit 0Select 1-, 2- or 4-wire synchronous trace interface in ARM coreEnable trace interface in ARM coreSelect alternate output function with GPIOC_CRL[7:4]

39 32 VDD_MEM Power 1.8 V supply (Flash, RAM)

40 33

PC0I/O

High current

Digital I/OEither enable with GPIO_DBGCR[5], or enable Serial Wire mode (see JTMS description, Pin 35) and disable TRACEDATA1

JRST I

JTAG reset input from debuggerSelected when in JTAG mode (default mode, see JTMS description) and TRACEDATA1 is disabledInternal pull-up is enabled

IRQD (1) I Default external interrupt source D

TRACEDATA1 O

Synchronous CPU trace data bit 1Select 2- or 4-wire synchronous trace interface in ARM coreEnable trace interface in ARM coreSelect alternate output function with GPIOC_CRL[3:0]

41 34

PB7I/O

High current

Digital I/O

ADC2 AnalogADC Input 2Enable analog function with GPIOB_CRH[15:12]

IRQC (1) I Default external interrupt source C

TIM1_CH2O

Timer 1 channel 2 outputEnable timer output in TIM1_CCERSelect alternate output function with GPIOB_CRH[15:12]

I Timer 1 channel 2 input (Cannot be remapped)






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42 35

PB6I/O

High current

Digital I/O


IRQB I External interrupt source B

TIM1_CH1O

Timer 1 channel 1 outputEnable timer output in TIM1_CCERSelect alternate output function with GPIOB_CRH[11:8]

I Timer 1 channel 1 input (Cannot be remapped)

43

PB5 I/O Digital I/O


TIM2CLK I Timer 2 external clock input

TIM1MSK I Timer 2 external clock mask input

44 36 VDD_CORE Power 1.25 V digital core supply decoupling

45 37 VDD_PRE Power 1.8 V prescaler supply

46 VDD_SYNTH Power 1.8 V synthesizer supply

47 38 OSC_IN I/O24 MHz HSE OSC or left open when using external clock input on OSC_OUT

48 39 OSC_OUT I/O 24 MHz HSE OSC or external clock input

49 41 GND Ground Ground supply pad in the bottom center of the package.

1. IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the EXTIC_CR and EXTID_CR registers.





STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Embedded memory

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4 Embedded memory

4.1 Memory organization and memory mapThe bytes are coded in the memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.

For detailed mapping of peripheral registers, please refer to the relevant section.

All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”).

Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register boundary addresses for the register boundary addresses of the peripherals available in all STM32W108xx devices.

Embedded memory STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Figure 4. STM32W108xB memory mapping

Main Flash Block (128kB)Lower mapping(Normal Mode)

07

0x00000000

0x0001FFFF

RAM (8kB)mapped onto System

interface0x20000000

0x20001FFF

RAM bit bandalias region

mapped onto System interface

(not used)

0x22000000

0x22002000

Flash

RAM

Peripheral

Registersmapped onto System

interface

Register bit bandalias region

mapped onto System interface

(not used)

0x40000000

0x40000XXX

0x42000000

0x42002XXX

Not used

Private periph bus (internal)

Not used

Private periph bus (external)

Not used

Not used

Not used

0xE0000000ITM

DWT

FPB

NVIC

TPIU

ROM table

0xE0001000

0xE0002000

0xE0003000

0xE000E000

0xE000F000

0xE003FFFF

0xE0040000

0xE0041000

0xE0042000

0xE00FF000

0xE00FFFFF

0xE0000000

0x00000000

0x20000000

0x40000000

0x60000000

0xA0000000

0xFFFFFFFF

0xDFFFFFFF

0x9FFFFFFF

0x5FFFFFFF

0x3FFFFFFF

0x1FFFFFFF

Fixed Info Block (2kB)

Customer Info Block (0.5kB)

0x08040000

0x080407FF

0x080409FF0x08040800

Main Flash Block (128kB)Upper mapping

(Boot mode)

0x08000000

0x0801FFFF

Fixed Info Block (2kB)

Optional boot mode maps Fixed Info Blockto the start of memory

0x000007FF

Not used

Not used

Ai15259


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Figure 5. STM32W108CC and STM32W108CZ memory mapping


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Table 3. STM32W108xx peripheral register boundary addresses

Bus Boundary address Peripheral Register map

APB

0x4000 F000 - 0x4000 FFFF General-purpose timer 2

(TIM2)

Table 10.3.20: General-purpose timers 1 and 2

(TIM1/TIM2) register map

0x4000 E000 - 0x4000 EFFFGeneral-purpose timer 1

(TIM1)

Table 10.3.20: General-purpose timers 1 and 2

(TIM1/TIM2) register map

0x4000 D025 - 0x4000 DFFF Reserved -

0x4000 D000 - 0x4000 D024Analog-to-digital converter

(ADC)

Table 11.3.12: Analog-to-digital converter (ADC) register map

0x4000 C871 - 0x4000 CFFF Reserved -

0x4000 C800 - 0x4000 C870Serial interface

(SC1)

Table 9.12.17: Serial interface (SC1/SC2)

register map

0x4000 C071 - 0x4000 C7FF Reserved -

0x4000 C000 - 0x4000 C070Serial interface

(SC2)

Table 9.12.17: Serial interface (SC1/SC2)

register map

0x4000 B000 - 0x4000 BFFFGeneral-purpose

input/output (GPIO)

Table 8.5.13: General-purpose input/output (GPIO) register map

0x4000 A000 - 0x4000 AFFFManagement interrupt

(MGMT)

Table 12.2.3: Management interrupt (MGMT) register map

0x4000 6025 - 0x4000 9FFF Reserved -

0x4000 600C - 0x4000 6024 Sleeptimer (SLPTMR)

MAC timer (MACTMR)/Watchdog

(WDG)/Sleeptimer(SLPTMR) register map

0x4000 6009 - 0x4000 600B Reserved -

0x4000 6000 - 0x4000 6008Watchdog

(WDG)



0x4000 5000 - 0x4000 5FFFMemory controller

(MEM)Memory controller

(MEM) register map

0x4000 4021 - 0x4000 4FFF Reserved -

0x4000 4000 - 0x4000 4020Clock switching

(CLK)Clock switching (CLK)

register map

0x4000 3000 - 0x4000 3FFF Reserved -


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4.2 Flash memoryThe STM32W108 provides Flash memory in four separate blocks as follows:

● Main Flash Block (MFB)

● Fixed Information Block (FIB)

● Fixed Information Block Extension (FIB-EXT)

● Customer Information Block (CIB)

The size of these blocks and associated page size is described in Table 4.

The smallest erasable unit is one page and the smallest writable unit is an aligned 16-bit half-word. The Flash is guaranteed to have 10k write/erase cycles. The Flash cell has been qualified for a data retention time of >100 years at room temperature.

APB

0x4000 2000 - 0x4000 2FFFMAC timer(MACTMR)



0x4000 1000 - 0x4000 1FFF Reserved -

0x4000 0000 - 0x4000 0FFFPower management

(PWR)Power management (PWR) register map

0x2000 4000 - 0x3FFF FFFF Reserved -

0x2000 0000 - 0x2000 3FFF SRAM -

0x0804 0000 - 0x1FFF FFFF Reserved -

0x0800 0000 - 0x0803 FFFF Main Flash memory

(256 Kbyte)-

Table 3. STM32W108xx peripheral register boundary addresses

Bus Boundary address Peripheral Register map

Table 4. Flash memory

STM32W108xB STM32W108CC STM32W108CZUnit

Size Page size Size Page size Size Page size

MFB 128 1 256 2 192 2 K Bytes

FIB 2 2 2 2 2 2 K Bytes

CIB 0.5 0.5 2 2 2 2 K Bytes

FIB-EXT 0 N/A 16 2 16 2 K Bytes

Total 130.5 276 212 K Bytes


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Flash may be programmed either through the Serial Wire/JTAG interface or through bootloader software. Programming Flash through Serial Wire/JTAG requires the assistance of RAM-based utility code. Programming through a bootloader requires specific software for over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also available preprogrammed into the FIB.

4.3 Random-access memoryThe STM32W108 has 8/12/16 Kbytes of static RAM on-chip. The start of RAM is mapped to address 0x20000000. Although the ARM® Cortex-M3 allows bit band accesses to this address region, the standard MPU configuration does not permit use of the bit-band feature.

The RAM is physically connected to the AHB System bus and is therefore accessible to both the ARM® Cortex-M3 microprocessor and the debugger. The RAM can be accessed for both instruction and data fetches as bytes, half words, or words. The standard MPU configuration does not permit execution from the RAM, but for special purposes, such as programming the main Flash block, the MPU may be disabled. To the bus, the RAM appears as 32-bit wide memory and in most situations has zero wait state read or write access. In the higher CPU clock mode the RAM requires two wait states. This is handled by hardware transparent to the user application with no configuration required.

4.3.1 Direct memory access (DMA) to RAM

Several of the peripherals are equipped with DMA controllers allowing them to transfer data into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full duplex so that a read and a write to RAM may be requested at the same time. Thus there are six DMA channels in total.

The STM32W108 integrates a DMA arbiter that ensures fair access to the microprocessor as well as the peripherals through a fixed priority scheme appropriate to the memory bandwidth requirements of each master. The priority scheme is as follows, with the top peripheral being the highest priority:

1. General Purpose ADC2. Serial Controller 2 Receive3. Serial Controller 2 Transmit4. MAC5. Serial Controller 1 Receive6. Serial Controller 1 Transmit


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4.3.2 RAM memory protection

The STM32W108 integrates two memory protection mechanisms. The first memory protection mechanism is through the ARM® Cortex-M3 Memory Protection Unit (MPU) described in the Memory Protection Unit section. The MPU may be used to protect any area of memory. MPU configuration is normally handled by software. The second memory protection mechanism is through a fine granularity RAM protection module. This allows segmentation of the RAM into blocks where any block can be marked as write protected. An attempt to write to a protected RAM block using a user mode write results in a bus error being signaled on the AHB System bus. A system mode write is allowed at any time and reads are allowed in either mode. The main purpose of this fine granularity RAM protection module is to notify the stack of erroneous writes to system areas of memory. RAM protection is configured using a group of registers that provide a bit map. Each bit in the map represents a 32-byte block of RAM for STM32W108xB and 64 bytes of RAM for STM32W108CC and STM32W108CZ.When the bit is set the block is write protected.

The fine granularity RAM memory protection mechanism is also available to the peripheral DMA controllers. A register bit is provided to enable the memory protection to include DMA writes to protected memory. If a DMA write is made to a protected location in RAM, a management interrupt is generated. At the same time the faulting address and the identification of the peripheral is captured for later debugging. Note that only peripherals capable of writing data to RAM, such as received packet data or a received serial port character, can generate this interrupt.

4.3.3 Memory controller

The STM32W108xx allows the RAM and DMA protection to be controlled using the memory controller interface. The chip contains eight RAM protection registers and two DMA protection registers. In addition, the chip contains a register, RAM_CR, for enabling the protection of the memory.


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4.3.4 Memory controller registers

RAM is divided into 32 byte pages. Each page has a register bit that, when set, protects it from being written in user mode. The protection registers (MEM_PROT) are arranged in the register map as a 256-bit vector. Bit 0 of this vector protects page 0 which begins at location 0x2000 0000 and ends at 0x2000 001F. Bit 255 of this vector protects the top page which starts at 0x20001FE0 and ends at 0x2000 1FFF.

Memory RAM protection register x (RAM_PROTRx)

Address: 0x 4000 5000 (RAM_PROTR1), 0x 4000 5004 (RAM_PROTR2), 0x 4000 5008 (RAM_PROTR3), 0x 4000 500C (RAM_PROTR4), 0x 4000 5010 (RAM_PROTR5), 0x 4000 5014 (RAM_PROTR6), 0x 4000 5018(RAM_PROTR7), and 0x 4000 501C (RAM_PROTR8).

Reset value: 0x0000 0000

Memory page protection x[31:0]:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Memory page protection x[31:16

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Memory page protection x[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits [31:0]Bit 0 in the RAM_PROTR1 protects page 0 … Bit 31 in the RAM_PROTR1 protects page 31 Bit 0 in the RAM_PROTR2 protects page 32 … Bit 31 in the RAM_PROTR2 protects page 63 Bit 0 in the RAM_PROTR3 protects page 64 … Bit 31 in the RAM_PROTR3 protects page 95 Bit 0 in the RAM_PROTR4 protects page 96 … Bit 31 in the RAM_PROTR4 protects page 127 Bit 0 in the RAM_PROTR5 protects page 128 … Bit 31 in the RAM_PROTR5 protects page 159 Bit 0 in the RAM_PROTR6 protects page 160 … Bit 31 in the RAM_PROTR6 protects page 191 Bit 0 in the RAM_PROTR7 protects page 192 … Bit 31 in the RAM_PROTR7 protects page 223 Bit 0 in the RAM_PROTR8 protects page 224 …. Bit 31 in the RAM_PROTR8 protects page 255


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Memory DMA protection register 1 (DMA_PROTR1)

Address: 0x 4000 5020 Reset value: 0x2000 0000

Offset[18:0]:

Offset[11:0]:

Reserved, must be kept at reset value

Memory DMA protection register 2 (DMA_PROTR2)



Channel[2:0]: Channel encoding

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Offset[18:3]

r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Offset[2:0] Address[11:0]Reserved

r r r r r r r r r r r r r r r

Bits [31:13]Offset in RAM

Bits [12:1]

DMA protection fault, faulting address.

Bit 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedChannel[2:0]

r r r

Bits [31:3]

Bits [2:0]

7: Not used 6: Not used 5: SC2_RX 4: Not used 3: ADC 2: Not used 1: SC1_RX 0: Not used


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Memory RAM control register (RAM_CR)



WEN: Makes all RAM writes appear as user mode


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedWEN

Reservedrw

Bits [31:3]

Bit 2

Bits [1:0]


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Memory controller (MEM) register map

Table 5 gives the MEM register map and reset values.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

.

Res

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Refer to Figure 4: STM32W108xB memory mapping, Figure 5: STM32W108CC and STM32W108CZ memory mapping, and Table 3: STM32W108xx peripheral register boundary addresses for the register boundary addresses of the peripherals available in all STM32W108xx devices.

Table 5. MEM register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x5000 RAM_PROTR1 Memory page protection 1[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x5004RAM_PROTR2 Memory page protection 2[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x5008 RAM_PROTR3 Memory page protection 3[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x500C RAM_PROTR4 Memory protection 4[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x5010 RAM_PROTR5 Memory protection 5[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x501C RAM_PROTR8 Memory protection 8[31:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x5020DMA_PROTR1 Offset[18:0] Address[11:0]

Reset value 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x5024DMA_PROTR2 Channel[2:0]

Reset value 0 0 0 0

0x5028 RAM_CR

WE

N

Reset value 0


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4.4 Memory protection unitThe STM32W108 includes the ARM® Cortex-M3 Memory Protection Unit, or MPU. The MPU controls access rights and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions. Refer to the ARM® Cortex-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU.

ST software configures the MPU in a standard configuration and application software should not modify it. The configuration is designed for optimal detection of illegal instruction or data accesses. If an illegal access is attempted, the MPU captures information about the access type, the address being accessed, and the location of the offending software. This simplifies software debugging and increases the reliability of deployed devices. As a consequence of this MPU configuration, accessing RAM and register bit-band address alias regions is not permitted, and generates a bus fault if attempted.

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Radio frequency module

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5 Radio frequency module

The radio module consists of an analog front end and digital baseband as shown in Figure 1: STM32W108 block diagram.

5.1 Receive (Rx) pathThe Rx path uses a low-IF, super-heterodyne receiver that rejects the image frequency using complex mixing and polyphase filtering. In the analog domain, the input RF signal from the antenna is first amplified and mixed down to a 4 MHz IF frequency. The mixers' output is filtered, combined, and amplified before being sampled by a 12 Msps ADC. The digitized signal is then demodulated in the digital baseband. The filtering within the Rx path improves the STM32W108's co-existence with other 2.4 GHz transceivers such as IEEE 802.15.4, IEEE 802.11g, and Bluetooth radios. The digital baseband also provides gain control of the Rx path, both to enable the reception of small and large wanted signals and to tolerate large interferers.

5.1.1 Rx baseband

The STM32W108 Rx digital baseband implements a coherent demodulator for optimal performance. The baseband demodulates the O-QPSK signal at the chip level and synchronizes with the IEEE 802.15.4-defined preamble. An automatic gain control (AGC) module adjusts the analog gain continuously every ¼ symbol until the preamble is detected. Once detected, the gain is fixed for the remainder of the packet. The baseband despreads the demodulated data into 4-bit symbols. These symbols are buffered and passed to the hardware-based MAC module for packet assembly and filtering.

In addition, the Rx baseband provides the calibration and control interface to the analog Rx modules, including the LNA, Rx baseband filter, and modulation modules. The ST RF software driver includes calibration algorithms that use this interface to reduce the effects of silicon process and temperature variation.

5.1.2 RSSI and CCA

The STM32W108 calculates the RSSI over every 8-symbol period as well as at the end of a received packet. The linear range of RSSI is specified to be at least 40 dB over temperature. At room temperature, the linear range is approximately 60 dB (-90 dBm to -30 dBm input signal).

The STM32W108 Rx baseband provides support for the IEEE 802.15.4-2003 RSSI CCA method, Clear channel reports busy medium if RSSI exceeds its threshold.

Radio frequency module STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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5.2 Transmit (Tx) pathThe STM32W108 Tx path produces an O-QPSK-modulated signal using the analog front end and digital baseband. The area- and power-efficient Tx architecture uses a two-point modulation scheme to modulate the RF signal generated by the synthesizer. The modulated RF signal is fed to the integrated PA and then out of the STM32W108.

5.2.1 Tx baseband

The STM32W108 Tx baseband in the digital domain spreads the 4-bit symbol into its IEEE 802.15.4-2003-defined 32-chip sequence. It also provides the interface for software to calibrate the Tx module to reduce silicon process, temperature, and voltage variations.

5.2.2 TX_ACTIVE and nTX_ACTIVE signals

For applications requiring an external PA, two signals are provided called TX_ACTIVE and nTX_ACTIVE. These signals are the inverse of each other. They can be used for external PA power management and RF switching logic. In transmit mode the Tx baseband drives TX_ACTIVE high, as described in Table 17: GPIO signal assignments on page 94. In receive mode the TX_ACTIVE signal is low. TX_ACTIVE is the alternate function of PC5, and nTX_ACTIVE is the alternate function of PC6. See Section 8: General-purpose input/output on page 87 for details of the alternate GPIO functions.

5.3 CalibrationThe ST RF software driver calibrates the radio using dedicated hardware resources.

5.4 Integrated MAC moduleThe STM32W108 integrates most of the IEEE 802.15.4 MAC requirements in hardware. This allows the ARM® Cortex-M3 CPU to provide greater bandwidth to application and network operations. In addition, the hardware acts as a first-line filter for unwanted packets. The STM32W108 MAC uses a DMA interface to RAM to further reduce the overall ARM® Cortex-M3 CPU interaction when transmitting or receiving packets.

When a packet is ready for transmission, the software configures the Tx MAC DMA by indicating the packet buffer RAM location. The MAC waits for the backoff period, then switches the baseband to Tx mode and performs channel assessment. When the channel is clear the MAC reads data from the RAM buffer, calculates the CRC, and provides 4-bit symbols to the baseband. When the final byte has been read and sent to the baseband, the CRC remainder is read and transmitted.

The MAC is in Rx mode most of the time. In Rx mode various format and address filters keep unwanted packets from using excessive RAM buffers, and prevent the CPU from being unnecessarily interrupted. When the reception of a packet begins, the MAC reads 4-bit symbols from the baseband and calculates the CRC. It then assembles the received data for storage in a RAM buffer. Rx MAC DMA provides direct access to RAM. Once the packet has been received additional data, which provides statistical information on the packet to the software stack, is appended to the end of the packet in the RAM buffer space.

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The primary features of the MAC are:

● CRC generation, appending, and checking

● Hardware timers and interrupts to achieve the MAC symbol timing

● Automatic preamble and SFD pre-pending on Tx packets

● Address recognition and packet filtering on Rx packets

● Automatic acknowledgement transmission

● Automatic transmission of packets from memory

● Automatic transmission after backoff time if channel is clear (CCA)

● Automatic acknowledgement checking

● Time stamping received and transmitted messages

● Attaching packet information to received packets (LQI, RSSI, gain, t

high-performance, ieee 802.15.4 wireless system-on-chip with up … · 2013. 9. 5. · datasheet...

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