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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TPEL.2014.2360172, IEEE Transactions on Power Electronics

HIGH POWER FACTOR RECTIFIER USING THE MODIFIED SEPIC

CONVERTER OPERATING IN DISCONTINUOUS CONDUCTION MODE

Carlos Gabriel Bianchin, Roger Gules, Member IEEE

Alceu Andre Badin, Member IEEE, Eduardo Félix Ribeiro Romaneli

Abstract – The theoretical and experimental analysis ofa modified version of the SEPIC DC-DC converter usedas pre-regulator operating in discontinuous conductionmode (DCM) is presented in this paper. The proposedconverter presents a low input current ripple operating inDCM and the switch voltage is lower than the outputvoltage. The switch voltage reduction increases theconverter reliability and a low drain-to-source on-resistance (RDSon) MOSFET can be used depending onthe converter specification. Moreover, a digital controltechnique is applied to the proposed converter in order toreduce the third harmonic input current distortionresultant of the operation in DCM. Finally, a 100Wprototype was developed operating with efficiency equalto 95.6%.

Index Terms: AC-DC power conversion, Rectifiers,Digital control.

I. INTRODUCTION

The usual solution for the implementation of a highpower factor (HPF) pre-regulator for a low output powerapplication (Po<200W) is to use a boost converter operatingin discontinuous conduction mode (DCM) [1]-[2]. This is asimple and cost effective solution because the design of therectifier in DCM allows the converter to operate as a voltagefollower, where the input current naturally follows the inputvoltage profile without the use of a current control loop. Theoperation in DCM reduces the commutation losses since theswitch turn-on occurs with zero-current-switching (ZCS) andthe output diode does not present reverse recovery current.This solution is limited for low power applications due to anincreased converter conduction losses operating in DCM.

Since the input inductor of the boost converter operates inDCM, a high frequency filter composed by an inductor Lfand capacitor Cf must be used in the pre-regulator input inorder to reduce the input current ripple, as presented in Fig.1.

However, a problem presented by the boost pre-regulatoroperating in DCM is the input current distortion, presenting athird harmonic component.

Manuscript received xxx x, 2014; revised xxxx , 2014; accepted xxx, 2014.Date of current version December xx,xxx. Recommended for publication byAssociate Editor xxx.C. G. Bianchin, R. Gules, E. F. R. Romaneli and A. A. Badin are with theFederal University of Technology, Curitiba, PR 80230901, Brazil.(e-mail: [email protected]; [email protected];

[email protected]; [email protected]).Digital Object Identifier xxxxxxxxxxxxxxxxxxxx

Fig. 1. Classical boost pre-regulator operating in DCM.

The voltage applied across the input inductor during itsdemagnetization is equal to the output voltage minus theinput voltage, hence, the current distortion increases whenthe difference between the output voltage and the peak inputvoltage is reduced. Therefore, the output voltage can beincreased, reducing the third harmonic input currentdistortion and improving the power factor. Also a variableduty-cycle control can be used in order to reduce the inputcurrent distortion as presented in section V. The boostconverter can operate with unitary power factorindependently of the difference between the output and inputvoltage operating at the boundary of the DCM andcontinuous conduction mode (CCM) with a variableswitching frequency modulation.

The classical SEPIC converter, shown in Fig. 2, presentsa step-up/step-down static gain and usually is used as a HPFpre-regulator in applications where the output voltage mustbe lower than the peak of the AC input voltage [3]-[4]. Theimplementation of the pre-regulator using the classicalSEPIC converter in DCM presents two additional operationcharacteristics. Firstly, the converter operates as a voltagefollower when designed in DCM with a low value for theinductor L2 and using a high value for the inductor L1, butthe input current presents a low current ripple just as a boostrectifier operating in CCM with current control loop.Consequently, the Lf-Cf filter used in the boost converterinput operating in DCM is not necessary using the SEPICconverter operating in DCM. Therefore, the number ofcomponents for both converters operating in DCM is equal.However, in a practical application, an electromagneticinterference (EMI) filter is necessary as in any rectifiertopology.

The second important characteristic using the SEPICconverter in DCM is that the input current follows the inputvoltage waveform without input current distortion. The thirdharmonic distortion is not presented because the inductor L2is demagnetized with the output voltage.

Nevertheless, the boost converter is the preferredtopology used for the pre-regulator application where theoutput voltage must be higher than the peak of the input



voltage, given that the switch voltage of the SEPIC converteris equal to the sum of the input and output voltages. TheSEPIC converter can be successfully used in applicationswhere the output voltage is lower than the input voltage.Several high-efficiency bridgeless configurations using theSEPIC and CUK converters are presented in [5]-[10].

Fig. 2. Classical SEPIC pre-regulator operating in DCM.

The modified SEPIC converter used as pre-regulatoroperating in DCM is shown in Fig.3. A modified SEPIC DC-DC converter was proposed in [11] with the inclusion of anadditional diode (DM) and capacitor (CM) at the classicalSEPIC converter, changing several characteristics such as theoperation with a switch voltage lower than the outputvoltage. However, only the operation as DC-DC converter inCCM was analyzed in [11]. This converter was also used in[12] as a pre-regulator operating in CCM presenting someadvantages when compared with the classical boost pre-regulator operating in CCM for universal line inputapplication (90Vrms - 260Vrms).

Fig. 3. Modified SEPIC pre-regulator operating in DCM.

Notwithstanding, the theoretical and experimentalanalyses of the modified SEPIC converter operating in DCMas a DC-DC converter and pre-regulator were not presentedyet, which is focus of this paper.

The proposed topology presents the same limitations ofthe classical boost converter when compared with theclassical SEPIC converter because its operation is solelypossible as a non-isolated converter with step-up static gain.Differently from the classical SEPIC converter, an auxiliaryinrush limitation circuit must be included for the rectifierstart-up. Also, the power factor is lower than the classicalSEPIC converter due to the third harmonic component in theinput current. However, the power factor and the inputcurrent distortion of the modified SEPIC converter can besignificantly improved applying a simple open loop actionusing the input and output voltage information.

The use of the boost and modified SEPIC rectifiers areonly possible in applications with an output voltage higherthan the peak of the input voltage and theses rectifiers aremore appropriated than the SEPIC converter with the same

specification, since the SEPIC converter presents a highswitch voltage.

The lowest switch voltage level is presented by themodified SEPIC topology.

The modified SEPIC converter operates as a voltagefollower and the input current presents low current ripplesuch as a classical SEPIC converter, designing the converterin DCM and using a low value for the inductor L2 and a highvalue for the inductor L1. The main converter characteristicsand analyses are presented in the following, with thetheoretical operation development of the proposed converter.

II. THEORETICAL ANALYSIS

The circuit of the pre-regulator using the modified SEPICconverter operating in DCM is presented in Fig. 3. The maindifference from the pre-regulator presented in [12] is theoperation mode and the control system that is composed byonly a voltage control loop due to the DCM operation. Also,the non-dissipative current snubber used in [12] is notnecessary because the reverse recovery current of the diodesand the turn-on switching losses operating in CCM arereduced with the DCM operation.

The modified SEPIC DC-DC converter operating inDCM presents three operation stages. The theoreticalanalysis is initially developed considering the operation as aDC-DC converter at steady state and all circuit componentsare considered ideal. The voltages across all capacitors areconsidered constant during a switching period, as an idealvoltage source. The DCM operation occurs when there is thethird operation stage, where the power switch is turned-offand the currents in all diodes of the circuit are null.Therefore, the DCM operation occurs when Do and DMdiodes are blocked before the switch turn-on.

The analysis and design procedure is also developed forthe operation as a pre-regulator with a diode bridge at inputand an AC input voltage, based on the study as DC-DCconverter.

The circuit presents two inductors, thus, differentinductor values combination can be adopted for the DCMoperation. In order to reduce the input current ripple of thepre-regulator, a relative high value for the inductor L1 isconsidered. A relative low value of the inductor L2 is usedfor the converter operation in DCM as a voltage follower,where the input current follows the input voltage waveform.As a result, the pre-regulator input current follows the inputvoltage waveform with low current ripple, without inputfilter and without current control loop.

An important equation for the operation analysis of theconverter is presented in (1).

Considering the operation at steady state, the averagevoltage across the inductors L1 and L2 are null and the sum ofthe input voltage Vi and capacitor CS voltage is equal to thecapacitor CM voltage.

The operation stages in DCM are presented as follows:

CSiCM VVV (1)



1) First Stage [t0 - t1] (Fig. 4) – During the conduction ofthe power switch S, the input inductor stores energy with theinput voltage applied across L1 (VL1). The voltage appliedacross L2 (VL2) is equal to the voltage of capacitor CM minusthe voltage of capacitor CS. As presented in (1), this voltagedifference is equal to the input voltage. Therefore, inductorsL1 and L2 store energy in this operation stage and the samevoltage is applied across these inductors. The currentsthrough inductors L1 and L2 increase following (3) and (4)respectively, but since L2 is lower than L1, the currentvariation in L2 is higher than in L1, as presented in thetheoretical waveforms shown in Fig.7. The diodes DM and Doare blocked during this operation stage.

Fig. 4. First operation stage.

i2L1L VVV (2)

fLDVi

1

i1L

(3)

fLDVi

2

i2L

(4)

Where f is the switching frequency and D is the converterduty-cycle.

2) Second Stage [t1 – t2] (Fig. 5) – At the instant t1, switchS is turned-off and the energy stored in the input inductor L1is transferred to the output through the CS capacitor andoutput diode Do. There is also energy transference to CMcapacitor through diode DM and the maximum switch voltageis equal to the CM capacitor voltage. The energy stored ininductor L2 is also transferred to the output and capacitor CSthrough diodes Do and DM. The voltage applied across L1 isequal to CM capacitor voltage minus the input voltage andthis difference is equal to the CS capacitor voltage ascalculated by (1). The voltage across the inductor L2 is equalto the negative capacitor CS voltage. Thus, the voltageapplied across the inductor L1 and L2 are equal to thenegative capacitor CS voltage during this operation stage andthe inductor current variation is calculated by (6) and (7)respectively.

As presented in Fig. 7, the time interval (t2-t1) of thesecond operation stage is defined as td and is equal to thetransference period of the energy stored in inductors L1 andL2 through diodes Do and DM. When L2 current valuebecomes equal to L1 current value with the same direction,the currents at diodes Do and DM becomes null, finishing thisoperation stage. Therefore, td is the conduction time ofdiodes DM and Do, when the energy stored in the inductors L1and L2 is transferred.

Fig. 5. Second operation stage.

CS2L1L VVV (5)

fLDV

i1

tdCS1L

(6)

f2LDV

i tdCS2L

(7)

Where:

ftTtD dd

td (8)

3) Third Stage [t3 – t4] (Fig. 6) – When diodes Do and DMare blocked at the instant t3, the voltage applied across theinductors L1 and L2 are null, maintaining the inductorscurrents constant as presented in (9) and (10). The currentsthrough the inductors L1 and L2 present the same value,operating as a freewheeling stage. This operation stage isfinished when the power switch is turned-on at the instant t4,returning to the first operation stage.

Fig. 6. Third operation stage.

0VV 2L1L (9)0ii 2L1L (10)

The main theoretical waveforms are presented in Fig. 7.The switch turn-on occurs with ZCS such as a classical DC-DC converter operating in DCM and the diodes do notpresent reverse recovery current. The maximum switchvoltage is equal to the capacitor CM voltage and this voltageis lower than the output voltage. The L1 inductor averagecurrent is equal to the input current and the L2 inductoraverage current is equal to the output current. The averagecurrent in the capacitors CS and CM are null at steady state,thus, the average current of diodes DM and Do are equal tothe output current.

III. MATHEMATICAL ANALYSIS OPERATING AS ADC-DC CONVERTER

The main equations of the modified SEPIC converter,operating in DCM as a DC-DC converter with constant inputvoltage Vi, are presented. Subsequently, a design procedure



operating as pre-regulator with AC input voltage is presentedbased on the established equations.

Fig. 7. Main theoretical waveforms.

A. Converter static gain and the capacitors CS and CMvoltages

The output voltage is equal to the sum of the CS and CMcapacitors voltages, as observed at the second operation stagepresented in Fig. 5 and the CM voltage is calculated by (11).

CSoCM VVV (11)

Replacing (1) in (11), the voltage across the capacitor CSis obtained and presented in (12).

2

VVV io

CS

(12)

Replacing (1) in (12), the voltage across the capacitor CMis obtained and presented in (13).

2

VVV io

CM

(13)

The maximum switch voltage for the classical SEPICconverter is equal to the sum of the input and outputvoltages, while the switch voltage is equal to the outputvoltage for the boost converter. The maximum switchvoltage of the modified SEPIC converter is equal to thevoltage across the CM capacitor calculated by (13). Thevoltage obtained from (13) for the modified SEPIC converteris always lower than the switch voltage of the classical boostand SEPIC converters because the input voltage is always

lower than the output voltage in the modified SEPICconverter.

Considering the operation at steady state and the averagevoltage across the inductors as equal to zero, the theoreticalwaveforms presented in Fig. 7shows that the positive area ofthe inductor voltage must be equal to the negative area aspresented in (14) for the inductor L1. The converter duty-cycle is equal to D and Dtd is the ratio between the diodes DMand Do conduction period td and the switching period T, aspresented in (8).

TDVVTDV tdiCMi (14)

The voltage across the CM capacitor is obtained from(14).

tdi

CMDD1

VV

(15)

Replacing (13) in (15), the converter static gain isobtained.

tdi

oD

D21VV

(16)

The CS capacitor voltage is obtained from (12) and (16).

tdi

CSDD

VV

(17)

The conduction period of the diodes td and the parameterDtd must be calculated for the static gain determination. Aspresented in Fig. 7, the currents at the diodes DM and Do areequal and the average value is equal to the output current Io.The current Io can be calculated by (18), where IDpk is thepeak value of the current conducted by the diodes DM andDo.

2I

I tdDDpko

(18)

The peak current at the output diode is equal to half of thesum of the inductors L1 and L2 current ripple, as calculatedby (19).

2I 2L1LDpk

(19)

Replacing (3) and (4) in (19), the output diode peakcurrent is equal to:

fLDV

fLDV

21I

2

i

1

iDpk

(20)

Therefore:

fL2DVI

eq

iDpk

(21)

Where:

21

21eq LL

LLL

(22)

Replacing (21) in (18), the conduction period of the outputdiode is obtained as presented in (23).



DVfLI4

Di

eqotd

(23)

Considering:

i

eqo

VfLI4

K

(24)

The conduction period of the output diode is equal to (25).

DKD td

(25)

Hence, the static gain and the voltage across the capacitorsCM and CS are calculated by (26), (27) and (28).

KD21

VV 2

i

o

(26)

KD1

VV 2

i

CM (27)

KD

VV 2

i

CS (28)

B. Limit for the DCM operationThe design procedure of the converter must ensure the

operation only in DCM for any line voltage angle and in alloperation conditions in order to maintain the high powerfactor operation. The operation in CCM without currentcontrol loop results in input current distortion increasing thetotal harmonic distortion (THD).

The conduction period of the power switch is representedby the interval (t1-t0) in Fig. 7 and also by the converter duty-cycle (D.T). The conduction period of the output diode isdefined by the interval (t2-t1) and by the parameter (Dtd.T).The limit for the DCM operation occurs when the sum of theswitch conduction period and the diode conduction period isequal to the switching period (T), as presented in (29).

1DD td (29)

Replacing the parameter Dtd form (17) in (29), themaximum duty-cycle for the DCM operation is obtained andpresented in (30).

iCS

CSVV

VD

(30)

Also, considering the voltage across the capacitor CScalculated by (12) and replacing in (30) the maximum switchduty-cycle as a function of the input and output voltage isobtained.

io

ioVVVV

D

(31)

As presented in [11], the static gain of the modifiedSEPIC converter operating in CCM (qCCM) is calculated by(32).

D1D1

VV

qi

oCCM

(32)

The duty-cycle obtained from (32) is equal to the valuecalculated by (31) because at the boundary of the conductionmodes, the static gain obtained with the converter operatingin DCM presents the same value obtained with the CCMequation.

The value of the equivalent inductance (Leqcrit) for theboundary of CCM and DCM operation is obtained replacing(23) in (29) and is presented in (33) using the duty-cyclecalculated by (31). This inductance can also be calculated by(34) as a function of the input and output voltage, replacing(31) in (33).

o

ieqcrit If4

VDD1L

(33)

o

2io

2iio

eqcritIf2VV

VVVL

(34)

IV. DESIGN PROCEDURE OF THE PRE-REGULATOR

Considering the mathematical analysis developed, adesign example of the pre-regulator proposed is presentedconsidering the specification in Table I.

TABLE IDesign specifications

Parameter Pre-regulator with modifiedSEPIC converter

Nominal input voltage (Virms) Virms = 127 VPeak value of input voltage (Vpk) Vpk = 180 V

Output voltage (Vo) Vo = 400 VOutput power (Po) Po = 100 W

Switching frequency (f) 30 kHzLine frequency (fL) fL = 60Hz

Maximum input current ripple ∆iL=26% of the inputpeak current

The pre-regulator input voltage is presented in (35). Sincethe third harmonic distortion at the pre-regulator input isrelatively low with a RMS input voltage equal to 127V andan output voltage equal to 400 V, some results are alsopresented with a RMS input voltage equal to 220V.

tsinVtV pki (35)

A. Limit of the DCM operation and the nominal duty-cycle

The maximum duty-cycle for the DCM operation iscalculated by (31). The peak value of the AC input voltagemust be considered in the equation of the maximum duty-cycle.

379.0180400180400

VVVV

Dpko

pko

(36)

Therefore, a duty-cycle equal to D=0.337 is used for theconverter operation at the nominal input voltage.

B. Inductors L1 and L2The input inductance L1 is calculated by (3) with the

specification of the maximum input current ripple (∆iL). The



peak of the input current (Iinpk) is calculated by (37) andconsidering the input current ripple ∆ iL presented in Table Iand a theoretical efficiency equal to 96%, the input inductorcan be calculated by (39).

A157.1212796.0

1002VPI

irms

oinpk

(37)

A3.026.0I inpkiL (38)

Therefore, the input inductance L1 obtained from (3) isequal to:

mH72.610303.0

337.0180fDV

L 3iL

pk1

(39)

An input inductance equal to L1=6.8mH was used in theprototype.

Considering the operation as a rectifier, the average valueof the output diode current (Io(ωt)) calculated in eachswitching period, changes with the AC input voltage and iscalculated by (40), obtained from (23).

fL4

tDDtsinVtI

eq

tdpko

(40)

Replacing the parameter Dtd(ωt) by (17) and (12), theaverage value of the output diode current is calculated by(41).

tsinVVfL2

DtsinVtI

pkoeq

2pk

o

(41)

The DC load current (Io), after the output filter capacitor,is equal the average value of Io(ωt) presented in (42).

td

tsin1tsin

fL2DV

tdtI1I0

2

eq

2pk

0oo

(42)

Where:

45.0400180

VV

o

pk (43)

Solving the integral presented in (42), the DC loadcurrent is equal to (44).

ieq

2pk

o KfL2

DVI

(44)

Where:

159.11

tan21

22K2

1

2i

(45)

Therefore, the equivalent inductance Leq is calculated by(46) and the inductor L2 is calculated by (47).

H28.500159.1

40010010302

337.0180K

VP

f2

DVL

3

2

i

o

o

2pk

eq

(46)

H4.5431028.500108.61028.500108.6

LLLL

L 63

63

eq1

eq12

(47)

A L2 inductance equal to 540 µH was used in theprototype.

C. Capacitors CS and CMThe voltages across the capacitors CS and CM calculated

by (12) and (13) change with the AC input voltage and arepresented in Fig. 8, considering the voltage ripple across thecapacitors null. The voltage across the CS and CM capacitorsare equal to 110 V and 290 V, respectively, at the peak of theinput voltage. The switch voltage is equal to the CM capacitorvoltage and lower than the output voltage.

In the classical SEPIC and in the modified SEPICconverters, the theoretical capacitors voltage are consideredconstant in a switching period. However, as presented in Fig.8, the capacitors voltages follow the line voltage variation inthe operation as pre-regulator. Therefore, the values of thecapacitors must be high enough to be considered a voltagesource during a switching period, but not too large in order tofollow the line input voltage variation without distortion inthe pre-regulator input current. In order to comply with theserequirements, a design methodology considering theconverter resonance frequency is presented in [3].

The converter resonant frequency must be considerablygreater than the line frequency to avoid input currentoscillations at every line half cycle. Also, the converterresonant frequency must be lower than the switchingfrequency to assure almost constant voltage in a switchingperiod.

Considering a converter resonance frequency equal to fR=5.5 kHz and the same value for the capacitors CS and CM, thecapacitor value is calculated by (48).

Fig. 8. Capacitors CS and CM voltages operating as pre-regulator.


A157.1212796.0

1002VPI

irms

oinpk

(37)

A3.026.0I inpkiL (38)


mH72.610303.0

337.0180fDV

L 3iL

pk1

(39)



fL4

tDDtsinVtI

eq

tdpko

(40)


tsinVVfL2

DtsinVtI

pkoeq

2pk

o

(41)


td

tsin1tsin

fL2DV

tdtI1I0

2

eq

2pk

0oo

(42)

Where:

45.0400180

VV

o

pk (43)


ieq

2pk

o KfL2

DVI

(44)

Where:

159.11

tan21

22K2

1

2i

(45)


H28.500159.1

40010010302

337.0180K

VP

f2

DVL

3

2

i

o

o

2pk

eq

(46)

H4.5431028.500108.61028.500108.6

LLLL

L 63

63

eq1

eq12

(47)









A157.1212796.0

1002VPI

irms

oinpk

(37)

A3.026.0I inpkiL (38)


mH72.610303.0

337.0180fDV

L 3iL

pk1

(39)



fL4

tDDtsinVtI

eq

tdpko

(40)


tsinVVfL2

DtsinVtI

pkoeq

2pk

o

(41)


td

tsin1tsin

fL2DV

tdtI1I0

2

eq

2pk

0oo

(42)

Where:

45.0400180

VV

o

pk (43)


ieq

2pk

o KfL2

DVI

(44)

Where:

159.11

tan21

22K2

1

2i

(45)


H28.500159.1

40010010302

337.0180K

VP

f2

DVL

3

2

i

o

o

2pk

eq

(46)

H4.5431028.500108.61028.500108.6

LLLL

L 63

63

eq1

eq12

(47)










nF2.228

1054.0108.6105.52

2LLf2

2CC

3323

212

RMS

(48)

A capacitance equal to CS= CM =220 nF was used in theprototype.

The RMS current through CM and CS capacitors arecalculated considering that the minimum current during eachswitching period at the L1 inductance Iimin(ωt) (49). Theparameter Dtd (ωt) and the output diode maximum currentIDpk(ωt) (50) are modulated by the sinusoidal input voltage Vi(ωt). The number of commutations during one semi-cycle ofline voltage can be calculated by (51).

tsinL2DV

VP

9.02tI

1

i

i

omini

(49)

tsintD

I29.02tI

td

oDpk

(50)

Tf21nL

(51)

Where fL is the line frequency and T is the high frequencyswitching period.

The RMS capacitor current value at each switching cyclecan be calculated by (52), considering the parameter (i)changing from 1 to n.

T

Tn

iDtdD

Tn

iDtdD

TD

2TD

0

2CM dtCdtBdtA

T1iI

rms

(52)Where:

tL

niV

niIA

2

i

mini

(53)

Tn

iD

TDtn

iIfL

niV

niIt

fL

Dn

iV

niIB

td

Dpk2

i

Dpk2

i

mini

(54)

niIC mini (55)

Thereby, the total RMS currents through capacitor CMand CS are calculated by (56).

A824.0iIn1II

n

1i

2CMCSCM rmsrmsrms

(56)

D. Semiconductors stressThe maximum voltage in all semiconductors is equal to

the CM capacitor voltage and the average current of thediodes DM and Do is equal to the average output current Io.

The average and RMS switch current are calculated by(57) and (58) respectively.

A431.0105001030

337.0180LfDV

Is 63

2

eq

2pk

avg

(57)

A953.06

337.0105001030

1806

DLf

VIs

3

63

3

eq

pkrms

(58)

E. Comparison at the boundary of the CCM and DCMoperation

Table II presents some parameters calculated consideringthe operation at the boundary of the CCM and DCM at thepeak of the input voltage and considering the nominalspecifications presented in Table I, in order to compare thethree topologies.

The modified SEPIC converter presents the lowest duty-cycle due to the highest static gain. The input current rippleequation for the SEPIC and modified SEPIC converter arethe same (39), so the input inductor of the modified SEPICconverter is lower than the input inductor of the SEPICconverter because the duty-cycle of the modified SEPICconverter is close to half of the duty-cycle of the SEPICconverter. Also, the equivalent inductance of the modifiedSEPIC converter for the boundary operation and for the sameoperation point in DCM is lower than in the otherstopologies.

TABLE IIPre-regulator parameters designed at the boundary of CCM

and DCMboost SEPIC Modified SEPIC

Duty-cycle D

55.0DV

VVD

o

pko

689.0D

VVVD

pko

o

379.0D

VVVV

Dpko

pko

Inductance for the boundary operation

H1485L

90If2VDD1

L

crit

o

pkcrit

H1286L90If2

VDD1L

eqcrit

o

pkeqcrit

H706L90If4

VDD1L

eqcrit

o

pkeqcrit

Switch voltage

V400VsVVs

max

omax

V580Vs

VVVs

max

pkomax

V290Vs2VV

Vs

max

pkomax

Switch peak current at the peak of the input voltage

A2.290isfLDV

90is

pk

crit

pkpk

A21.390is

fLDV

90is

pk

eqcrit

pkpk

A21.390is

fLDV

90is

pk

eqcrit

pkpk



The modified SEPIC converter presents the lowest switchvoltage. The boost converter presents the lowest switch peakcurrent and the SEPIC and modified SEPIC converterspresent the same peak current but with a lowest switchconduction time for the modified SEPIC converter.

V. THIRD HARMONIC REDUCTION TECHNIQUE

The classical boost rectifier operating in DCM and themodified SEPIC rectifier present a third harmonic distortionin the input current. This current distortion is a function ofthe voltage difference between the input and output voltage.Normally, the output voltage is increased in order to reducethe third harmonic distortion and to maintain high powerfactor, but the semiconductors losses are increased.

In order to reduce the third harmonic distortion withoutincreasing the output voltage, an open loop control action forthe classical boost converter with analog implementation waspresented in [13]. Only the information of the input andoutput voltage are necessary to define a duty-cycle variationin a line voltage half period, reducing the third harmonicdistortion even for a relative low output voltage.

The same open loop technique is developed in this paperfor the modified SEPIC converter using a digitalimplementation, obtaining high power factor.

Considering by simplification that the converter operateswithout losses, the input power is equal to the output power.

)t(IV)tsin(I)tsin(VtPtP ooipkpkoi

(59)Replacing (16) and (41) in (59), the instantaneous input

power is calculated by (60).

fL4tDDtsinV

tDD2tsinV

tsinV)tsin(I)tsin(V

eq

tdpk

td

pkpkipkpk

(60)The pre-regulator input current is calculated by (61)

obtained from (60).

DD2tDfL4

tsinV)tsin(I td

eq

pkipk

(61)

Therefore, the pre-regulator input current will besinusoidal if the term Kc presented in (62) is constant.

DD2tDK tdc (62)The converter duty-cycle must be changed in a half cycle

of the AC input voltage in order to maintain (62) constant,since the parameter Dtd(ωt) changes with the input voltage.Replacing the parameter Dtd calculated by (17) and the VCSvoltage calculated by (12) in (62), the duty-cycle variation isobtained and presented in (63), in order to maintain (62)constant.

o

pkcV

tsinV1

2KtD

(63)

Therefore, the third harmonic distortion can be reducedsolving (63) requiring solely the measurement of the inputand output voltages. The output voltage can be replaced bythe output voltage reference in (63), considering theoperation at steady state.

The peak of the pre-regulator input current Iipk ispresented in (64).

A111.1KcfL4

VV

P2I

eq

pk

pk

oipk

(64)

The parameter Kc can be calculated by (65).

372.0180

10301028.5001008K

V

fLP8K

2

36

c

2pk

eqoc

(65)

The parameter Kc should be calculated at each half cycleof the AC input voltage because this parameter is a functionof the peak of the input voltage Vpk and also changes with theoutput current. However, a constant value for the parameterKc can be used considering the nominal specifications andthe duty-cycle variation calculated by (63) can be multipliedby the output voltage control loop. The pre-regulator duty-cycle obtained by multiplying the output voltage control loopand the value calculated by (63) with constant value for theparameter Kc, regulates the output voltage and allows thereduction of the third harmonic distortion with the correctgain.

The variation of the main rectifier parameters with theinput voltage as the duty-cycle, conduction period of theoutput diode, input current and the average value of theoutput diode current are presented for the operation with andwithout the third harmonic reduction technique.

The duty-cycle variation calculated by (63), consideringthe nominal values presented in Table I and the componentscalculated at the design procedure, is shown in Fig. 9.

Fig. 9. Duty-cycle variation in a half line period with and withoutthe reduction of the third harmonic distortion.



The output diode conduction period Dtd, considering theoperation with a constant duty-cycle and with the variableduty-cycle calculated by (63), are presented in Fig. 10.

Changing the pre-regulator duty-cycle D as calculated by(63), the output diode conduction period Dtd calculated by(17) also changes. Replacing these two parameters in theinput current equation (61), the theoretical input currentwaveform is obtained, considering the inductor current ripplenull. Figure 11 presents the pre-regulator theoretical inputcurrent waveform operating with and without the thirdharmonic reduction technique. The theoretical input currentwaveform is improved mainly for pre-regulator operationwith the highest value of the input voltage (220 V), where thethird harmonic distortion is more expressive.

The average value of the output diode current is presentedin Fig. 12.

Fig. 10. Output diode conduction period Dtd operating with constantduty-cycle and with a variable duty-cycle with third harmonic

reduction.

Fig. 11. Pre-regulator theoretical input current waveform with andwithout the third harmonic reduction.

The theoretical waveform of the output diode averagecurrent is equal for the operation with input voltage equal to127 V and 220V with the third harmonic reductiontechnique.

Fig. 12. Output diode average current Io(ωt) and the DC outputcurrent (Io) waveforms with and without the third harmonic

reduction.

The theoretical rectifier power factor (FP) and the inputcurrent total harmonic distortion (THDi) can be calculated by(67) and (68) respectively from the theoretical input currentwaveform presented in Fig. 11, considering the input currentRMS value (66). Results with the input voltage equal to 127V and 220 V are summarized in Table III.

0

2

tdeq

pkirms tdtDtD2tD

fL4

tsinV1I

(66)

irmsirms

o

IVP

FP

(67)

1FP

1100%THD 2i (68)

TABLE IIITheoretical power factor and total harmonic current

distortionInput voltage 127 V 220V

Control

Withthird

harmonicreduction

Withoutthird

harmonicreduction

Withthird

harmonicreduction

Withoutthird

harmonicreduction

Iirms 0.786 A 0.79 A 0.455 A 0.474 AFP 1 0.996 1 0.959

THDi 0 % 8.845 % 0 % 29.65 %



VI. OUTPUT VOLTAGE CONTROL SYSTEM

A. Control-to-output transfer function (vo(s)/d(s))A dynamic model of switching converter is required for

feedback control loop. However, the power converters aredescribed by a set of the nonlinear differential equations.Usually is easier to analyze a small-signals model that islinearized related to the quiescent operation point in order toobtain a linear model, as presented in [15].

The small signal equivalent circuit of buck, boost andbuck-boost converters presents a capacitor and inductor,operating in DCM. The transfer functions have two poles.One pole is due to the output capacitor, at low frequency, andother pole, in much higher frequency due to the inductor.For this reason, an approximate way to determine the lowfrequency small-signal transfer function of the basicsconverters is to let the inductance tend to zero [15].

Also, the capacitor CM and CS are very small in themodified SEPIC converter, where Co>>CM and Co>>CS.Therefore, they can be neglected to obtain control-to-outputtransfer function for low frequency. In this case, the highfrequency capacitors dynamics can be ignored. The modifiedSEPIC without CM, CS and L1 is shown in Fig. 13(a) and theequivalent circuit is shown in Fig. 13(b). The remainingmodel is solved for the low-frequency converter dynamics.

Fig. 13. Simplified circuit model of modified SEPIC DC-DC: (a)with neglected components, (b) equivalent circuit.

To perform this analysis, the model of the PWM switchin DCM proposed in [16] is used considering the equivalentcircuit presented in Fig. 13(b). The equivalent circuit of anaverage model and small-signal model of PWM switch inDCM is shown in Fig 14.

Transfer function is obtained considering a resistive load.The model of the PWM switch in DCM is replaced in themodified SEPIC converter and the input voltage is shortened.Figure 15 shows the equivalents circuits.

Fig. 14. Model of PWM switch in DCM: (a) Average model(b) Small-signal model.

Where:

ac

ai V

Ig

(69)

DI2

k ai

(70)

DI2

k po

(71)

cp

po V

Ig (72)

ac

pf V

I2g

(73)

Fig. 15. Small-signal equivalent circuit for control-to-outputtransfer function of modified SEPIC: (a) complete circuit (b)

simplified circuit.

The control-to-output transfer functions of the convertercan be obtained applying circuit analysis in circuit of Fig.15(a) and the transfer function is presented in (74).

2

o2ooo2oooo

ooo

SgLRCSgLRCgR1

KRSdSV

(74)The small-signal parameters are evaluated at the

operating point, where Ip=Io and Vcp=Vo, as follows:

DI2k o

o

(75)

o

oo V

Ig (76)

Figure 16 shows the dynamic behavior of the outputvoltage waveform under duty-cycle disturbances consideringthe operation as a DC-DC converter. At 0.5 s, a 1% step isapplied in the duty-cycle. At 1.1s, the duty-cycle returns toits nominal value. The results show good resemblancebetween the proposed model and the simulation of theconverter power circuit. The dynamic response of theproposed converter operating in DCM is an overdampedsecond order system with a step response similar to a firstorder system.

The modified SEPIC rectifier presents an oscillating inputvoltage with double line frequency. On the other hand, alarge output capacitor is used to minimize the output voltageripple. Thus, output voltage does not change significantly ina half-line period and a simplified model can be consideredwithout the input ripple.

The simulation result of the modified SEPIC operating asa rectifier and the prediction of the small signal model for astep change in the duty-cycle are shown in Fig. 17.

It can be observed that this model gives good results atlow frequencies. It cannot accurately predict high frequencydynamics because CM, CS and L1are neglected. However, the



output voltage feedback loop in the conventional rectifiercontrol system must have a low-bandwidth in order to avoiddistortions in the input current waveform. The controllershould have sufficiently small loop gain at the evenharmonics of the AC line frequency. Therefore, low-frequency small-signal transfer function is appropriate for thecontrol of the modified SEPIC rectifier.

Fig. 16. Comparison of the transient responses of output voltage fora 1% disturbance in the duty-cycle for the modified SEPIC

operating as a DC-DC converter in DCM.

Fig. 17. Comparison of the transient responses of output voltage fora 2% disturbance in the duty-cycle for the modified SEPIC

operating as a rectifier in DCM.

B. Control SystemThe pre-regulator operation in DCM allows obtaining

high power factor without a current control loop and only avoltage control loop is necessary [14]. The output voltagecontrol algorithm used in the proposed converter is based onthe classical PI controller. The design procedure can besimplified using a design procedure similar to the classicalboost converter. Also, the 120 Hz ripple of the pre-regulatoroutput voltage must be rejected by the voltage control loop inorder to maintain the high power factor operation. Therefore,the voltage control loop presents a very slow dynamicresponse such as any classical pre-regulators.

The block diagram of the digital control implementationis presented in Fig. 18, including the third harmonicreduction technique. Only the output and input voltages arenecessary to control the pre-regulator. The control algorithmwas developed using a digital signal processor

TMS320F2812, operating with sampling rate equal to 30kHz. The sampled output voltage signal is compared to anoutput voltage reference and the error is applied to a PIvoltage controller. Simultaneously, the sampled rectifiedinput voltage and the output voltage reference are applied to(63) in order to calculate the duty-cycle variation for the thirdharmonic reduction. The result of the PI output voltagecontroller and the result of the third harmonic reduction aremultiplied obtaining the pre-regulator duty-cycle andgenerating the PWM signal that controls the switch S.

Fig. 18. Block diagram of the pre-regulator control system.

VII. EXPERIMENTAL RESULTS

The proposed pre-regulator was implemented aspresented in Fig.18 using the specifications presented inTable I and the components used are shown in Table IV. Thepre-regulator performance is compared with and without theimplementation of the third harmonic reduction technique.The waveforms were obtained with nominal output powerand input voltage equal to 127 Vrms and 220 Vrms.

The pre-regulator input current and voltage waveforms,operating with Vi = 127 Vrms and without the third harmonicdistortion reduction technique are presented in Fig. 19.

TABLE IVPre-regulator components

Parameter Pre-regulator with modifiedSEPIC converter

Inductor L1L1 = 6.8 mH

ESR=692 mΩ

Inductor L2L2 = 540 µHESR=98 mΩ

Capacitor CSCS=220 nF

ESR=10 mΩ

Capacitor CMCM=220 nF

ESR=10 mΩ

Output capacitor CoCo=120 F

ESR=390 mΩ

Diodes DM -DoDM=Do=UF5408

Vf=1.7 V

Power switch SS=FQA28N50VDSS=500 V

RDSon=0.16 Ω (25ºC)



The total input current harmonic distortion is equal to13% without the application of the third harmonic reductiontechnique and the pre-regulator power factor is equal to0.993. The total input voltage harmonic distortion is equal to3.1%.

Fig. 19. Input voltage and current operating with Vi=127 Vrms andwithout the third harmonic reduction technique (CH1 - Input

voltage - 100 V/div, CH3 - L1 current – 0.5 A/div, CH4 - Inputcurrent – 0.5 A/div).

The pre-regulator input current and voltage waveforms,operating with Vi = 127 Vrms and with the third harmonicdistortion reduction technique are presented in Fig. 20. Thetotal input current harmonic distortion is reduced to 5.3%with the application of the third harmonic reductiontechnique and the pre-regulator power factor is increased to0.999. Considering that the total voltage harmonic distortionis equal to 3.1%, the total input current distortion is 2.2%higher than the total input voltage distortion.

The pre-regulator input current and voltage waveforms,operating with Vi = 220 Vrms and without the third harmonicdistortion reduction technique are presented in Fig. 21.Reducing the voltage difference between the peak of theinput voltage and the output voltage, the third harmonicdistortion increases, operating with constant duty-cycle.

The total input current harmonic distortion is equal to35.9% without the application of the third harmonicreduction technique and the pre-regulator power factor isreduced to 0.951.

Fig. 20. Input voltage and current operating with Vi=127 Vrms andwith the third harmonic reduction technique (CH1 - Input voltage -100 V/div, CH3 - L1 current – 0.5 A/div, CH4 - Input current – 0.5

A/div).

Fig. 21. Input voltage and current operating with Vi=220 Vrms andwithout the third harmonic reduction technique (CH1 - Input

voltage - 100 V/div, CH3 - L1 current – 0.5 A/div, CH4 - Inputcurrent – 0.5 A/div).

The pre-regulator input current and voltage waveforms,operating with Vi = 220 Vrms and with the third harmonicdistortion reduction technique are presented in Fig. 22.

Fig. 22. Input voltage and current operating with Vi=220 Vrms andwith the third harmonic reduction technique (CH1 - Input voltage -100 V/div, CH3 - L1 current – 0.5 A/div, CH4 - Input current – 0.5

A/div).

The total input current harmonic distortion is reducedfrom 35.9% to 8.84% with the application of the thirdharmonic reduction technique and the pre-regulator powerfactor is increased from 0.951 to 0.988. The total inputcurrent distortion is 5.74% higher than the total input voltagedistortion.

The pre-regulator operation with nominal output powerand input voltage equal to Vi=127 Vrms are presented fromFig. 23 to Fig. 30, considering the operation with the thirdharmonic reduction technique.

The L1 and L2 currents are presented in Fig. 23 and itscurrent ripple is close to the theoretical values 0.3 A and 3.56A respectively.

The CS and CM capacitor voltages are presented in Fig.24. The theoretical value of the CS and CM capacitor voltagesat the peak of the input voltage, considering the capacitorvoltage ripple null, is equal to 110 V and 290 V respectively.

The switch voltage and current are presented in Figs 25and 26. The maximum switch voltage is close to 300V for aninput voltage equal 127 Vrms and output voltage equal to 400V.



The currents in the diodes DM and Do are presented inFig. 27. The theoretical diode peak current is equal to 2 Aand the theoretical value of the diode conduction period isequal to td=17.45 µs at the peak of the input voltage.

Fig. 23. L1 and L2 currents (CH3 – L1 current - 0.5 A/div, CH4 – L2current – 1 A/div).

Fig. 24. CS and CM capacitor voltages (CH1 – CS voltage - 100V/div, CH2 – CM voltage – 100 V/div).

Fig. 25. Switch voltage and current (CH2 – Switch voltage - 100V/div, CH4 – Switch current – 2 A/div, 2.5ms/div).

Fig. 26. Switch voltage and current (CH2 – Switch voltage - 100V/div, CH4 – Switch current – 2 A/div, 10s/div).

Fig. 27. Currents in the diodes DM and Do (CH3 – DM current - 1A/div, CH4 – Do current – 1 A/div).

(a)

(b)Fig. 28. PWM modulation signal (a) Vi=127 V and (b) Vi=220V.



The PWM modulation signal obtained from the productof the voltage control loop and the third harmonic reductiontechnique, as presented in Fig. 18, was applied to a digital toanalog converter of the digital controller and is presented inFig. 28 operating with Vi=127 Vrms and Vi=220 Vrms. Thevoltage variation from 0 to 1 V corresponds to the duty-cyclevariation from 0 to 1. The modulation signal obtained fromthe prototype is similar to the theoretical result presented inFig.9.

The dynamic response of the pre-regulator is presented inFigs. 29 and 30 for Vi = 127 Vrms. Figure 29 shows thedynamic response of the converter during the load changefrom 100% to 30% and Fig. 30 presents the load transientfrom 30% to 100%.

The theoretical efficiency of the proposed converteroperating with a RMS input voltage equal 127 V hasbeen estimated considering the component parameters usedin the prototype shown in Table IV.

Considering the RMS switch current calculated by (58)and the RDSon MOSFET with resistance equal 240 mΩ(at 80ºC), the switch conduction loss is equal to 0.22 W.The average current in the DM and Do diodes are equal to theoutput current and considering the diode UF5408 (3A-800 V)used in the prototype with a diode forward voltage equal to1.7 V, the DM and Do diodes total conduction losses is equalto 0.85 W.

Fig. 29. Load change from 100% to 30% (CH2 – Output voltage -100 V/div, CH4 – Input current - 1 A/div, 250 ms/div).

Fig. 30. Load change from 30% to 100% (CH2 – Output voltage -100 V/div, CH4 – Input current - 1 A/div, 250 ms/div).

The average current in the input bridge diodes is equal to0.37 A and the total conduction losses of input diodebridge is equal to 2.52 W. Therefore, the estimatedtheoretical efficiency of the proposed converter is equal to

95.6% considering the total losses of the inductors equal to 1W. The classical boost converter presents similar losses in allcomponents. However, there is only one diode in theconverter output, reducing the diode conduction losses in0.42 W for the boost prototype in comparison to theproposed converter prototype, resulting in a theoreticalefficiency equal to 96%.

The same diode (UF5408) was used in the experimentalprototypes of the boost and the modified SEPIC converters.However, since the maximum voltage in the diodes DM andDo is always lower than the output voltage (Vo=400V), thediode UF5404 (3A- 400V) with a diode forward voltageequal to 1.0 V, as presented in the diode manufacturercatalog (Vishay), could be used in the proposed converterprototype.

Consequently, using the diode 1N5408 in the classicalboost converter, the output diode conduction losses is equalto 0.425 W and using the diode 1N5404 in the proposedconverter as the diodes DM and Do, the total diode conductionlosses will be reduced from 0.85 W to 0.5 W. Also a lowerRDSon MOSFET could be used in the proposed converterdue to the lower switch voltage.

The experimental efficiency of the proposed converteroperating with Vi=127 Vrms and Vi=220 Vrms are shown inFigs. 31 and 32 respectively, measured with the digital powermeter Yokogawa WT230. The prototype configuration wasalso changed to the classical boost rectifier presented in Fig.1 using the same semiconductors of the proposed converter.The efficiency curve of the boost converter is presentedconsidering an operation point similar to the proposedconverter using an inductance equal to 1.1 mH.

The efficiency of the proposed converter operating withoutput power equal to 108 W and Vi=127 Vrms is equal to95.6%, while for the boost converter is equal to 95.2%.

The efficiency of the proposed converter was measuredalso operating with the third harmonic reduction technique.The experimental results show that not only a reduction ofthe third harmonic input current distortion and theimprovement of the rectifier power factor occur, but there isalso an increment in the converter efficiency. The efficiencyincrement using the third harmonic reduction modulationoperating with the nominal output is close to 0.5% for theinput voltage Vi=127 Vrms and equal to 1% for the inputvoltage Vi=220 Vrms.

Fig. 31. Pre-regulator efficiency for Vi=127 Vrms.



Fig. 32. Pre-regulator efficiency for Vi=220 Vrms.

However, a significant efficiency increment occurs inboth input voltages for the light load operation, maintainingthe converter efficiency higher than 93% for all load range.This operation characteristic is interesting for applicationswhere the rectifier operates during a long period with lowoutput power.

VIII. CONCLUSION

The theoretical and experimental analysis of the modifiedSEPIC converter used as pre-regulator operating in DCM ispresented in this paper. The proposed converter presents lowinput current ripple operating in DCM and the switch anddiodes voltages are lower than the output voltage. The switchvoltage reduction increases the converter reliability and alower RDSon MOSFET can be used depending on theconverter specification.

The experimental results presented operating with thethird harmonic reduction technique shows that the total inputcurrent harmonic distortion is reduced from 13% to 5.3%operating with an input voltage equal 127 Vrms and is reducedfrom 35.9% to 8.84% operating with an input voltage equalto 220 Vrms, considering a total input voltage harmonicdistortion equal to 3.1%. The power factor is higher than0.988 with the third harmonic reduction in all input voltagerange.

The efficiency operating with input voltage equal to 127Vrms and output power equal to 108 W is equal to 95.6%. Theexperimental results show that there is also an increment inthe converter efficiency operating with the third harmonicreduction modulation that mainly occurs at light loadoperation in 127 Vrms and 220 Vrms.

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