high-speed low-power flash adc architecture using switched...

Circuits Syst Signal ProcessDOI 10.1007/s00034-017-0673-8

High-Speed Low-Power Flash ADC Architecture UsingSwitched-Capacitor Positive Feedback Comparator andParallel Single-Gate Encoder

Saleh Abdel-Hafeez1 · Ali Shatnawi1

Received: 15 November 2016 / Revised: 15 September 2017 / Accepted: 18 September 2017© Springer Science+Business Media, LLC 2017

Abstract In this paper, two essential components of the Flash ADC are designed andintegrated within a new Flash ADC architecture. The power consumption is reducedby realizing a switched-capacitor positive feedback (SCPF) comparators structureas a replacement for conventional comparators structure. The SCPF comparator istailored to a single-ended input/single-ended output configuration that operates in twosteps: offset-cancelation function followed by comparison decision. Furthermore, theencoding stage is implemented usingN parallel independent components of one singleAND gate each, where N is the number of quantized regions. This structure providesfast encoding with minimal encoding activities. The design architecture exploits twostages, which are separated by latches. The first stage allocates the analog input to aquantized region, while the second stage converts the level of the quantized regioninto its corresponding binary code. This separation is considered the key successfor incorporating the SCPF comparators structure into our Flash ADC architecture.HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technologyand 1-V power supply. The simulation results show that our 5-bit Flash ADC canfunction at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz atNyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with anoverall maximum power consumption of 3 mW.

B Saleh [email protected]

Ali [email protected]

1 Jordan University of Science and Technology, Irbid 22110, Jordan

http://crossmark.crossref.org/dialog/?doi=10.1007/s00034-017-0673-8&domain=pdf

Circuits Syst Signal Process

Keywords Flash ADCs · Digital signal processing · High-speed low-power · FinFettechnology · Switched-capacitor positive feedback comparator · Thermometerencoder

1 Introduction

The analog-to-digital conversion is considered an essential component in many digitalsignal processing and communications systems. A Flash analog-to-digital converter(ADC) uses a multi-step voltage ladder, with a comparator at each successive step tocompare the input against reference voltages [18]. Due to their high speed and designsimplicity, Flash ADCs are widely used in integrated circuits applications that requirethe task of analog-to-digital conversion. Hence, the integrated circuit (IC) industrypertaining to data communications and networking, drive large demand on designingFlash ADCs with high sampling frequencies and low-power budgets. However, thanksto the great advances in CMOS technology [12], which makes the implementation ofhigh-speed low-power Flash ADC possible [19]. Therefore, it is the duty of hardwareand circuit designers to utilize these advances in producing optimized ADCs. SeveralFlash ADC realizations have succeeded to increase the sampling frequency, but at theexpense of more complicated circuits with high power requirements [2,8,16].

Other researchers have tried to alleviate the problem of high power requirements(without lowering the sampling frequency of Flash ADCs) by reducing the excessivepower consumption components of the design. For example, some structures rely onreducing the number of comparators by using analog and digital multiplexers [6].However, the use of multiplexers tends to slow the design by consuming a portionof the sampling period; besides, they are not power-free components. Several otherapproaches focus on improving the sampling frequency by employing multi-stagecomparators with analog latches [7,8,10]. These designs tend to improve the quanti-zation resolution; however, they draw considerable amount of power, and require largeinput/output delays. Recently, fast and low-power comparator designs work on incor-porating different threshold values for theCMOS inverter as a high-speed time-domaincomparator [9,11,13]. However, the control mechanism for the threshold values of thisinverter is considered premature and unreliable at different technology parameters andenvironments, making the Flash ADCs resolution considerably low.

On the other hand, several attempts focus on improving the speed of the encoder byoptimizing the conversion from thermometer (unary) code to the standard binary code.Varieties of encoder designs can be based on Flat-tree such as Wallace tree, ROMtable, dynamic logic and digital multiplexers [14,17,20,21]. Most of these designshave several delay stages; besides, the switching activities are carried out to most ofthe encoder gates in order to reach to a particular binary conversion.

An attempt in [7,8] used an interpolation approach in order to reduce the numberof comparators and, hence, reduce the overall drawn power. This is due to the fact thatcomparators are the main source of power consumption in the Flash ADC. However,the cascaded analog latches that are used to capture the analog decisions from thecomparator stage are not reduced. In fact, latches turn out to consume more powerand introduce more delay. The work reported in [8] requires high design cost in com-


pact layout, using 8 layers and 2 poly-material. This design is reported to have about256 dummy latches to reduce the effect of coupling and layout mismatches betweenthe analog cascaded latches. Besides, the design required a special circuit for Hold-AND-Track (HAT) analog data as contrary to other designs which embed HAT in thecomparator stage. The design required a special calibration circuit during initializa-tion phase that tends to reduce circuit speed. Additionally, the design requires timingcontroller using several delay capacitances, which turns to be unreliable on differenttechnologies. Finally, the design used thermometer Gray binary encoder structure,which is known to be inefficient in terms of power vs. speed [14,17,20].

The designs proposed in [9,11,13] to reduce the power of the comparator stageuse basic digital logic gate with adjusted threshold as a comparator component. Thisreduces the biasing consumed power. The structure in [13], for example, uses twotypes of comparators, namely conventional double-tail and NOR-NAND digital logicgate comparators. The conventional double-tail one compares the input against thereference tap voltages, which are generated form the resistor ladder, and it is designedfor most significant bits (MSB) quantization regions. Hence, the design requires fewanalog comparators of type double tail. On the other hand, the design uses digitalgate of NOR-NAND circuit with desired built-in reference voltage for fine resolutionof quantization levels. It reduces the power consumption; however, the quantizationresolution is far below what is attained by modern designs. This is mainly due todifferent technology threshold environmental corners and layout grid mismatches.Although the design records large sampling frequency, the maximum-recorded inputfrequency was about 100× less than the sampling frequency. Besides, the designdoes not utilize recent technology factors as it operates at a high power supply,1.8 V.

In order to alleviate typical drawbacks of the previous designs, we propose a newsplit architecture alongwith switched-capacitor positive feedback (SCPF) comparatorsstructure and parallel single AND gates encoder. The SCPF comparator is a realizationof a switched-capacitor and a positive feedback [4,5] that is tailored to an auto-zerofunction followed by a comparison cycle with a single-ended input/single-ended out-put. Hence, the new Flash ADC architecture inherits the advantages of the SCPFdifferential comparator, which is commonly known for its high-speed, low supplyvoltage operation and low power. Additionally, the architecture optimizes the encoderby assigning parallel single AND gates for each quantized region. Thus, only one sin-gle AND gate is activated and one single gate is deactivated for any sampled analoginput, and thus resulting in low-power consumption. Furthermore, the delay of theencoder is reduced to a single gate resulting in a circuit with an extremely fast decod-ing time. The two stages operate concurrently using non-overlapping clock system[15]; such that, while the second stage is refining the converted digital data, the firststage samples a new analog data. The design operates on two phases of the samplingclock in parallel, thus achieving sampling at a high frequency.

The remainder of this paper is organized as follows. Section 2 covers the proposeddesign operating principles and overall architecture, while Sect. 3 provides the designdetails. Section 4 provides HSPICE simulation results and performance analysis fortesting the proposed Flash ADC of 5-bits with 1 V input signal swing range. Conclud-ing remarks and suggestions for further work are provided in Sect. 5.


2 Overall Architecture

The proposed Flash ADC architecture, illustrated in Fig. 1, is designed with only twomain stages that operate concurrently at the two asserted levels of the sampling clock.Each main stage is comprised of four sub-stages, which are necessary to convert theanalog input to its corresponding digital value. The first main stage includes a resistorladder along with analog buffers (ABs), single-ended input and single-ended outputcomparators, and a parallel single gates encoder. On the other hand, the second mainstage includes a positive edge trigger D-type Flip Flops (DFFs), an error correctionlogic, parallel single pass-gates (switches), and positive edge trigger DFFs. The pur-pose of the first main stage is to do the conversion from analog information to digitalinformation, while the purpose of the second main stage is to refine the digital infor-mation to a quantization region and filter out the errors incurred during the conversionstage.

The sub-stages are now explained. The first sub-stage is a conventional resistorladder [18] that divides the maximum voltage (Vmax) and minimum voltage (Vmin)into 2m equal segments, thus providing m-bit binary resolution. Hence, the soft nodes(reference tap voltages VRUi, VRLi), which are generated from the resistor ladder, arepropagated though high-speed analog buffers (ABs) [3]. The analog buffers (ABs),which are considered the second sub-stage, are used to obviate the coupling effectwhich ismajorly due to changes in the input signal andvoltage supply at sub-stage3, thecomparators. In order to minimize the grid layout mismatches, two SCPF comparatorsare combined into a single block with single biasing, which is illustrated as a boundarycomparator (BC) and referred to as the third sub-stage. The boundary comparatorscover non-overlapping quantization segments as clearly illustrated in Fig. 1. Therefore,the m-bit Flash ADC structure consists of 2m−1 boundary comparators, with a totalnumber of SCPF comparators that is equal to 2m . Each boundary comparator comparesthe analog input voltage (Vin) against two reference voltages which are referred to asthe upper reference tap voltage (VRUi) and the lower reference tap voltage (VRLi),where VRUi>VRLi. Thus, each boundary comparator produces two outputs, whichare the upper output voltage (VUOi) and the lower output voltage (VLOi). The functionfbc given in the following equation describes behavior of the boundary comparator.

fbc =

⎧⎪⎨

⎪⎩

VUOi = VDD and VLOi = VDD VIN > VRUi

VUOi = 0V and VLOi = VDD VRLi < VIN < VRUi

VUOi = 0V and VLOi = 0V VIN < VRLi

(1)

The forth sub-stage exploits parallel and separate gate logics (AND with Inverter),one for each quantized segment. Each gate logic determines the boundary comparatordecision outputs (VUOi,VLOi) of that particular quantized segment. This parallelsingle-gate logic represents a simple quantization encoder that exhibits minimumactivities. That is, only the assigned active quantized region triggers the AND logicto high, while the rest of AND logics, which are assigned to other quantized regions,are triggered to low. Therefore, for each new conversion, one AND logic changes itslogic to high, while the previously logic-high AND gate goes to logic-low. Hence,


Fig. 1 The proposed Flash ADC architecture with two main stages, each consisting of four sub-stages

only two AND logic gates of the encoder structure exhibit activities, a key feature forlow dynamic power.

The second main stage includes the sub-stages 5–8, as follows. Sub-stage 5 hasDFFs, where each DFF is assigned to one of the encoder outputs. The DFFs hold thequantized encoder values. Sub-stage 6 is used to eliminate any error that might occurdue to a sparkle or a bubble. These bubbles usually introduce more than one high valuein the encoder sub-stage, and thus, more than one high value are stored in sub-stage5. Hence, sub-stage 6 is needed to remove the erroneous high values and keep onlysingle high value within the pattern (more details will be given in Sect. 3). This singleasserted output pattern enables only one switch from the binary array switches (i.e.,sub-stage 7), and thus, the binary array switches release the digital binary value to


Fig. 2 Timing diagram of sampling frequency with respect to input analog value versus digital output value

the final sub-stage DFFs. The number of DFFs in this final sub-stage (sub-stage 8) isobviously equal to m.

The timing diagram shown in Fig. 2 is similar to the modern two-phase non-overlapping clocking system design [15], where the main first stage operates at thesampling clock (CLOCK-1), while the second main stage operates at the negatedclock (CLOCK-2). Following the timing diagram in Fig. 2, the first analog input (i.e.,value (0)) is being sampled at the rising edge of CLOCK-1 and is processed duringthe high level of this clock signal (CLOCK-1). On the other hand, the second mainstage starts processing value (0) at the positive edge of CLOCK-2 after a half cycleof CLOCK-1. As the second main stage processes this input (value(0)), the first mainstage starts initializing the feedback capacitors of BCs in order to receive a new ana-log value (value (1)) at the positive edge of CLOCK-1. Sub-stage 5 is composed ofN = 2m DFFs, which are triggered by CLOCK-2. Hence, it isolates the overlappingoperation between the two main stages. In addition, sub-stage 8 is also composed ofm DFFs to represent 2m quantized regions. This sub-stage is triggered at the positiveedge of CLOCK-1 despite its existence in the second main stage. Therefore, at everyrising edge of CLOCK-1, a new analog input is sampled and a new digital outputcorresponding to the previous sample of the analog input is released.

3 Circuits Design

In this section, we explore a detailed analysis of the circuit components of the proposedFlash ADC circuit architecture. The resistor ladder is a conventional circuit that hasbeen widely used and analyzed in several Flash ADCs, which are reported in theliterature; a detailed layout analysis can be found in [1]. Another important advantageof the resistor ladder is having a boundary voltage ofVmax andVmin, since the cominganalog signal is bounded between these two values. The reference tap voltages, whichare divided by the resistor ladder, usually produce circuit non-idealities (not just layoutgradient error) of small voltage changes that follow the input signal. This makes theresistor ladder reference voltage swing (partially up and down) following the behavior


Fig. 3 Schematic diagram of the modified SCPF comparator along with complete boundary comparator

of the input signal. These non-idealities are usually due to coupling effect with theinput signal at the boundary comparators sub-stage (sub-stage 3). Some of these circuitnon-idealities are discussed in [1–3]. In order to alleviate this coupling effect betweenthe resistor tap voltages and the input voltage, low-power analog buffers [3] are used.These buffers drive the resistor taps voltages and consequently isolate them from anycoupling with the input signal and preserve constant reference voltages for accuratecomparisons.

The boundary comparator, which is illustrated in Fig. 3, is composed of two SCPFcomparators with a single bias driving circuitry. It receives three analog input voltages,which are the upper boundary reference tap voltage (VRUi), lower boundary referencetap voltage (VRLi), and the input voltage (VIN). Moreover, it produces two outputdecision voltages, the upper decision voltage (VOUi) and the lower decision voltage(VOLi). The SCPF comparator is derived from a differential input comparator-basedswitched-capacitor positive feedback comparator [4]. This comparator is known forits low operating voltage with large and fast gain response that makes it attractive foradvance nanoscale CMOS technologies. Further, it operates on the two phases of thesample clock cycle.

Without loss of generality, we confine the discussion on the left SCPF comparatorsince the right comparator is an analogue of the left but with different reference tapvoltage.During phase 1 of the clock cycle, all S0 switches are closed as clearly depictedin Fig. 4. Hence, the VRLi is sampled through the two capacitors labeled as C1 at bothinputs of the SCPF comparator, while capacitors C2 are shorted as clearly shown inFig. 4a. On the other hand, during phase 2 of the clock cycle, all S0 switches areopened as shown in Fig. 4b. In phase 2, the VIN is inputted into one side of the SCPFcomparator, while the sameVRLi is used on the other side of SCPF comparator. Hence,the voltage difference of VIN with respect to the reference tap voltage (VIN–VRLi)is compared against the voltage difference of the same reference tap, (VRLi–VRLi).


Fig. 4 The differential input comparator-based switched-capacitor positive feedback comparator: a allswitches are closed; b all switches are opened

Thismechanism adapts the SCPF to be used in FlashADC structure and also precludesoffset voltage that usually appears due to the grid layout mismatches of the two sideof the SCPF comparator. Furthermore, it eliminates the clock-feed-through since thesame value is subtracted from itself once more. The detailed analysis of the SCPFcomparator during the two phases of clock cycle is given in the following.

– Phase 1: All S0 switches are closed as shown in Fig. 4a, we have

V X1 = V X2 = V L1 = V L2 (2)

C1[V X1 − V RLi] = Q1 (3)

where Q1 is the total charge at node X1

C1[VX2 − (VRLi + VOFF)] = Q2 (4)

where Q2 is the total charge at node X2– Phase 2: All S0 switches are opened as shown in Fig. 4b, we have

C1[VX1 − VIN] + C2[VX1 − VO2] = C1[VX1 − VRLi] (5)

C1[VX2−(VRLi+VOFF)]+C2[VX2−VO1] = C1[VX2−(VRLi+VOFF)] (6)

From (6), we have:

VX2 = VO1 (7)

From (5), we have:

VIN = C2

C1VX1 − C2

C1VO2 + VRLi (8)


From (8), we have:

(VIN − VRLi) = C2

C1VX1 − C2

C1VO2 (9)

Thus, the differential input is independent of the offset voltage. From (8), (6), and(2), we have:

(VIN − VRLi) = C2

C1VO1 − C2

C1VO2 (10)

From (10), the differential inputs with respect to the single outputs VO1 and VO2represent the case of lower than and higher than, respectively. Therefore, we onlychoose the single-ended output that represents the case of lower than; that is,

VIN − VRLi = C2

C1VO1 (11)

Equation (11) shows the difference of input voltage with respect to the associatedreference tap voltage (VIN–VRLi) from one side, and the difference of the associatedreference tap voltage with itself (VRLi–VRLi) from the other side. Thus, repeating thesame reference tap voltage during the two phases of clock minimizes the effect of theoverall clock-feed-through switches and the comparator-offset voltage. Furthermore,Eq. (11) represents the positive feedback gain of the SCPF with C2/C1 ratio. In addi-tion, the SCPF comparator has a simple active load consisting of a single transistor thatreduces the VDD and GND to only one threshold value. Thus, the SCPF comparatorcan operate on a low supply voltage and a large signal swing.

The sub-stage 4 presents parallel single gates (AND with Inverter), which is calledthe quantization encoder. It is used for detecting the quantization regions based onthe received outputs of boundary comparators. To clarify, assume the proposed FlashADC has eight quantization regions with 3 bits being used for binary outputs as shownin Fig. 5. If we assume error-free comparator decision outputs, the comparator outputsshould belong to the set {01111111, 00111111, 00011111, 00001111, 00000111,00000011, 00000001}. Consequently, the parallel single gates quantization encoderneeds to detect the change from 0 to 1 as illustrated in Fig. 5. Therefore, the output ofthe parallel single gates quantization encoder is asserted high for only one gate output,while all other gated outputs (7-outputs) are asserted “0s”, where each gate outputrepresents a quantization region.

Sub-stage 5 realizes parallel simple digital low-powerDFFs that are triggered simul-taneously by the negated input clock (CLOCK-2). Hence, the purpose of the DFFs isto hold the asserted quantized signal coming from the parallel single gates quantiza-tion encoder, which is sub-stage 4. Besides, the DFFs in sub-stage 5 permit the SCPFcomparators to restart the initialization phase (Phase 1: all switches are closed) andprepare for the next comparison input voltage, while the current quantization regionvalue is preserved and processed in sub-stages 6, 7, and 8.


Fig. 5 Proposed Flash ADC block diagram for a 3-bit example

Fig. 6 Error correction circuit for any order of bubbles (sparkles)

Sub-stage 6 comprises of error correction logic that is illustrated in Fig. 6 for thecase of more than one asserted values appearing at sub-stage 5, commonly known asbubble or sparkle [14–17]. If there are multiple asserted values held by the DFFs dueto SCPF comparators parasitic delay clock, the error correction circuit filters out allbubbles and makes sure that only one asserted value is passed to the next sub-stage(sub-stage 7). The error correction circuit is composed of a look-ahead logic structure,


which keeps the lowest logic 1 from the bottom side of the circuit and removes allother 1s.

Sub-stage 7 exploits parallel switches, where each switch represents the digitizedbinary value of a quantization region. The asserted value of the encoder stage (sub-stage 4), which is held by the DFFs sub-stage (sub-stage 5) and then corrected by theerror correction logic (sub-stage 6), is released by one switch in sub-stage 7. Everydigitized binary value is assigned to a particular switch; such that, when this switchreceives an asserted signal from sub-stage 6, it releases the digitized binary value.Sub-stage 6 assures that only one signal is asserted high and all others signals areasserted low; hence, only one switch is enabled and all others switches are disabled.Subsequently, the digitized binary value is then stored through the final DFFs at therising edge of the clock in sub-stage 8. Therefore, at every rising edge of the clock,one digitized binary value is stored in the final DFFs. The number of final DFFs isequal to the digitized binary resolution value, which is in our example three.

Obviously, the design operates on a two-phase clocking system that permits thedesign to produce a digital output and sample an analog input at every rising edge ofthe sample clock. The design uses components that are well known for their appealingcharacteristics: low power, high speed and ability to scale well with advances in tech-nology. For example, the SCPF comparator is known to be attractive for low-power,high-speed applications. However, it is normally used in differential mode operations.We tailored the behavior of SCPF design for usage in single-ended input/output mode.Further, the use of a two-phase clocking system results in a lowpower high speed SCPFcomparator with offset cancelation.

Another advantageof the design is the use of amodular structure.Theuseofmultiplesub-stages simplifies the operations operated by the different stages. Furthermore, ourencoder uses parallel single gate AND structure, with one-gate delay, in which onlyone gate is activated and one gate is deactivated and all other gates are not involved inany activity. On the contrary, the classical Flash ADC encoder relies on flat gate levelstructure, which is considered a high source of power activities due to engaging mostof the encoder area most of the time. Our design combines merits that are hard to findin one Flash ADC design (low power, high speed, and large quantization range).

4 Simulation Analysis

The proposed Flash ADC architecture is characterized by its high conversion speed,high resolution and low-power consumption. HSPICE simulation is used to verifythese characteristics using a 5-bit design with the features listed in Table 1. The SCPFcomparator design provides a resolution of about half theweight of the least significantbit (LSB) which is equivalent to 1/2 ∗ (1/32) ∗ (0.8 − 0.2) = 9.375mV. The clockrunning frequency is 1 GHz with a slew rate of 0.2 ns/V. The power supply voltage ischosen to be 1 V.

The simulation results given in Fig. 7 illustrate the waveforms of the SCPF com-parator combined with the responses of the analog buffer (AB) using a samplingfrequency of 1 GHz. The input signal (VIN) has a ramp waveform and the referencetap input voltage (VRLi) is set to 0.5 V. The ramp input (VIN) is made to exercise all


Table 1 Characteristics of theproposed Flash ADC

Characteristics Value

Power supply 1.0 V

CMOS technology 35 nm

Analog input range 0.2 V-to-0.8 V

Resolution 5-bit

Sampling frequency 1 GHz

INL and DNL <<1

2LSB

SNR 31 dB

SFDR 40 dB

Power consumption 3 mW @maximum Nyquist rate

Transistors count 2120

Fig. 7 Waveform time simulation for the comparator

quantization levels in ascending and descending orders. Several other simulations arealso made to test the response speed by having the comparator to switch full range ofinput within one sampling cycle, but are not shown for brevity of discussion. Figure7 shows the maximum consumption current (CURRENT = 91µA); therefore, theoverall average consumption power is calculated to be (1V∗90µA)∗32 = 2.88mW.Additionally, Fig. 7 shows the differential inputs, VIN, which is the ramp ascendingfrom 0.2 to 0.8 V and the reference tap voltage which is set to 0.5 V. Furthermore,Fig. 7 shows that the SCPF comparator single-ended output VOLi is set to ground≈ 0 V when VIN<VRLi, and is set to VDD=1 V when VIN>VRLi. In conclusion,Fig. 7 shows that the SCPF comparator operates at 1 GHz clock speed with clear


Fig. 8 Time simulation of ramp input at 1 GHz sampling frequency

offset cancelation and clear low power current in the order of< 90µA. Hence, the 32SCPF combined exhibits very low-power consumption, which is comparable to thelow-power design ADC converter.

The complete proposed Flash ADC design given in Fig. 1 is depicted in Figs. 8, 9,10, 11, 12 and 13. Figure 8 shows the output response using binary values for a givenramp input sampled at 1 GHz clock frequency. The first window in Fig. 8 shows thesampling clock period of 1 ns per period; the secondwindow displays the ramped input(VIN) which is applied to our Flash ADC. The last window of Fig. 8 shows that theFlash ADC produces 5-bit digital outputs V(B0), V(B1), V(B2), V(B3), and V(B4) atevery sampling period. It can be noticed that the digital waveforms have equal distanceof one cycle from each other at every period; thus, the concept of a perfect workingdesign is proven. Furthermore, the binary outputs are expressed in voltage waveformsas shown in Fig. 9, which indicates that integral nonlinearity (INL) and differentialnonlinearity (DNL) are much less than 1/2 the weight of the least significant bit of thedigital representation.

Figure 10 shows the timing simulation for the input signal running at 500 MHz asa Nyquist rate with respect to the sampling frequency 1 GHz. The digitized outputdepicted in Fig. 10 (V(B0), V(B1), V(B2), V(B3), V(B4)) shows a consistent uni-form spacing pattern, which indicates accurate simulation results. Further, simulationverification is considered by taking the Fourier Transform of the digitized output asclearly illustrated in Fig. 11. Figure 11 verifies the peak frequency at 500 MHz andshows the signal-to-noise ratio of about 31 dB, which is consistent with theoreticalone, about 6 dB per resolution bit. Another simulation verification is carried throughanalyzing a very slow input frequency at 7.8125 MHz as shown in Fig. 12 in order to


Fig. 9 Analyzing the ramp input for INL and DNL at sampling frequency of 1 GHz

Fig. 10 Time simulation of input frequency of 500 MHz at 1 GHz sampling frequency

exercise all possible digitized outputs and test the complete resolution of the proposedFlash ADC. The digitized outputs (V(B0), V(B1), V(B2), V(B3), V(B4)) shown inFig. 12 show a consistent pattern for the given signal input running at 7.8125 MHz.


Fig. 11 Power spectral density at 500 MHz input frequency with 1 GHz sampling frequency

Fig. 12 Time simulation of input frequency of 7.8125 MHz at 1 GHz sampling frequency

The verified Fourier Transform shown in Fig. 13 of the sampled analog input at 7.8125MHz, shows a peak at the input frequency and provides a similar SNR of 31 dB.


Fig. 13 Power spectral density at 7.8125 MHz input frequency with 1 GHz sampling frequency

Several other input frequencies have been tested and verified to confirm the properfunctionality of the ADC; however, for the sake of brevity we have only presented theabove simulations. On the other hand, the total power consumption was measured andverified by calculating the switching activities and leakage of transistors in addition tothe power consumption of the comparators (i.e., static and dynamic). It was observedthat the quantization encoder depicted by sub-stage 4 has only one active gate and oneinactive gate, a case similar to sub-stage 7, whereas sub-stage 5 and sub-stage 8 uselow-power DFFs. Furthermore, sub-stage 6 uses small number of CMOS transistors.Hence, the total power consumption for the digital sub-stages (4 to 8) is about 0.48µW . Therefore, the design has a total power consumption of 2.8848 mW, which isactually manifested by the comparators (sub-stage 3) and the analog buffers (sub-stage2). Additionally, the total number of CMOS transistors is 2120. Hence, the proposedFlash ADC is not only efficient but also simple in terms of the design and hardwarecomplexity.

5 Comparison with Other Works

Flash ADCs are widely used in Analog-to-Digital research area and practical ICsdesign implementations. In recent years, Flash ADCs have gained more attention inthe industry due to advances in nanometer CMOS technologies that can reach up to14 nm practical implementations [12]. The advances in nanometer CMOS technolo-gies provide key features that are directly related to low supply voltage, low-powerconsumption, and high-speed operation which are considered the corner stones in


Table 2 Comparison with other Flash ADCs

ADC Fs (MHz) Fin (MHz) MR Power supply and Voltage MP

[2] 2000 1000 6 1.8 V 0.8 Vp-p 28

[10] 1000 500 6 1 V 0.6 Vp-p 15.75

[6,16] 50 25 6 1 V 0.6 Vp-p 0.4

[16] 1500 750 6 1.2 V 0.6 Vp-p 204

[21] 1750 200 5 1 V 0.4 Vp-p 7.6

[13] 250 100 5 1.8 V 0.4 Vp-p 7.11

[8] 2000 1000 6.5 1.2 V 0.4 Vp-p 20.7

This work 1000 500 5 1 V 0.2 V to 0.8 V 3

ADC Offset cancelation Encoder structure Comparator structure

[2] Calibration Memory Large active load

[10] Calibration Fat tree Multi-cascaded stages

[6,16] Calibration MUX-based Multi-stage preamplifier

[16] Programmable offset Wallace tree Multi-stage

[21] Calibration shift register ROM Multi-stage

[13] Standby mode Wallace tree Conventional double tail and gain booster

[8] Offset calibration Gray-code Interpolation and dynamic latches

This work No calibration Parallel single gate SCPF

MR maximum resolution in bits, MP maximum power in mW

designing practical Flash ADCs for modern applications. Therefore, in our compari-son depicted in Table 2, we have highlighted these key features.

Flash ADCs given in [2,8,13] have large active load comparator circuit, whichare known for low resolutions, and require large power supply in order to operatethrough all the thresholds voltages. This is considered a major drawback feature inCMOS technology. Other Flash ADCs [10,16,21] have used a multi-cascaded-stageamplifier in order to improve the resolution. This limits the speed and increases thepower consumption. As shown in Table 2, the cascaded structure requires some sortof offset calibration, which is also a limiting feature for timing initialization andfor compatibility with future technology environments. Another major drawback ofFlash ADCs is the high-cost encoder design. The memory encoder designs in [2,21] suffer from a speed bottleneck. Similarly, the fat-tree encoder logic in [8,13,16]and are considered to have speed and power consumption drawbacks. Having largeencoder actually compromises the speed benefits of using advance nanometer CMOStechnology. Some reported Flash ADCs must operate at low input frequencies; eventhough, their sampling frequencies are high as in [6,13,21]. This shortcoming is dueto the design structure that consumes large power when operated on high frequencies.

The proposed design is implemented to sustain continued advance scaling CMOStechnologies, and utilize the key features of these technologies. The comparator of theSCPF is known for its large gain, low supply voltage, and high resolution due to theuse of offset cancelation. That is, the design is made suitable to operate at low supply


voltage less than 1 V, and yet provide high gain with fast convergence due to thepositive feedback capacitor ratio. Furthermore, the architecture obviates the couplingeffect and mismatches offset at the comparator stages by using a simple analog buffer.Additionally, the split architecture through intermediate DFFs (sub-stage 4) providestiming overlaps and enough time per main stage to evaluate the digital output. Thispermits the two main stages to operate concurrently, and thus, the overall design isoperating at a two-phase non-overlapping clocking system. As a result, the designsupports large sampling frequency in the order of 1 GHz, and input frequency of 500MHz at Nyquist rate with a total power consumption of 3 mW. These features areconsidered attractive for modern and future communication applications. In addition,the encoder is the only single-gate delay with minimum power consumption; only twogates change states (activate and de-activate) per each new analog input. Subsequently,the encoder structure within the overall architecture reduces the delay to only one gateand minimizes the drawn power activities, making our design excellent for high speedand low-power concurrently.

6 Conclusion

In this work, we have proposed a new Flash ADC architecture with two essential com-ponents, which are single-ended input/output SCPF comparator that inherits largeoffset cancelation with large gain and low supply power, and a parallel single-gateencoder with obviously a one-gate delay. The design exploits the advantages of con-tinued CMOS technology scaling which has key features of operating at low supplyvoltage, low-power switching activities, and high-speed operation. The architectureuses intermediate DFFs that separate the analog evaluation phase from the digital eval-uation one. The two phases are working concurrently; such that, while the design iscorrecting bubbles and encoding digital data, it samples a new analog data and mapsit to a quantized region. HSPICE simulations clearly show that the design can operatesmoothly at 1 GHz sampling frequency with full Nyquist rate input frequency, andhence, producing 1 GS/s for the example of 5-bit resolution using 35 nm technology.

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