7/28/2019 High Voltage Power Pulse Circuit

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IDEAS FOR DESIGN

Fast rise-time high-voltage pulseshave many uses ranging fromEMC testing to device characteri-

zation.The simple, low-cost circuit de-scribed here deals with the latter. Itsable to generate 0- to 1000-V pulseswith currents up to 50 A, and a risetime of 100 ns for 800 V/30 A. The out-

put can withstand short circuits, andcapacitive and inductive loads. Pulselength and repetition rate are deter-mined by an optically isolated TTL-in-put signal. Commercial equipment likepulse/function generators or a PC canbe connected to this input. The pulsesamplitude is set by the HV supply; alow-cost photomultiplier-type supply(0, 5 ..5 mA) can be used when repeti-tion rates are below 20 Hz.

The circuit operates as follows:when applying the HV supply, C1 ischarged up to a voltage HV via R1

and D1 (see the figure). A 0-V controlsignal keeps the PowerFET Q1 in theoff state. A 5-V signal on the controlinput operates the driver IC2, fromwhich a 12-V signal is presented onthe gate of the PowerFET Q1, bring-ing it into conductance. The output ofthe circuit becomes HV volts as the

negative terminal of C1 is nowgrounded. The pulse ends by makingthe control signal 0 V. Useful pulselength is limited by he voltage dropduring the pulse (caused by discharg-ing C1) and by the 100-s/64-A savelimit of the PowerFET. For the val-ues shown, the circuit voltage drop is10 V for a 1-s, 10-A pulse.

The short-circuit and overload pro-tection is based on R1. When the out-put current is rising, the effectivegate-source voltage of the Power-FET diminishes, enlarging the FET

resistance. With the given 0.1-value, the output current is limited to50 A. In a short-circuit situation, ca-pacitor C1 can be fully (and safely)discharged in the PowerFET. Re-verse voltages caused by inductiveloads are eliminated by D1. When the

circuit isnt operating, R14 dis-charges C1 for safety reasons.Circuit layout is very

importanta groundplane is neededto keep inductance low. C1 must be alow-inductance pulse capacitor. Eventhe FET driver IC2 needs a low-in-ductance layout and decoupling. Dur-ing the leading-edge gate currents,up to 2 A are needed to charge theFET input capacitance. Resistors R1and R2 have to be made of at least 10paralleled discretes to get a low se-

ries inductance. R4 and C3 compen-sate for the remaining inductance inR2 (the value of C3 can be changedfor this). C2, R5, R6, and R7 form asnubber network to protect the FETagainst voltage spikes. The values forthe voltage and current monitor lev-els are given for a 50- load.

Higher currents can be obtainedby duplicating the IC2-Q1-R1 stageand connecting them in parallel. R1helps to equalize the current for eachstage. A 100-A pulser has been suc-cessfully built in this manner.

High-Voltage PowerPulse Circuit

R.N. SCHOUTENFaculty of Applied Physics, DIMES, Delft University of Technology,

P.O. Box 5046, 2600A Delft, The Netherlands.

Circle 520

147

ELECTRONICDESIGN/DECEMBER1,

1997

Fast risetime pulses of 0 to 1000 V, with currents up to 50 A, can be generated by this simple, low-cost high-voltage power pulse circuit.

R447

HV Pulse output

R13330 Voltage

monitor

1 mV/V

Currentmonitor

10 mV/A

C322 nF

R34.7k

1 kV

D1RURP8100

Harris

R11330

R1556

R12330

R20.02

33

33

R6

33 2.2R7

C11F1 kV

2k

HV suppl

R18 R1410M

1200 V

C2

R5

Q1

R10.1

R82k

R92k

R10

STE16N100SGS-Thomson

+12 V

C4100 nF

10 nF

C510F

IC1

IC2

+12 V C6100 nF

R175.6k

MAX626

8

7

6

5

0/+5 V

Control In

R16200

D2

1N4148

6N135

1

2

3

48

7

6

5

1

2

3

4