HINS BPM Overview

N. EddyFor Instrumentation Dept

BPM Hardware Overview

2

BPF LPF

Trig

Down Mix

Cal (xxx)

Timing(VME)

LO (665)CLK

(81.25)

TRG

Digital Receiver

(VME)

VME µPMotorola

5500Q

Ibeamposition

4 buttonBPMpickup

IF (15)

beam

VME BUSLAN

PLL

4ATT

4

CAN

CTRL

325

Analog Signal Processing

• 4-ch. Analog downmixer– IN: 650 (2nd harmonic), LO: 665.1, IF:

15.1 MHz– CAN-bus controlled gain, attenuator

& cal system– Gain switchable, low-noise, high IP3

input gain stage– Image rejection (SSB) mixer– ~30 dB gain,

ultralinear IF stage3

15.145 MHz

BPFATT LNA BPF LNA LPF

SSB Mixer

LO

0°

90°

LNALPFDirectional

CouplerIN

714MHzCF: 650MHzBW: 10MHz G: 14/-2 dB

NF: 1dB0 - 28 dB

4 dB steps1.6 dB loss

665.1 MHz

CF: 15.1 MHzBW: 4MHz

G: 18 dB BW: 40 MHz

OUT

BW: 800 MHz G: 15 dBNF: 1dB

Cal Tone Signal

8-Ch,14-bit, 125 MS/s VME Digitizer

4

BLOCK DIAGRAM

FPGAAlteraCyclone III

VMEDrivers

4x32MDDR2SDRAM

JTAG

EPCS4Interface

VME bus

Oscillator

Oscillator

CLK IN

CLK OUT

GATE

TRIGGER

TCLK

SYNC IN

SYNC OUT

Generic Digitizer

External Control

Clock Driver (PLL & DIV)

ADC

ADC

AC passive

8 Analog Inputs 4 Channels per Chip

• 125 MSPS, 500 MHz BW• 4-ch serial ADC chips• 8-ch, AC passive (or DC active)• PLL/VCO CLK distribution• SNR > 72 dB (@50 MHz)

FPGA Block Diagram

5

ADC Input14 Bits69 MHz

NB Filter1.4kHz output

16 Bits/ch

32 ch/

NB Gate

WB Gate(s)

DDR RAM

NB DataTBT DataRaw Data

Σ50Hz

VMENB Data

VMERaw Data

TBT FilterDDC & average

VMETBT Data

8 ch/

Trigger DAQ SMCh delays (clocks)

Gates in Turns

WB Gate(s)

NB Gate

32 Registers

VMENB Sums

VMEIRQ

reset latch

reset

latch

16 ch/

Narrowband Signal Processing• Design footprint for 8 ADC channels

• 2 NCOs for beam and cal frequencies -> 16 DDCs

• 32 CIC Filters operating at 69 MHz• 5 stage CIC uses 13 k LEs

and <1% of RAM

• 1 Serial FIR Filter will process all 32 CIC Filter outputs

• 76 tap FIR (400 Hz BW, 500 Hz Stop, -120 db stopband)

• Decimate by 3 to 1.4 KSPS output

6

ADC Input14 Bits69 MHz

X

NCO (sin, cos)24 Bits Phase

(~1 Hz)

I

Q16 Bits

CIC5 StagesR=16485

DDC24 Bits

4.2 KSPS

FIR (76 taps)LPF 500HzDecimate 3

BitShift

SelectSignificant

Bits

20 Bits4.2 KSPS

16 Bits1.4 KSPS

I

Q

- Denotes Peak Detectors to optimize scaling

28 pts aveto notch 50 Hz

Software Components

7

VMEECAN-2 PMC (1x)

VMETimingK-TGF(1x)

VMEDigitizer

(12x)

CLK (64.9)

TRG(Gate)

A

B

C

D

714

2.16

INJ(BIS)

729

CAN

ClassADC

Interrupt

I/Q Data

DDC Configure

ClassKTGF

Bucket Delay

Turn Data

Sample Count

ClassCALBox

Control

Status

ClassATFBPM

ClassATFBPMC

AL

Control

Status

Sample

Control

Interrupt

Control

Pos/ Int Data

EPICSIOC

Control

Status

Flash

WB / NB

Single/Multi-turn

Diag. Mode

Bucket Delay

Turn Delay

Diagnostic

Flash

Orbit

Multi-turn

VME Hardware Motorola 5500 µP Software (VxWorks)

Ethernet

Raw Signals from 4/20/11

BPM 1

BPM 3

BPM 2

BPM 1

BPM 3

BPM 2

FFT of RAW Signals for 1st BPM

DDC with Boxcar Filter ~4MHz BW

Magn

Diff/Sumfiltered

Sumfiltered

Magn

Diff/Sumfiltered

Sumfiltered

Questions

• What information is desired from the BPM?

• BW and update rate over the pulse?– Could have WB arrays & pulse averages

• Phase measurement (???)– Should produce relative phase along bpms able to

detect changes in TOF– Could produce absolute phase if we make a reference

bpm from RF… needs some further thought

Summary

• Hardware for standard bpms completely installed and working

• Firmware/Software for ATF project – Currently only provides 1024 ADC samples– Need to decide exactly what the Firmware should

do…