how to design a reliable power distribution network ... ·...
TRANSCRIPT
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How to Design a Reliable Power Distribution Network Through Chip/Package/PCB Co-Design
ZTE Corporation
Meng Liqiang,Lu xian,Zhu Shunlin ,YI [email protected];[email protected]@zte.com.cn;[email protected]
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With the increase of chip rate, the decrease of core voltage and the rise of current, PCB PDN design is one of the main challenges of the PCB design. Because PDN design has its own characteristic, so one kind of power supply design scheme is generally cannot be copied to another case, EDI CON convention in March 2018 speech we mentioned it is difficult to obtain the CPM model but is something worth doing. It is very lucky, we get some model,through the Chip/package/PCB co-simulation,We optimize the performance of the power supply, reduce the cost of the product, improve the performance of the product. This paper mainly focuses on the research of the target impedance under the actual working current of the chip,introduce a method to meet the chip noise specification.
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ü The Goal of PDN Designingü General PDN Simulation Flowü Chip Power Modelü Characteristic Impedance Simulationü Transient Analysisü Conclusion
Agenda
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The Goal of PDN Designing
DC IR DROP Impedance for AC Transient Analysis
Setup/Hold Margin Reduction
EMC Noise
Bit Error Rate for serial links
100GBASE-KR4 requires <150mUI of deterministic jitter
SSN
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General PDN Simulation Process
ü How much drop is ok ü What is the cutoff
frequency of PCBü What does the current
waveform look like
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System power analysis with the CPM model can predictØ Noisy in the die Ø Noise at the bumps Ø Frequency resonanceØ Optimize PCB decapsTransient analysis can help toØ Find the best solutions Ø Tradeoffs for die capacitance
and package decaps
Chip Power Model
TotalL < 3 nH
measuredbetween BGA mtg.surfaces.
PCB parasiticInductance and Resistance
>nuF
ESL
ESR
BGAsPCB Decoupling cap
Package Model
< 3nH
<2nHR1
Rx
< 3nH
Rx
VSS
VSS
VXX
R_Package &L_Package
Rg
Rg < 0.5 ohms/C4
(BGA PTH)
(BGA PTH)
VSS C4s
n-port core
Core Model
Load
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System Integrator Design Flow
VRM
l Collecting modelüVRMüCPMl Extract PCB model with correct DC pointl AC and Transient Analysis set upl Test Validation
PGCap
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Simulation Setup ü VRM Ideal simple RLC Pspice modelü PCB Broadband SPICE or S-parameterü PKG S-parameter or RLC model ü CPM different operating modes
VRM model PCB model PKG model CPM model
System Simulation Setup for Core VDD & VDDA
S-parameter S-parameter RLC
Different operating modesPspice model
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Characteristic Impedance Result
System Simulation Setup for Core power AC impedance
Design margin
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Transient Analysis Result
Schematic diagram Simulation Result AC nosie 1.9% DC IR Drop 4%
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Test VS Simulation
Characteristic Impedance Test vs Simulation Transient Analysis Test vs Simulation
16mV@BGA
18.8mV@BGA
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SummaryØ Getting the CPM model is a very difficult but necessary thing to do
Ø CPM has accurate load current profile and complete package information
Ø Dynamic target impedance show that PCB have same margin compaire with traditional target impedance
Ø Test Vs simulation is can improve design confidence for both ac and transient
Ø Thermal&SI&PI co-simulation is another worth thing to do
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Thank you!