how to design an integrated circuit - interdisciplinary … · 2005. 11. 4. · how to design an...
TRANSCRIPT
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How to Design an Integrated Circuit
History and Motivation– What’s a circuit– What’s an integrated circuit
IC design processOur friend the MOS transistorLet’s make a chipExamplesTrends
IC design is detailed and meticulous (i.e. not cheap)IC fabrication is also not cheapNo user serviceable parts inside – the chip works or it doesn’tSo why do we do this at LBL?Is IC design really sorcery?
P. DenesEngineering Division
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Circuit Problem ca. 1750
C
S R1
Charge capacitor CClose switch SEstimate propagation time through this transmission lineN ~ 1000
R2 R3 RN
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Solution
French physicist Abbe NolletComponents used:1000 Carthusian monksCapacitor based on design from University of LeydenResistive contact to C
R1 .. R1000 C S
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Circuit Layout
~900 feet
Simultaneous jumping of monks →“electricity is fast”Circuit composed of well-defined, discrete parts connected together(Circuit dimensions are a bit large)
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Fast Forward → 1906
Grid modulates conductionCan be used for analog applicationsCan also be used for digital applications
TriodeLee de Forest
TriodeLee de Forest
Plate (+)
Grid
Cathode (-)
Heater
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ENIAC – 1945, U. Penn.Designed to calculate ballistic ordnance firing tables
Electronic Numerical Integrator And Computer
Its thirty separate units, plus power supply and forced-air cooling, weighed over thirty tons. Its 19,000 vacuum tubes, 1,500 relays, and hundreds of thousands of resistors, capacitors, and inductors consumed almost 200 kilowatts of electrical power.
But then, some work at a famous industrial lab changed everything
But then, some work at a famous industrial lab changed everything
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IBM 701 -1952
16 kHz cycle2k words fast storage1st computer for scientific work
CPU
Modular circuit assembliesof components
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The solution?
E
B
C
Thin razor cut
Point contacttransistor
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Almost
Point contact transistor is a surface effect device (and surfaces are easy to contaminate – not to mention paper clips can be mechanically unstable)Schottky contacts, rather than pn junctionsShockley junction transistor (1949)
Ge
pp n
CE
B
Although the point contacttransistor did live for a while
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CDC 1604/160 - 1960
160 kHz cycle32k words fast storage
Modular circuit assembliesof components
The first desktop (literally)
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Integrated Circuits - 1958
Jack KilbyGe
(1 transistor)
Robert NoyceSi
(2 transistors)
Texas Instruments(Patent)
Fairchild(Patent)
Legal wranglesResolved in mid-60’s
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p+ substrate
Early Circuits – Planar Bipolar Process
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p+ substrate
high resistivity p- epitaxial layer
Early Circuits – Planar Bipolar Process
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p+ substrate
high resistivity p- epitaxial layer
grow SiO2 andopen base window
Early Circuits – Planar Bipolar Process
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p+ substrate
high resistivity p- epitaxial layer
n implant
n+
Early Circuits – Planar Bipolar Process
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p+ substrate
high resistivity p- epitaxial layer
p implant
n+p+
Early Circuits – Planar Bipolar Process
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p+ substrate
high resistivity p- epitaxial layern+p+
E
Contacts/Metal
B B C
Early Circuits – Planar Bipolar Process
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EB B C
p+n+
p+
p
p+
SB DG
n+ p+ p+n
E
B
C
ICIB
IC ~ β IBIB ~ exp(VBE/kT)
S
G
D
ID
ID ~ (VGS – VT)2 VGS>VTID ~ 0 VGS<VT
B
Bipolar Junction vs. Insulated Gate Transistors
1st MOS on Si - 1960
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MOS and CMOS take over
Early circuits were mostly bipolar (especially analog)MOS took hold for memoryCMOS invented in 1963, but took off (once fabrication became good enough) in the 80’s
PassingWORDlinesSTI/TrenchCapacitor
W: WL=H BL=HR: WL=H BL=LX: WL=L
WL
BL
Bipolar SRAM CMOS DRAM
S
DD
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MOS logic – Intel 4004 - 1970
The first single chip CPU was the Intel 4004, a 4-bit processor meant for a calculator. It processed data in 4 bits, but its instructions were 8 bits long. Program and Data memory were separate, 1K data memory and a 12-bit PC for 4K program memory (in the form of a 4 level stack, used for CALL and RET instructions). There were also sixteen 4-bit (or eight 8-bit) general purpose registers. The 4004 had 46 instructions, using only 2,300 transistors in a 16-pin DIP. It ran at a clock rate of 740kHz (eight clock cycles per CPU cycle of 10.8 microseconds) - the original goal was 1MHz, to allow it to compute BCD arithmetic as fast (per digit) as a 1960's era IBM 1620.
8 µm PMOS
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Timeout - Glossary
Metal Interconnect
Metal Interconnect
IBM 0.18µ SOI CMOS
Polysilicon gate
Process – the complete fabrication process which produces the integrated circuits. It includes photolithographic mask preparation, wafer preparation and processing, etc. The process defines for the designer what kinds of devices are available and what their performance characteristics should beFeature size (or line width) – the smallest dimension which can be reliably lithographed. So a “1 µm CMOS process” contains N- and P-channel MOS transistors with 1 µm minimum feature size
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Size: 7.44mm x 5.29mm; 174,569 transistors; 0.5 um CMOS technology (triple metal layer).
ENIAC – 50th Anniversary Edition
30 mg vs 30 tons
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Digital Standard Cells
Predefined logic gates (“cells”) - Circuit composed of well-defined, discrete parts connected togetherwrite a description(program) of the logic functionssynthesize the design (using the library)place and route the design
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For example
B
A
Q
A
BQA B Q
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But This Is Not What We Do
We do mixed-mode design - analog functions, supported by digital logic. The analog functions are full custom: design the circuit at the transistor level, and design/optimize each transistor for the given function. This is not assembling a collection of pre-defined modules.
Timeout - GlossaryFull custom design means that we draw each transistor. What we can adjust are the width (W) and length (L) of the channel. For a given process, the transconductance (∂I/∂V) and capacitance depend on W, L and the process parameters.
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Why do we do this?
High rate fixed target experiments in the ’80s (NA11, E706, …) needing finer granularity (to reduce occupancy)
5x5 cm2 Si strips
Particle Tracking Detectors
Higher density of electronics and
interconnect required
Higher density of electronics and
interconnect required
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What we do
Design custom ICs, typically in support of lab programsGenerally, these ICs have many channels and are connected to some sort of sensor, transducer, … at the front-end, do some sort of signal acquisition/processing, and send information, usually digital, off the back end of the chip
We conceptualize the design, implement it electrically and produce the data needed to prepare the masksWe don’t actually fabricate the ICs – we use commercial IC processes
Analog FE “Conversion” Digital BE
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Commercial Processes
Mask sets for modern technologies are very expensive (so we don’t work at the cutting edge)One wants to try ideas out first anyway, so we use “Multi-project” services (brokers, who assemble many people’s projects onto one run)So our technology choices are limited
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Large R&D Investment
2003 investment ~$14B (17% of sales). Recently, investment ~12-15% of sales…
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Steps in the IC Design Process
ConceptualDesign
Negotiatethe specs
InitialBehavioral
Design
No transistors yetTechnology selection
1→0?0→1?
SchematicDesign &
Simulation
Circuit solutionsTransistor designFight the tools!
Layoutand
Verification
OptimizationDRC, LVSFight the tools!
Post-layoutSimulation
parasitic extractionFight the tools!
Tape out!
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Let’s Make A Chip
For a made-up application, we have a high-output-impedance sensor that needs a buffer amplifier. Specifications:– Drive an output load of 1 pF in less than 10 ns– Use no more than 1 mW– Be precise to >6 bits
This will be a pretty banal example to fit within the time of this talk
CL=10pF∞ Ω
≤10 ns
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Our Friend the MOS Transistor
G
S D
Gate O
xide
Bulk
Channel L
Channel
W
TOX
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Design
VIN
VBIAS
CL
Current Mirror
IIN IOUT
Same VGSSame current
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Design
VIN
VBIAS
CL
Current Mirror
IIN IOUT
Same VGSSame current
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Design
VIN
VBIAS
CL
Current Mirror
IIN IOUT
Same VGSSame current
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Hand Calculation
140~LWfor mA/V 2
A 400 mW 1
F/m 0048.0
nm 1.7/Vm 03.0
20
2
=
=∂∂
=
⇒
==
==
ILWC
VIg
TC
T
OXGS
m
OX
OXOX
OX
μ
μ
εε
μ ProcessParameters
Check the calculationwith simulation
( )
ILWC
VIg
VVLWCI
OXGS
m
TGSOX
μ
μ
=∂∂
=
−= 2
2
VIN
VBIAS
CL
01=
∂∂
==DSDS
DS VI
Rg
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Simulation Schematic
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Simulation
( )22 TGS
OX VVLWCI −=
μ
Netlist
Choice of model
MS2 D1 D1 VDD VDD PCH L=1U W=80U M=1C1 OUT GROUND 1PV3 N$617 GROUND DC 0V AC 1 0V2 INP N$617 PULSE ( 1 1.5 50N 1NS 1NS 1 2 )I1 VDD N$207 DC 0.25MAMN4 N$207 N$207 GROUND GROUND NCH L=1U W=20U M=1MN3 OUT OUT S1 GROUND NCH L=0.28U W=39U M=1MN2 D1 INP S1 GROUND NCH L=0.28U W=39U M=1MS1 OUT D1 VDD VDD PCH L=1U W=80U M=1MN1 S1 N$207 GROUND GROUND NCH L=1U W=20U M=1V1 VDD GROUND DC 2.5V
Process parameters
20
2
F/m 0048.0
nm 1.7/Vm 03.0
==
==
OX
OXOX
OX
TC
Tεε
μ
ChosenSimulator
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How Did We Do?
Response to a 1 → 1.5V step
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2nd Order Effects are Critical in IC Design
gm – not too bad, hand calculation → 2 mA/V, simulation → 1.86 mA/VRDS – not so good, hand calculation → ∞ Ω, simulation → 24 kΩ– Channel length modulation: IDS → IDS(1 + λVDS) so R = 1/λIDS
DC gain – not so good, hand calculation → ∞, actual value is AV = gmRDS = 1.86 mA/V x 24 k Ω ~ 50 ⇒ offset of 1-2%
OK – so now, I understand everything, right?
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Modern Devices are more Complicated
Simple model Modern Reality
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2nd Order Effects may be 1st Order for the Design
VGS
I DS
VT
Stronginversionmodel
Sub-
thre
shol
d sl
ope
1/n
kT/q
Weakinversion
model
03
2 WLCC OXGS =
( )qkT
In
VVL
WCVIg D
TGSOX
GS
DSm /
1−=
∂∂
=μ
For a preamp, maximize gm/CG
JunctionLeakage
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Process Variation
Simulation parameters are for the “typical” processBut what if you got the “Friday at 4:30” process?Foundries often provide “corner” data which attempt to represent, within device models, what are the “worst” and “best” cases. The designer needs to make sure that the design works under all of these cases (you don’t know who will be running the implanter the day of your run)
OK – so now, I understand everything, right?
T
FF
SS FS
SFThe process variation models often take the form that one flavor of transistor is “better” (or “faster”) than the other, and the cause may be correlated or anti-correlated with the other flavor. This leads to 5 cases: “typical” and the permutations of the extremes above.
As processes improve,“corners” shrink ⇒ oursuccess rate goes up
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Matching
Not all Carthusian monks are identical – nor are all MOS transistorsDirectional variation of implantation across the wafer; statistics of how many dopantatoms there are…
IIN IOUT
Same VGS≠Same current
δVGS
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Up to 33 masks in this process
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Drawn Layers
Si substrate
SiO2
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Verification
• DRC• LVS
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Still Not Done
Extraction (of parasitics) and “post-layout” simulation2nd Order Effects are Critical in IC Design
RPAR=80 Ω
CPAR=0.2 pF
Various otherdesign sinsnot checked
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Current IC Group Projects
4-channel CCD readout (CDS + 16 bit dynamic range digitizer) for SNAP (space qualified)A “high-voltage” clock driver and sequencer for the above (space qualified)A 16-channel higher-speed variant for almost Column-Parallel CCD readout (>100 fps / Megapixel; ≥14 bits)4-channel, 10 GS/s switched capacitor array with digitizers and digital waveform accumulators16x16-channel CdTe pixel readout for high-energy x-ray astronomy (space qualified)Monolithic detectors (see below)
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Increasing Integration
Si Detector
Custom IC
Sept. 9, 2002 M. Garcia-Sciveres - The ATLAS Pixel Detector 14
P i x e l 2 0 0 2 - C a r m e l
Pixel Module
Schematic Cross Section(through here)
Bumps
Flex Hybrid (green)
Sensor
Wirebonds
ASICs
Pigtail (beyond)
Sept. 9, 2002 M. Garcia-Sciveres - The ATLAS Pixel Detector 14
P i x e l 2 0 0 2 - C a r m e l
Pixel Module
Schematic Cross Section(through here)
Bumps
Flex Hybrid (green)
Sensor
Wirebonds
ASICs
Pigtail (beyond)
1D
2D-Hybrid
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Active Pixels – the IC is the Detector
SiO2
Si
~10 µm
~10 µm
SiHeavilyDoped
Substrate
Used to replace CCDs in cheap (and now not-so-cheap) digital camerasAlso might make the ideal detectors for certain types of electron microscopy
300 keV e−
1000 µm
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Well Adapted to High Sensitivity (speed)
Thin detectorThin collection region within thin detectorGain – e− are several times minimum ionizing: very high S/NMonolithic – can add on-chip electronics (ADCs, fast readout …)Use radiation-hardening techniques developed for HEP
300 keV e−
4 µm SiO2
8 µm active Si
40 µm
2 µm SiO2
2 µm Al
Inactive Si
50 µm total
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1st Image (200 keV)
CMOS Imager Film
12x3640 µm Pixels
24x7220 µm Pixels
48x14410 µm Pixels
Beam stop on the 200 CX at NCEM
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1st Useful Detector Prototypes
19 µm pixelsin-pixel CDS
6 µm pixels
19 µm anti-blooming pixels
Constructing readout anduser interface software now
10 bit ADCson 19 µmpitch
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Future for IC Design
Mandatory Plot
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Technology Node Scaling
10
100
1000
1994 1999 2004 2009 2014
Year
Tech
nol
ogy
Nod
e [n
m] ITRS 94
ITRS 97ITRS 99ITRS 00ITRS 03
International Technology Roadmap for Semiconductors
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CMOS Scaling
Gate
n+ S n+ D
p substrateDoping - Na
Channel Length L
tOX
NMOS Scaled NMOS
Constant Field Scaling
V/κ
Channel Length L/κ
p substrateDoping - κ Na
tOX/κ
WD
V
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Advantages of Scaling
• Speed ~CGATEVDD/IDSAT~ 1/κ• Circuit Density ~ 1/A ~ κ2
• Power/circuit ~ 1/κ2
• Power Density (P/A) ~ 1
V
Great for digital.Just press the “zoom”button and shrink your layout!Analog is another story
IBM
J. R
&D
, Vol
ume
46, N
umbe
rs 2
/3, 2
002
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Another Word on Matching
D
OXV
VV
T
OXOXaT
TA
DSWLA
V
TWLTNV
T
T
T
∝
⊕=
∝
)(
~
σ
Fluctuations in doping
Scaling: W/L=const., L∝TOXBut newer technologies don’t have AVT x LMIN = const.Bad for analog, worse for digital. Digital to the rescue?
1
2
VO1VI2
VO2VI1
Mismatch affectsthis noise margin
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What’s Next?
ITRS 2003“Scaling” and “Death of CMOS” are talks on their own…
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Future for IC Design at LBL
Keep the edge in HEP (LHC upgrades, Linear Collider)Astronomy – on the ground and in spaceBiology and materials – imaging detectors– general “smart” detectors – 2D arrays measuring (x, y, E, t)– specialized “smart” detectors – e.g. built-in temporal
autocorrelations– fast detectors for dynamics – “movies”– high sensitivity
R&D– Hybrid pixilated APDs – 2D single photon counting arrays– Chemfets – CMOS circuits where the conduction modulation is
by (bio) chemical reaction
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Electronic Technology Growth Benefits All Science at LBL
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And Acknowledgements + Apologies to the IC+ES Groups
J-F BecheJ-M BussatB HolmesJ JohnsonJ JosephA KarcherB KriegerT StezelbergerJ StirkkinenC VuJ-P WalderA WhichardH YaverS Zimmermann
Topics not suitably addressedCMOS scalingNew devicesSiGe (and other strained Si) / SOIAnalog design problems at fine feature size…