how to detect single tones with fpgas - digilent.s3.us

How to Detect Single Toneswith FPGAs

by Pablo Trujillo

2How to Detect Single Tones with FPGAs

The detection of single tones or harmonics is still a challenge for embedded systems, as it requires a large computational power. Designers can easily evaluate different approaches by using FPGA boards for signal generation and tone detection.

Engineers sometimes need to implement a proof-of-concept system quickly. And evaluation kits and modules, which fit the application under consideration perfectly, are not always available. This is especially the case if discrete logic and high computing power is needed at the same time. This is where development boards with FPGAs can help. For example, a designer needs to evaluate the detection of special single tones in a signal, something which is still a challenge for the hardware and the processing power of embedded systems. To accomplish this task, he can generate the signal on one board and analyze it on a second one.

Introduction

Figure 1: A single tone detection system using two FPGA boards and two data converter boards from Digilent

Using two FPGA development boards, which are connected through the analog signal, will accomplish that easily. For the board creating the single tone signal, an Eclypse Z7 Zynq-7000 APSoC (All Programmable System-on-Chip) board together with the Zmod AWG 1411 digital-to-analog converter module, both from Digilent, could be used. A signal generator running on the Eclypse board would then create the signal employing a frequency-shift keying modulation, which is common in communication systems.

On the receiving side, Digilent’s Genesys ZU-3EG Zynq Ultrascale+ MPSoC development board and the Zmod Scope 1410 analog-to-digital converter module for acquiring the signal are an excellent choice. The Genesys’ on-board multi-processor system-on-chip (MPSoC) features not only a quad-core Arm Cortex-A53 applications processing unit. It also includes a dual-core Arm Cortex-R5F real-time processing unit (RPU) and plenty of programmable logic (PL). This way, enough processing power is available for the task at hand.

Figure 2: Block diagram of the evaluation system


Eclypse Z7

XC7Z020

PLZMOD

DACfsk_modulator

ZMOD DAC driver

Genesys ZU

ZU3G

PL RTU

ZMODADC

driver

Goertzelfilter

ZMODADC

The FSK modulation technique modulates a sinusoidal carrier frequency with different frequencies to encode either a logic ‘0’ or a logic ‘1’. As it works with a band of frequencies, it is possible not only to encode binary values but also complete bytes. The receiver would then decode the resulting analog signal with a fast Fourier transformation (FFT), a discrete Fourier transformation (DFT) or a Goertzel filter.

To achieve the required high frequencies of the output signal, a fast clock signal is needed. The Eclypse board has two clock sources connected to the Zynq APSoC: one directly to the processing subsystem (PS) and the other one coming from the Ethernet PHY to the programmable logic (PL). As the PS is not needed to create the modulated signal, the clock connected to the PL which runs at a frequency of 25MHz can be used. To achieve higher

Implementing the Tone Generation with an FSK Modulator


Figure 3: Block diagram of the tone generator

Figure 4: Schematic of the DAC output circuitry on the Zmod DAC

frequencies, for example 100MHz, one of the mixed mode clock manager (MMCM) can be utilized. These are part of the clock management tile (CMT) on the UltraScale architecture.

The carrier signal for the FSK is stored as a sine wave in one of the block random access memories (BRAMs) of the SoC. At every edge of the clock, a value from an address in the BRAM will be read, and the address incremented. It is possible to create the different frequencies related to the logic levels to be encoded using different increment values.

Before the modulated signal can be converted to the analog domain, the digital-to-analog converter on the Zmod AWG module needs to be configured. This is done by setting the analog multiplexer IC on the board to the value needed.

Eclypse Z7

DDR interface

GPIO configuration

PL

ZMODDAC

XC7Z020 PL

ZMODDAC

driver Top FSKmodulation

BRAM


Detecting a Single Tone with the Goertzel Algorithm

Figure 5: Block diagram of the single tone detector

The analog signal is then acquired by the analog-to-digital converter of a Zmod Scope module mounted on a Genesys ZU board. The Zmod Scope board uses the AD9648 converter from Analog Devices. It has a resolution of 14 bits, two channels, and provides 105 MSamples/sec. The board needs to be configured and the power supply enabled at start-up. A freely available module created by Digilent for use on the FPGA will take care of these tasks. The Zmod connects to the Genesys ZU development board through the SYZYGY-compliant interface through an SPI port and a DDR interface for the data transfer.

To create this DDR interface on Zynq UltraScale+ devices, the IDDRE1 (dedicated Dual data rate input register 1) primitives have to be used. These primitives are similar to the IDDR primitives from Xilinx‘ 7 series, but these are incompatible with the newer generations. To enable the communication, the processing subsystem has to generate two clock signals: one for the transfers over the SPI port with 50MHz and one for the DDR interface and the AXI (advanced extensible interface) modules for control and BRAM with 100MHz. This frequency also corresponds to the sampling rate.

Once all samples are read and moved to BRAM, the Goertzel algorithm will execute to detect if the frequencies in question are present in the signal. While it would be possible to use an FFT to discover the presence of a single tone in a time-domain sequence of n samples, it is not very efficient, as several multiplications of complex numbers would have to be executed. Employing a single-point DFT would reduce the number of multiplications and would therefore be more effective. But it still does not solve the problem of the operations on complex numbers.

Genesys ZU

DDR interface

SPI interface

PL

ZMODADC

ZU-3EG PL

AXIAcquisition

control

AXI4

AXI4

ZMODADC

driver

BRAM

AXI BRAMcontroller

RTU

Goertzel filter


Figure 6: The complete design block for the Genesys ZU board

Speed Improvements are PossibleWhile the Goertzel algorithm works, thanks to the RPU, fine on the Zynq UltraScale+ device, it is not very suitable for using it at the Edge, because it needs to acquire an entire window to run. Even if the real-time processing unit runs at 500MHz and the processing of all samples takes 60µs, the maximum frequency is limited to 16kHz.

The Goertzel algorithm on the other hand is very efficient. It is implemented in the form of a second-order IIR-(infinite impulse response-)filter using two real feedback coefficients and a single complex feedforward coefficient, reducing the number of arithmetical calculations. On the Genesys ZU board, the algorithm will run on the Arm Cortex-R5F real-time processing unit of the on-board Zynq MPSoC.

The filter needs a static number of samples to compute the selected tone. These samples need to be shared between the programmable logic and the processing subsystem. A solution proposed by Digilent is to use an AXI IP block that reads a configurable number of converted values and writes them to the BRAM. This block random access memory has to be created as true dual port memory, where one port is connected to the AXI acquisition control module and the other one to the AXI BRAM controller. The AXI control module will contain just two registers: one for acquisition start and the other one for setting the length of the window.

Figure 6 shows the complete block diagram for the decoding system, including the Zynq UltraScale+ block, the driver for the Zmod Scope, the acquisition control module, the BRAM, the AXI BRAM controller for storing samples, and the other AXI blocks.

Pablo Trujillo is an FPGA developer for power electronics devices and a specialist in DSP and power electronics control design.


Since 2000, Digilent (a wholly owned subsidiary of National Instruments) has provided embedded engineers, researchers, scientists, and students with cost-optimized products, tools, and application information for innovative, FPGA and SoC based hardware-software systems. Our customizable and flexible solutions will accelerate development time for even the most experienced professionals, while maintaining low barrier to entry for advancing engineers, students, and the perpetually curious.

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We specialize primarily in Xilinx-based FPGA/SoC development boards/kits and portable USB test and measurement devices, all designed to be owned by and used from an engineer's or student's desk. We also offer a variety of expansion modules (Pmods and Zmods) to create flexible I/O options for our other products.

There are several options to improve the performance. First, the algorithm could be executed in the PL, allowing to process each signal at the time it is acquired. Also, using a notch filter together with a peak detector will reduce the time needed for computation to a fraction of that needed by the Goertzel algorithm. But in this case, the information carrying the signal phase is lost.Yet another option is to use both RTU cores on the Zynq UltraScale+, as they can be run in split mode. Unlike DFT, where a decimation in time can be implemented, IIR filters need the previous outputs to compute the next. Here the delay will still be 60µs, but the throughput will improve, because the output will be updated at twice the frequency.On Digilent’s website, a complete example project is available for download:

https://projects.digilentinc.com/pablotrujillojuan/single-tone-detector-with-genesys-zu-and-rtu-728c3f

how to detect single tones with fpgas - digilent.s3.us

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