Huang-Yu Chen†, Mei-Fang Chiang†, Yao-Wen Chang†

Lumdo Chen‡, and Brian Han‡

Novel Full-Chip Gridless Routing Considering Double-Via Insertion

†The Electronic Design Automation LaboratoryGraduate Institute of Electronics Engineering

Department of Electrical EngineeringNational Taiwan University

Taiwan

‡UMC, Taiwan

2

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion

3

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion

4

Redundant-Via Insertion Via-open defectsVia-open defects are one of the dominant failures due

to the low-k, copper metal process in the nanometer era Redundant-via insertionRedundant-via insertion is highly recommended

by foundries to improve via yield and reliability Double vias have 10X 100X smaller failure rates than single vias

90nm copper interconnect(source: TSMC)

double-via insertion

metal 1metal 2

viaredundant via

5

Dead, Alive, and Critical Vias For a via, a redundant-via candidateredundant-via candidate is its adjacent

position where a redundant via can be inserted Via categories:

Dead via:Dead via: the via with no redundant-via candidate Alive via: Alive via: the via with at least one redundant-via candidate Critical via:Critical via: the via with exactly one redundant-via candidate

critical via

dead viaalive vias

metal 1metal 2

viaredundant-via candidate

6

SS

TT

SS

TT

Redundant-Via Aware Routing Traditionally, double-via insertion is focused on the

post-layout stage Minimizing dead and critical vias during routingMinimizing dead and critical vias during routing can

increase the post-layout double-via insertion rate by 15 25%

Dead vias cannot be paired with redundant vias Critical vias may not be paired due to competition with others

SS

TT

a bad path a better pathdead via alive via

a routing instance

7

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion

8

Multilevel Routing Billions of transistors may be fabricated in a single chip Multilevel routingMultilevel routing has demonstrated the superior

capability of handling large-scale designs

Already-routed netTo-be-routed net

coarsening uncoarsening

‧global routing ‧detailed routing

‧failed nets rerouting‧refinement

9

Observations In the coarsening stage, global and detailed routing global and detailed routing

are intertwined with each otherare intertwined with each other at each level Advantage:

Routing resource estimation is accurate Information of previously routed nets is exactly

known Disadvantage:

Optimization freedom is limited Refinement takes a lot of efforts and the solution

easily falls into local optima

Need more flexibility to address Need more flexibility to address nanometer electrical effectsnanometer electrical effects

10

SeparateSeparate global routing and detailed routing Effectively perform global and detailed routing optimization

Pre-analyzePre-analyze congestion congestion to assist resource estimation

Apply bottom-upbottom-up routing approaches to handle local circuit effects

Better for routability, congestion, and via minimization Redundant-via planning is a local effect

Maximize the optimization freedom

Ideas for Improvements

11

Our Two-Pass, Bottom-Up Routing FrameworkTo-be-routed net Already-routed net

G0

G1

G2

coarsening

First Pass StageFirst Pass Stage Second Pass StageSecond Pass StagePrerouting StagePrerouting Stage

high

low

coarsening

G0

G1

G2

coarsening

coarsening

Apply global routingglobal routing for local nets and iteratively refine the solution

Use detailed routingdetailed routing for local nets, reroute failed nets, and estimate resources level by level

Identify congestion congestion hot spotshot spots based on the routing topology of each net

12

Redundant-Via Aware Routing

Congestion-Prediction PreroutingCongestion-Prediction Prerouting

Via-Minimization Global RoutingVia-Minimization Global Routing

Redundant-Via Aware Detailed RoutingRedundant-Via Aware Detailed Routing

13

congestion-predictionprerouting

Congestion-Prediction Prerouting Predict congestion hot spots to guide the following routing

for better congestion minimization Help to reduce detours and thus the via count

Alleviate post-layout double-via insertion efforts

global tilecongestion-minimization

global routingrouting

topology

14

SS

TT

Probabilistic Congestion Model Predict congestions based on the probabilistic distribution

of 1- and 2-bend global routes

probabilistic congestions

SS

TT+3/5

+1/5

+1/5

+2/5

+1/5

+2/5

+1/5

+1/5

+3/5

+1/5 +1/5 +1/5+2/5

+1/5 +1/5 +2/5+1/5

five 1- and 2-bend global routes

may become congestion hot spot

15

Via-Minimization Global Routing Apply congestion-driven global pattern routingpattern routing

[TCAD’02] to reduce via counts Uses L-shaped (1-bend) and Z-shaped (2-bend) connections

to route nets Has lower time complexity than maze routing

L-shaped (1-bend) connection Z-shaped (2-bend) connection

16

The objective is to minimize dead and critical vias Router should select a path that passes through the

fewest redundant-via candidates in the routing graph It may incur more detours and thus more vias

Must consider (1) redundant-via planning and (2) via minimization simultaneously

Take the via countvia count and redundant-via related penaltyredundant-via related penalty as the cost to guide the detailed maze routing

Redundant-Via Aware Detailed Routing

Cost function for a net n: Vn: #via, Pn: redundant-via related penalty.

n n V P

17

Redundant-Via Related Penalty Degree of Freedom of via v (DoFv):

# of redundant-via candidates of v Set the cost of redundant-via candidate r as

S

T

1/3

1/3

1/3

1/4

1/4

1/4

1/4

1/2

1/2

metal 1 metal 2 via redundant-via candidate

S

T

penalty = 5/6

penalty = 1/4

?

?

1iv

DoF{ max{ } | vi is the via that shares r }

18

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion

19

Post-Layout Double-Via Insertion Problem Given a post-routing layout, pair each via with one

redundant via as many as possible without incurring any design-rule violation

Different approaches may affect the insertion result

2 vias are paired 3 vias are paired

metal 1metal 2

viaredundant via

Better Yield

20

Previous Work Yao et al. [GLSVLSI’05] mentioned that post-layout

double-via insertion can be solved by maximum bipartite matching

Lee and Wang [ASPDAC’06] showed that maximum maximum bipartite matching formulation is incorrect for some bipartite matching formulation is incorrect for some casescases

Lee and Wang used maximum independent set (MIS)maximum independent set (MIS) to solve the problem and applied heuristics to speed up

MIS is NP-complete, MIS is NP-complete, high time complexityhigh time complexity

21

A Troublesome Example

v2 v3

v1v1

v2 v3

V2 and V3 cannot be paired simultaneously

(horizontal design-rule conflict)

v2 v3

v1

v1

r2

v2

v3v2 v3

v1

v1r1v2

v3

V1 and V3 cannot be paired simultaneously

(vertical design-rule conflict)

routing layout cross-section view

metal 1metal 2

via12

redundant-via candidate

metal 3

via13

22

Bipartite Graph Formulation Problem

V2 and V3 cannot be paired simultaneously

v1

r2

v2

v3

v1r1v2

v3

V1 and V3 cannot be paired simultaneously

v1r1

r2

v2

v3

a bipartite formulation

v2 v3

v1

v2 v3

v1

v2 v3

v1

v1

r1,2v2

v3

another bipartite formulation

v1r1v2

v3

v1

r2

v2

v3

InfeasibleLack

optimality

best result ?

23

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm

Optimal Algorithm for up to 3 Routing LayersOptimal Algorithm for up to 3 Routing Layers On-Track/Stack Redundant-Via Enhancement Two-Stage Double-Via Insertion (TDVI) Algorithm

Experimental Result Conclusion

24

Our Bipartite Formulation If stack via is treated as one unit viastack via is treated as one unit via, the double-via

insertion for designs with up to 3 layersup to 3 layers can be optimally solved by maximum bipartite matchingmaximum bipartite matching A polynomial-time optimal algorithm for the restricted case

The troublesome example can be accurately formulated

v1 v2

routing layout redundant-via candidate

metal 1metal 2

via12metal 3

via13

r2

v2

v3r

v1

v2

v1v2

cross-section view

v2

v1r2

v2

v3r

v1

v2 v2

v1

v2 is pairedv1 is paired

25

r4,5

v1

v2

r1

r2

r3

r6

Alive Vias

Redundant-ViaCandidates

v3 r9

r7,8

final bipartite graph

Optimal Algorithm for up to 3 Layers

metal 3metal 1 metal 2 via23 redundant-via candidatevia12

v1

v2

r1

r2

r3

r4

r5

r6

Alive Vias

Redundant-ViaCandidates

v3

r7

r8

r9

v1v2r1 r6

v3

r8

r2r3

r4 r7

r9

r5

r8

v2r7

v3

design-rule conflict between r7 and r8

routing layout

initial bipartite graph

26

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm

Optimal Algorithm for up to 3 Routing Layers On-Track/Stack Redundant-Via EnhancementOn-Track/Stack Redundant-Via Enhancement Two-Stage Double-Via Insertion (TDVI) Algorithm

Experimental Result Conclusion

27

Preference for On-Track/Stack Redundant Via Redundant vias can be placed on-track or off-track.

If a redundant via is placed on the wire segment of its corresponding via, it is on-track; otherwise, it is off-track

Prefer on-track on-track and stack stack redundant vias for double-via insertion

On-track redundant vias consume fewer routing resources Better to protect stack vias which have lower yield than

single vias

r1

r2r3

r4

r6

r5

v1

v2

on-track

metal 1metal 2

via12

redundant-via candidate

metal 3

via23

routing layout

off-track

28

On-Track/Stack Redundant-Via Enhancement Construct the weighted bipartite graphweighted bipartite graph and use

minimum weighted bipartite matching minimum weighted bipartite matching to solve For via v and its redundant-via candidate r, define

weight w(v, r) as follows:

stack redundant via preference

on-track redundant via preference

w(v,r) =tr/N, if v is a stack via containing N single vias;

tr, if v is a single via.{

tr =1, if r is on-track;2, if r is off-track.{

29

Double-Via Insertion with Preference

routing layout

r1

r2

r3

r4,5

r6

r7,8

r9

1

2

2

1/2

1

1/2

1

22

v1

v2

v3

weighted bipartite graph

redundant via

r4

v1v2r1

r2r3

r6

r7

v3

r9

r8

r5

metal 3metal 1metal 2

redundant-via candidatevia23via12 via24

metal 4

insertion resultwith preference

v1v2

v3

r1 r6

r9

30

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm

Optimal Algorithm for up to 3 Routing Layers On-Track/Stack Redundant-Via Enhancement Two-Stage Double-Via Insertion (TDVI) AlgorithmTwo-Stage Double-Via Insertion (TDVI) Algorithm

Experimental Result Conclusion

31

Lb

Lt

Two-Stage Double-Via Insertion Algorithm1. Partition the layout into sublayouts with at most 3 layers,

s.t. # of design-rule conflicts between sublayouts is minimized

v1 v2

v3

v4

r3 r7

v6

r4

r8

metal 1 metal 2metal 3 metal 4

viaredundant-via candidate

r1 r2

r6r5

v5

conflict

32

criticality = 2

criticality = 0

Two-Stage Double-Via Insertion Algorithm2. Decide the priority of each sublayout by criticalitycriticality

For redundant-via candidate r that has design-rule conflicts with the different sublayout, criticality cr = # of induced dead vias after inserting r; otherwise, cr = 0

Criticality of sublayout L = Σ cr, where r is inside L

v1 r1

r4

v5

v2

v3

v4

r7

r5 v6r8

metal 1 metal 2metal 3 metal 4

viaredundant-via candidate

Criticality: 0r2

r3

r6

conflict

Criticality: 2Lb

Lt

33

Two-Stage Double-Via Insertion Algorithm3. Solve sublayouts in the non-decreasing order of criticality

If one sublayout is solved, update its adjacent sublayouts by removing the infeasible redundant-via candidates

v1 r1

r4

v3

r3

r6r5

metal 1 metal 2metal 3 metal 4

viaredundant-via candidate

Criticality: 0

Criticality: 2Lb

r1

r2

v1

v2

v3

v4

v5

v6

r7,8

r4,5

r3

v5

conflict

Lt

v2

v4

r7

v6r8

r2

34

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion

35

Experimental Setting Platforms

Routing system: 1.2 GHz Sun Blade 2000 Double-via insertion algorithm: 3.2 GHz Intel Pentium 4

DRC verification: Cadence SoC Encounter MCNC benchmark:

Circuit Size (um2) #Layer #Net #Pin

Mcc1 45000 × 39000 4 1693 3101

Mcc2 152400 × 152400 4 7541 2502

4

Struct 4903 × 4904 3 3551 5471

Primary1 7522 × 4988 3 2037 2941

Primary2 10438 × 6488 3 8197 1122

6

S5378 435 × 239 3 3124 4818

S9234 404 × 225 3 2774 4260

S13207 660 × 365 3 6995 10776

S15850 705 × 389 3 8321 12793

S38417 1144 × 619 3 21035

32344

S38584 1295 × 672 3 28177

42931

36

1 100%1 1.4 100%1.24 2.6 100%7.2 100%1.20 Comp.

148.5 100%54483191.6 100%74054170.9 100%688.6 100%67026S38584

43.7 100%4065555.9 100%5279892.0 100%362.8 100%50304S38417

16.4 100%1663320.0 100%2340539.3 100%326.0 100%19875S15850

11.6 100%1376715.7 100%1826331.2 100%122.6 100%17127S13207

2.9 100%53503.4 100%66908.4 100%22.6 100%6833S9234

4.0 100%67844.6 100%852011.0 100%41.0 100%8296S5378

17.7 100%2236523.7 100%2497759.7 100%42.0 100%25955Primary2

2.7 100%53474.2 100%616912.3 100%4.6 100%6374Primary1

2.8 100%72483.5 100%996911.6 100%5.9 100%10055Struct

783.0 100%331531149.1 100%34387702.9 100%3339.9 100%33093Mcc2

25.7 100%568751.5 100%576538.8 100%171.2 100%5791Mcc1

(s)RateVia(s)RateVia(s)Rate(s)RateVia

TimeCmp.#SingleTimeCmp.#SingleTimeCmp.TimeCmp.#Single

TBR (Ours)VMGR (ASPDAC'06)MARS (TCAD'05)MGR (ASPDAC'05)

Circuit

1 100%1 1.4 100%1.24 2.6 100%7.2 100%1.20 Comp.

148.5 100%54483191.6 100%74054170.9 100%688.6 100%67026S38584

43.7 100%4065555.9 100%5279892.0 100%362.8 100%50304S38417

16.4 100%1663320.0 100%2340539.3 100%326.0 100%19875S15850

11.6 100%1376715.7 100%1826331.2 100%122.6 100%17127S13207

2.9 100%53503.4 100%66908.4 100%22.6 100%6833S9234

4.0 100%67844.6 100%852011.0 100%41.0 100%8296S5378

17.7 100%2236523.7 100%2497759.7 100%42.0 100%25955Primary2

2.7 100%53474.2 100%616912.3 100%4.6 100%6374Primary1

2.8 100%72483.5 100%996911.6 100%5.9 100%10055Struct

783.0 100%331531149.1 100%34387702.9 100%3339.9 100%33093Mcc2

25.7 100%568751.5 100%576538.8 100%171.2 100%5791Mcc1

(s)RateVia(s)RateVia(s)Rate(s)RateVia

TimeCmp.#SingleTimeCmp.#SingleTimeCmp.TimeCmp.#Single

TBR (Ours)VMGR (ASPDAC'06)MARS (TCAD'05)MGR (ASPDAC'05)

Circuit

Gridless Routing Comparison Compared with the gridless router

Reduce the via count 20% over MGR [ASPDAC’05] Reduce the via count 24% over VMGR [ASPDAC’06]

37

Redundant-Via Aware Detailed Routing Consider redundant vias during detailed routing

1.4X fewer dead vias and 1.1X fewer critical vias 2% slight increase in the via count

1 1 1 1 100%0.84 1.14 1.41 0.98 100%Comp.

175.3 12185333053057100%148.5 13358450952295100%S38584

53.0 8804247739489100%43.7 9702328739289100%S38417

20.6 3695107716179100%16.4 3950139615969100%S15850

14.2 291378613443100%11.6 3248103713263100%S13207

3.4 11403385158100%2.9 12844345144100%S9234

5.0 14984456411100%4.0 16566196448100%S5378

20.0 378943522338100%17.7 429858621788100%Primary2

3.0 800635325100%2.7 9501005176100%Primary1

3.1 531427097100%2.8 664586763100%Struct

997.3 7518261732153100%783.0 8741417931237100%Mcc2

29.8 13133885508100%25.7 15466165385100%Mcc1

(s)ViaViaViaRate(s)ViaViaViaRate

Time#Critical#Dead#TotalComp.Time#Critical#Dead#TotalComp.

With Redundant Via ConsiderationWithout Redundant Via Consideration

Circuit

1 1 1 1 100%0.84 1.14 1.41 0.98 100%Comp.

175.3 12185333053057100%148.5 13358450952295100%S38584

53.0 8804247739489100%43.7 9702328739289100%S38417

20.6 3695107716179100%16.4 3950139615969100%S15850

14.2 291378613443100%11.6 3248103713263100%S13207

3.4 11403385158100%2.9 12844345144100%S9234

5.0 14984456411100%4.0 16566196448100%S5378

20.0 378943522338100%17.7 429858621788100%Primary2

3.0 800635325100%2.7 9501005176100%Primary1

3.1 531427097100%2.8 664586763100%Struct

997.3 7518261732153100%783.0 8741417931237100%Mcc2

29.8 13133885508100%25.7 15466165385100%Mcc1

(s)ViaViaViaRate(s)ViaViaViaRate

Time#Critical#Dead#TotalComp.Time#Critical#Dead#TotalComp.

With Redundant Via ConsiderationWithout Redundant Via Consideration

Circuit

38179.2%-98.6%0.98 70.8 76.2%-96.0%0.98 Comp.

2.02 78.8%3832297.8%4863228.8 77.6%3631494.1%468174972753057S38584

1.41 79.5%2885898.1%363198.4 78.7%2762194.8%350913701239489S38417

0.53 78.5%1159497.8%1477326.2 77.9%1107294.1%142141510216179S15850

0.44 79.6%987898.0%1240312.5 77.5%925894.4%119441265713443S13207

0.15 79.1%374998.4%474132.2 70.8%322894.6%455948205158S9234

0.20 76.9%448597.7%58301.6 75.0%418193.4%557159666411S5378

0.76 81.5%1783199.9%2187232.8 80.1%1737099.0%216772190322338Primary2

0.16 82.0%430999.9%525837.8 74.1%385398.8%520152625325Primary1

0.24 84.1%592999.9%705327.5 79.0%555299.6%702970557097Struct

1.80 75.7%2205698.6%2911817.9 75.7%2169897.0%286502953632153Mcc2

0.27 75.6%380298.2%502814.6 71.2%349495.9%490851205508Mcc1

RateRviaRateRvia

(s)Track Track RateRvia(s)Track Track RateRvia

TimeOn-#On-Ins.#Ins.TimeOn-#On-Ins.#Ins.

#Alive#Total

TDVI (Ours)H3K (ASPDAC'06)Via Info.

Circuit

179.2%-98.6%0.98 70.8 76.2%-96.0%0.98 Comp.

2.02 78.8%3832297.8%4863228.8 77.6%3631494.1%468174972753057S38584

1.41 79.5%2885898.1%363198.4 78.7%2762194.8%350913701239489S38417

0.53 78.5%1159497.8%1477326.2 77.9%1107294.1%142141510216179S15850

0.44 79.6%987898.0%1240312.5 77.5%925894.4%119441265713443S13207

0.15 79.1%374998.4%474132.2 70.8%322894.6%455948205158S9234

0.20 76.9%448597.7%58301.6 75.0%418193.4%557159666411S5378

0.76 81.5%1783199.9%2187232.8 80.1%1737099.0%216772190322338Primary2

0.16 82.0%430999.9%525837.8 74.1%385398.8%520152625325Primary1

0.24 84.1%592999.9%705327.5 79.0%555299.6%702970557097Struct

1.80 75.7%2205698.6%2911817.9 75.7%2169897.0%286502953632153Mcc2

0.27 75.6%380298.2%502814.6 71.2%349495.9%490851205508Mcc1

RateRviaRateRvia

(s)Track Track RateRvia(s)Track Track RateRvia

TimeOn-#On-Ins.#Ins.TimeOn-#On-Ins.#Ins.

#Alive#Total

TDVI (Ours)H3K (ASPDAC'06)Via Info.

Circuit

Post-Layout Double-Via Insertion Compared with H3K [ASPDAC’06]

71X runtime speedup A higher insertion rate (98.6%) and a higher on-track rate (79.2%)

39

Double-Via Insertion of S5378

40

Local View of Insertion Results

41

Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion

42

Conclusion We have developed a redundant-via aware gridless

routing system Reduced via counts Obtained fewer dead vias and critical vias

We have proposed a post-layout double-via insertion algorithm

Resulted in a higher insertion rate Resulted in a higher on-track rate Achieved at least one-order runtime speedup

43

Thank You!

44

Q & A