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Hardware Documentation

8-Bit Microcontroller forDirect 12 V-Operation

HVC 2480B-B4

Edition Feb. 2, 2016DSH000176_001EN

Data Sheet

HVC 2480B-B4 DATA SHEET

2 Feb. 2, 2016; DSH000176_001EN Micronas

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Any information and data which may be provided in the document can and do vary in different applications, and actual performance may vary over time.

All operating parameters must be validated for each customer application by customers’ technical experts. Any new issue of this document invalidates previous issues. Micronas reserves the right to review this docu-ment and to make changes to the document’s content at any time without obligation to notify any person or entity of such revision or changes. For further advice please contact us directly.

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– easyLIN

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Contents, continued

Page Section Title

DATA SHEET HVC 2480B-B4

5 1. Introduction5 1.1. Features

8 2. Package and Pins8 2.1. Pin Assignment9 2.2. Pin Function Description10 2.3. Multiple Function Pins10 2.3.1. BA-Ports10 2.3.2. B-Ports10 2.3.3. BH-Ports10 2.3.4. MOUT Ports10 2.3.5. LIN-Port10 2.3.6. S5VE11 2.4. Special I/O Function Assignment14 2.5. External Components15 2.6. Package Outline Dimensions

16 3. Electrical Data16 3.1. Absolute Maximum Ratings17 3.2. ESD and Latch-up17 3.3. Transient Supply Voltage18 3.4. Recommended Operating Conditions20 3.5. Characteristics

31 4. Functional Summary31 4.1. Power Supply31 4.2. Voltage Regulators31 4.3. CPU31 4.4. CPU Modes33 4.5. Clock Supply33 4.5.1. 1 MHz IC Oscillator33 4.5.2. Internal Low-Power RC-Oscillator33 4.5.3. Clock Supervision33 4.5.4. PLL/ERM34 4.6. Memory34 4.6.1. Memory Map34 4.6.2. Program Memory (Flash)34 4.6.3. EEPROM34 4.6.4. NVRAM34 4.6.5. I/O Registers34 4.6.6. XRAM34 4.6.7. IRAM / (E)SFR35 4.7. Peripherals35 4.7.1. Wake-up Logic35 4.7.2. Window Watchdog / Wake Timer35 4.7.3. Digital Watchdog35 4.7.4. LIN UART and LIN Physical Interface36 4.7.5. Fast Shutdown Logic (FSD)

Micronas Feb. 2, 2016; DSH000176_001EN 3

Contents, continued

Page Section Title


36 4.7.6. Multi-Threshold Comparator (MTC)36 4.7.7. External Port Control (EPC)36 4.7.8. A/D Converter (ADC)37 4.7.9. Internal Temperature Sensor37 4.7.10. Embedded Amplifier37 4.7.11. 16-Bit Timers T0, T137 4.7.12. 8-Bit Timer T2, T337 4.7.13. Capture Compare Unit38 4.7.14. SPI38 4.7.15. Enhanced Pulse Width Modulator (EPWM)38 4.7.16. Pulse-Width Modulator

39 5. Differences

40 6. Data Sheet History



Note: The limited possibilities of analyzing the device in the given package, may lead to a number of not analyzable problems.

1. Introduction

The HVC 2480B is a highly integrated embedded 8-bit microcontroller suitable for direct 12V operation. Based upon a high-performance 8051 core, with 8-bit data and 16-bit addresses, the controller integrates numerous diagnostic and high-performance analog functions aimed at minimizing both design effort, as well as required board space. The IC features a debug interface, timers/counters, capture compare units, an interrupt controller, a multi-channel A/D converter, an advanced LIN UART with a LIN2.1 compliant physical interface, an embedded operational amplifier, a linear temperature sensor, multi-threshold comparators, and PWM outputs. The multitude of integrated digital and analog features minimizes the number of necessary external components and allows to connect switches and sensors directly either with 5 V or 12 V signal range. The integrated power supply switches, together with five different operating modes, allow power optimi-zation to be tailored to specific system needs.

The HVC 2480B features 32 kbyte of Flash program memory, providing high flexibility in code development, production ramp-up, and in-system code update.

1.1. Features

Core

– CPU: High-performance 8051 core with on-chip sin-gle-wire debug interface, 14-input 4-prio interrupt controller and NMI, two data pointers, 4 HW break-points, embedded trace module with 16 branch trace message frames

– CPU-active operating modes: DEEP SLOW, SLOW and PLL

– Power-saving modes (CPU inactive): IDLE, SLEEP and STANDBY

– CPU clock up to 24 MHz

– Internal oscillators:

• IC oscillator: 1 MHz, 2%, with PLL generating up to 24 MHz and EMI reduction

• RC oscillator: 35 kHz

Memory

– RAM: 1.75 kbyte (256 byte IRAM and 1.5 kbyte XRAM)

– Flash: 32 kbyte

– EEPROM: 512 byte

Analog

– S5VE: Auxiliary 5 V/20 mA power supply, overcur-rent and short-circuit protected (GND and VBAT)

– Overtemperature supervision

– Supply supervision: VDD, FVDD undervoltage reset, VBAT overvoltage reset with time delay of 524 ms and VBAT over/under voltage alarm inter-rupts

– 10-bit queued ADC channels with HW trigger option: 6 external inputs + VBAT + linear temperature sensor

– ADC reference: internal (AVDD or VREF) or external (S5VE)

– Three high-voltage multi-threshold comparators

– Embedded operational amplifier with 5 V I/O

– Linear temperature sensor connected to the ADC

– Virtual star point resistor network derived from high-current driver outputs serving as reference to the multi-threshold comparator

Communication

– LIN telegram supporting UART with automatic baud rate adjustment and receive/transmit FIFO

– Synchronous serial peripheral interface

High-Current Drivers

– Three 300 mA half-bridges to control motors, peak current up to 600 mA

Note: For passive free-wheeling on the high side external free-wheeling diodes are recom-mended.



Input and Output

– BA-ports: 5 ports with 12 V/5 V analog in, 12 V digi-tal in

– B-ports:6 ports with 12 V/5 V digital I/O (5 V in open drain mode), NVRAM1) selects reset state

– BH-ports: 6 ports with 12 V/5 V high-current digital I/O, source and sink typ. 15 mA, NVRAM1) selects reset state

– MOUT ports: 3 high-current half-bridge outputs

– MVSS1 and MVSS2 pins to connect external shunt resistor to ground for current measurement if using the integrated half-bridges

– LIN V2.1 interface

– PWM module configurable as either one single 15-bit PWM or two 8-bit PWMs

– Three enhanced PWM modules, 212-bit outputs, center or edge-aligned with programmable dead-band insertion

1) NVRAM is a non-volatile memory which is used to configure basic functions of the system like port states and related values during reset, operating status of digital and window watchdog after reset, etc.

Timers and Counters

– One 16-bit free-running counter with 3 capture and compare modules

– Two 8-bit timers

– Two 16-bit timers

Miscellaneous

– Digital watchdog clocked with the IC oscillator clock

– Window watchdog and wake-up timer clocked with the IC or RC oscillator clock

– Interrupt Controller with 28 inputs and 8 port wake-up inputs

– Fast shutdown logic: 3 voltage controlled modules for external power MOS protection

– Supply voltage: 9 to16 V (limited performance from 6 to 9 V and from 16 to 28 V)

– Junction temperature range: 40 to +140 °C

– Small package: PQFN40 6.0 8.0 0.9 mm3



5

BVDD

BVSSVDDVSS

fSYS

AVDD

VDD Regulator5 V

S5VE RegulatorS5VE

Power SavingLogic

35 kHz RCOscillator

Window Watch-dog / Wake Timer

Digital Watch-dog

1 MHz IC Oscillator

PLLERM

10-Bit ADC

12-Bit EPWM 00

16-bit Timer 0

16-bit Timer 1

16-bit CC

CAPCOM 0CAPCOM 1CAPCOM 2

DebugInterface

LIN UART

SPI

8051CPU

IRAM

InterruptController

XRAM1.5 kbyte

BA

0P

ort

BH1

Port

B0

Por

t

6

EEPROM512 Byte

MON

Fast Shutdown

FSD 0FSD 1FSD 2

8-Bit PWM 08-Bit PWM 1

LIN

Por

t

1

FVDD RegulatorFVDD

12-Bit EPWM 01

8-bit Timer 2

8-bit Timer 3

Wake Logic

Multi Threshold

MTC 0MTC 1MTC 2

AVDD Regulator &Sleep-Regulator

Emb.

Comparator

12-Bit EPWM 1012-Bit EPWM 11

12-Bit EPWM 2012-Bit EPWM 21

OpAmp

Counter

Logic

SDATFlash Memory

32 kbyte

TemperatureSensor

Three

MVSS1

MVDD1

Half-

BH0

Port

bridges

3

3

Virtual Star Point

MOUT0MOUT1MOUT2

MVSS2

MVDD2

256 Byte

NVRAM16 Bytes for

deviceconfiguration

Fig. 1–1: Block diagram of the HVC 2480B



2. Package and Pins

2.1. Pin Assignment

Pin Name PinNo.

BH1.0 21BH0.2 22BH0.1 23BH0.0 24BVSS 25

LIN 26MON 27

MVSS2 28MOUT2 29MVDD1 30MOUT1 31MVSS1 32

BA0.4 33BA0.3 34BA0.2 35

MOUT0 36MVDD2 37

BA0.1 38BA0.0 39

n.c. 40

PinNo.

Pin Name

20 BVDD19 BVDD18 S5VE 17 BH1.116 n.c.15 BH1.214 VDD13 VSS12 VSS11 VSS10 FVDD9 FVDD8 B0.07 n.c.6 B0.15 B0.24 B0.33 B0.42 B0.51 SDAT

21

40

20

1

See Fig. 2.1. for the pin assignment of the HVC 2480B. See Table 2–2 on page 11 for the special function assignment of the I/O pins.

Fig. 2–1: Pin assignment of the HVC 2480B in PQFN40-2 package



2.2. Pin Function Description

Table 2–1: Pin description

Name I/O Module / Function

Power Supply Pins

BVDD Positive power supply (14 V typical).

BVSS Ground

VDD Internal 5 V supply net, to be buffered by a capacitor to VSS.

VSS Digital ground

FVDD Internal 2.5 V power supply for the Flash memory, to be buffered by a capacitor to VSS.

Power Supply Pins for Integrated Half-Bridges

MVDD1 Positive power supply of half-bridges (14 V typical). To be connected to BVDD!

MVDD2 Positive power supply of half-bridges (14 V typical). To be connected to BVDD!

MVSS1 Common ground of half-bridges; a shunt for current measurement can be connected between this pin and BVSS. Must be connected with MVSS2!

MVSS2 Common ground of half-bridges; a shunt for current measurement can be connected between this pin and BVSS. Must be connected with MVSS1!

Application Pins

SDAT I/O Single wire debug interface

MON I Supply voltage supervision input

S5VE I/O Auxiliary 5 V power supply for external components. Optionally usable as digital input or reference input to the ADC.

B0.0 to B0.5 I/O 12 V / 5 V digital I/O, 5 V output in open drain mode with external pull-up (B0.5 is a 5 V analog in, too)

BA0.0 to BA0.4 I 5 V analog in, 12 V / 5 V digital in (BA0.2 is a 5 V digital input only)

BH0.0 to BH0.2,BH1.0 to BH1.2

I/O 12 V / 5 V high-current digital I/O, 5 V output in open drain mode with external pull-up

MOUT0 to MOUT2 O Outputs of the three half-bridges

LIN I/O LIN transceiver I/O



2.3. Multiple Function Pins

2.3.1. BA-Ports

A BA-port can either be used as an analog or digital input. The analog input is connected to the ADC input multiplexer. The digital input can either be read as a logical value in the corresponding register or it can be used as special input.

Some of the BA-ports are provided with additional ana-log functions like the I/Os of the embedded amplifier. BA0.4 can be used to connect an external reference to the MTC.See Table 2–2 for the assigned special input and out-put functions.

2.3.2. B-Ports

The B-ports are general-purpose high-voltage low-cur-rent digital I/O ports. The outputs can be configured to work in push-pull, open-drain, or tristate mode. In addi-tion to the digital I/O function, one special output func-tion can be assigned to each port.

The input can be used as digital input or as input for the special function assigned to the port.

See Table 2–2 for the special input and output function assignment.

Some of the ports can be used as wake-ports in power-saving modes.

The reset status of these ports can be defined by NVRAM setting.

2.3.3. BH-Ports

The BH-ports are general-purpose high-voltage high-current digital I/O ports. The outputs can be configured to work in push-pull, open-drain or tristate mode. In addition to the digital I/O function, up to three special output functions can be assigned to each port.

The input can be used as digital input or as input for the special function assigned to the port.


Some of the ports can be used as wake-ports in power-saving modes.

The reset status of these ports can be defined by an NVRAM setting.

2.3.4. MOUT Ports

The MOUT ports are three half-bridge outputs to con-nect e.g. a three phase BLDC motor.

Either the BH port pins OR the MOUT port pins can be used by the application!

The reset status of these ports can be defined by the appropriate NVRAM settings for the BH ports.

2.3.5. LIN-Port

The LIN port is mainly used for the communication via the LIN bus. The output is driven via the physical LIN interface. In addition to the LIN I/O function of the port, up to three special output functions can be assigned.


An incoming LIN message can be used as wake signal for the system.

2.3.6. S5VE

The S5VE port is designed to supply external hard-ware with 5 V supply voltage. The voltage at this pin (either supplied internally by activating the output or applied externally if the output is inactive) can be used as reference voltage for the ADC.

The S5VE-pin can also be used a digital input.



2.4. Special I/O Function Assignment

Table 2–2 shows special functions which can be assigned to some ports.

Table 2–2: Pins with special function assignments

Pin Name

Special InputFunction

Pin Output Function Analog I/O

# 0 # 1 # 2 # 3

12 V/5 V digital I/O, 5 V output with open drain

B0.0 WP0, CC0-IN-A, CLK-IN

B0D.B0 T3-OUT OP-IN1+

B0.1 WP1-A, CC1-IN-A B0D.B1 UART-TX OP-IN1-

B0.2 CC2-IN-A B0D.B2 CC2-OUT

B0.3 WP2-A, SPI-D-IN-A B0D.B3 T2-OUT

B0.4 CC0C-IN B0D.B4 SPI-D-OUT

B0.5 SPI-CLK-IN-A,CC1-IN-C

B0D.B5 SPI-CLK-OUT

ADC5

12 V/5 V analog in, 12 V digital in

BA0.0 WP3, UART-RX-A ADC0, OP-IN0+

BA0.1 WP2-B ADC1, OP-IN0-

BA0.2 CC2-IN-B ADC2, OP-OUT

BA0.3 WP4 ADC3

BA0.4 WP5 ADC4, MTC reference

12 V/5 V high current digital I/O, 5 V with open drain

BH0.0 FSD0 BH0D.B0 EPWM00 PWM0 T2-OUT FSD01)

BH0.1 FSD1 BH0D.B1 EPWM10 CC2-OUT PWM1 FSD11)

BH0.2 FSD2 BH0D.B2 EPWM20 CC1-OUT FSD21)

BH1.0 WP6, CC0-IN-B, SPI-D-IN-B, FSD0

BH1D.B0 EPWM01 PWM0 T3-OUT FSD01)

BH1.1 WP1-B, CC1-IN-B, FSD1

BH1D.B1 EPWM11 PWM1 SPI-D-OUT FSD11)

BH1.2 WP7, SPI-CLK-IN-B, FSD2

BH1D.B2 EPWM21 CC0-OUT SPI-CLK-OUT

FSD21)

LIN transceiver I/O

LIN UART-RX-B, WPLIN, CC2-IN-C

LMUX-OUT BH0D.LIN EPWM20 CC2-OUT

1) FSD0 to FSD2: Fast shutdown channel x can be configured to switch off this control signal.



Table 2–3: Half-bridge outputs

Pin Name

controlled transistor Pin Output Function Analog I/O

# 0 # 1 # 2 # 3

MOUT0 PMOS BH0D.B0 EPWM00 PWM0 T2-OUT MTC0, integrated star point resistor

NMOS BH1D.B0 EPWM01 PWM0 T3-OUT

MOUT1 PMOS BH0D.B1 EPWM10 CC2-OUT PWM1 MTC1, integrated star point resistor

NMOS BH1D.B1 EPWM11 PWM1 SPI-D-OUT

MOUT2 PMOS BH0D.B2 EPWM20 CC1-OUT MTC2, integrated star point resistor

NMOS BH1D.B2 EPWM21 CC0-OUT SPI-CLK-OUT



Table 2–4: Special function descriptions

Name Function

ADCx Analog input connected to ADC input multiplexer.

BH0D.LIN LIN port data latch

BH0D.Bx BH0 port data latch

BH1D.Bx BH1 port data latch

CCx-IN-A,CCx-IN-B,CCx-IN-C,CCx-IN

Inputs of the CAPCOM modules. A, B and C denote alternative inputs (either signal CCx-IN-A, signal CCx-IN-B or signal CCx-IN-C can be connected to the dedicated CAPCOM channel x).

CCx-OUT Compare output of the associated CAPCOM module.

CLK-IN External clock input.

FSDx Fast shutdown channel x can be configured to switch this control signal.

LMUX-OUT Output of the digital output multiplexer of the LIN output. Different signals can be output via this multiplexer.

MTCx Input of multi-threshold comparator x

OP-IN0+, OP-IN0-, OP-IN1+, OP-IN1-

Positive (+) and negative (-) inputs of the embedded amplifier. IN0+/- and IN1+/- are alternative inputs.

OP-OUT Output of the embedded amplifier.

SPI-CLK-IN-A,SPI-CLK-IN-B

Serial Synchronous Peripheral Interface Clock input. A and B denote alternative inputs.

SPI-CLK-OUT Serial Synchronous Peripheral Interface Clock output.

SPI-D-OUT SPI data output line.

SPI-D-IN-A, SPI-D-IN-B

SPI data input line. A and B denote alternative inputs.

Tx-OUT Timer module x output

UART-RX UART receive input.

UART-TX UART transmit output.

WPLIN LIN wake-up input.

WPx-A, WPx-B, WPx Wake port inputs. A and B denote alternative inputs (either signal WPx-A or signal WPx-B can be connected to the dedicated wake channel x).



2.5. External Components

12 V

5 V

5 V

2.5 V

MON

BVDD

BVSS

VDD

VSS

S5VE20 mA

VBATD1

11)2) 100n2)

10n2)

12)

CFVDD2)/

OvercurrentProtection

FVDD

47n

6V3

Rmon_ext

12 V

5 V

10n2)

Note: All values noted in this graphic might be changed after characterization.

10n2)

1 k

LIN

LINmaster

only

LIN bus

VBUS

BVDD

SDAT single-wire JTAG

0 during application

MVDD1

MVDD2

IntegratedHalf-Bridges

MVSS1

MVSS2shunt resistor 1)

1) Value according to the application needs.2) Blocking capacitors have to be placed as close as possible to the pin (<5 mm).

The connections between VSS and BVSS, between MVDD1, MVDD2 and BVDD and between MVSS1 and MVSS2 have to beimplemented as short and as low-resistive as possible.

CVDD1)2)/ 16 V

VSUP B

3) A 27 V TVS diode is recommended to improve powered ESD robustness.

V3)

50

Fig. 2–2: Recommended external supply and connections for HVC 2480B



2.6. Package Outline Dimensions

© Copyright 2009 Micronas GmbH, all rights reserved

b

0.30.18

MO-220C

JEDEC STANDARD

ISSUE

1.00.8

A

mm

UNIT A1

0.050.0

ITEM NO.

A3 *

0.2

aaa

0.15

ZG001094_001_0411-07-08

ANSI

bbb

0.1

ISSUE DATEYY-MM-DD

6.0

CO

0.08

D2

4.2

D

06694.0001.4

DRAWING-NO.

E

8.0

E2

6.2

ZG-NO.

Le

0.5

0 5

scale

10 mm

A4

0.4x45°

E

2xaaaC

A

B

DaaaC2x

e

e

b 40xbbb C BA

L

E2

D2

PIN 1 INDEX

C

DETAIL X

A

SEATING PLANE

CCO

X

A1

ccc C

BARE COPPER

A4

ccc

0.10.50.3

A3

* A3: Reference is leadframe thickness Lead side flank is half etched, thus remaining thickness is lower than original leadframe thickness (typical 0.08 mm)

LEADFRAME TIE BAR

Fig. 2–3: PQFN40-2: Plastic Quad Flat Non-leaded package, 40 pins, 6.0 8.0 0.9 mm3, 0.5 mm pitch, exposed thermal padOrdering code: DVWeight approximately 0.137 g



3. Electrical Data

3.1. Absolute Maximum Ratings

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability.

This device contains circuitry to protect the inputs and outputs against damage due to high electro-static voltages or electric fields; however, it is advised that normal precautions will be taken to avoid application of any voltage higher than absolute maximum-rated voltages.

Table 3–1: All voltages listed are referenced to BVSS, except where otherwise noted. All ground pins (BVSS and VSS) must be connected to a low-resistive ground plane close to the IC.

Symbol Parameter Pin Name Min. Max. Unit

TJ Junction Temperature under Bias 45 +150+180 1)

°C

Ts Storage Temperature 45 +150 °C

VSUP B Main supply voltage(battery voltage after polarity protection diode)

BVDD = MVDD1 = MVDD2

0.3 18 28 (2 min. max.)40 (2 sec max.)

V

tr SUP B Main supply voltage rise time BVDD = MVDD1 = MVDD2

4 (13 V ... 28 V),5 (13 V ... 40 V)

sms

ISUP Supply current BVDD, BVSS 200 200 mA

Sum of Motor supply current MVDDx, MVSSx 900 900 mA

MVSS Virtual motor ground MVSSx 600 600 mV

Vin 5V Input voltage for 5 V inputs SDAT, BA0.2 VSS0.3 VDD+0.3 V

Vin 12V Input voltage for 12 V inputs BA0.x 2) 3), BHx.y, B0.x, MON, S5VE

BVSS0.5 BVDD+0.7 V

MOUTx MVSS0.5 MVDD+0.7

Vin LIN Input voltage on LIN pin LIN 18 30 V

Iin 5V Input current for 5 V inputs SDAT, BA0.2 2 2 mA

Iin 12V Input current for 12 V inputs BA0.x 2) 3), BHx.y, B0.x, MON

2 2 mA

Iin total Sum of input current for 5 V and 12 V inputs

SDAT, MONBA0.x, B0.x

20 20 mA

Iout total Short term sum of output currents of all output ports (< 3 µs)

B0.x, BHx.y 300 300 mA

Sum of all output currents of all ports (>3 µs) B0.x, BHx.y 150 150 mA

1) Between TJ=+150 °C to +170 °C the overtemperature interrupt is triggered.10 °C above the interrupt threshold the overtemperature reset is generated, shutting down the whole device and setting all ports to reset state.

2) Except port BA0.2. This is a 5 V input port only!3) Input voltage clamped internally to VDD when the input is connected to the ADC.



3.2. ESD and Latch-up

Table 3–2: ESD and latch-up

Symbol Parameter Min. Max. Unit Comment

Ilatch Maximum latch-up free current at any pin (measurement according to AEC Q100-004 Grade 1 (TA=125 °C)

100 100 mA

ESD Human body model, equivalent to discharge 100 pF with 1.5 k (measurement according to AEC-Q100-002)

82

+8+2

kVkV

LINall other pins

System ESD According to IEC 61000-4-2 (330 Ohm, 150pF) 4 +4 kV LIN

CDM Charged device model (measurement according to AEC-Q100-011)

750 +750 V

3.3. Transient Supply Voltage

Table 3–3: Transient supply voltage

Parameter Pin Name Min. Max. Unit

ISO 7637-2:2004 pulse 1 1) BVDD 100 V

ISO 7637-2:2004 pulse 2 2) BVDD +50 V

ISO 7637-2:2004 pulse 2b BVDD +10 V

ISO 7637-2:2004 pulse 3a 3) BVDD, BA, B 150 V

ISO 7637-2:2004 pulse 3b 3) 4) BVDD, BA, B +100 V

ISO 7637-2:2004 pulse 5 BVDD +40,400 ms

V

ISO 16750-2 BVDD +28, 2 min V

1) With reverse polarity diode 2) Reverse polarity diode with equivalent series resistance and 1 F blocking capacitor with low ESR 3) 4.7 k minimum series resistance for I/O ports4) The sum of the whole clamping currents must not exceed 100 mA



3.4. Recommended Operating Conditions

Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.

Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device destruction.

Functional operation of the device at conditions beyond those indicated in the “Recommended Operating Condi-tions” is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.


Symbol Parameter Pin Name Min. Typ. Max. Unit

TJ Junction Temperature under Bias 40 +140 °C

VSUP B Main supply voltage(battery voltage)

BVDD=MVDD1=MVDD2

9

5.4 1)

14 16 18 (max. 8000 h)28 (max. 2 min.) 1)

40 (5 400 ms,30 s period) 1) 2)

Time values are not cumulative.

V

MVSS Virtual motor ground MVSSx 400 400 mV

S5VE Regulator, External Auxiliary 5 V Supply Voltage

CS5VE External Buffer Capacitor S5VE 0.68 1 2.2 µF

RS5VE External Load Resistance S5VE 0.25 50 k

Port Input Voltage

Vil Input Low Voltage BA0.x, B0.x, BHx.y, S5VE

0 1.4 V

Vih Input High Voltage BA0.x, B0.x, BHx.y, S5VE

3.6 BVDD V

Input High Voltage BA0.2 3.6 4.5 V

Embedded Amplifier Input Voltage

Vin Input Voltage B0.0, B0.1, BA0.0, BA0.1

0 AVDD 1.6 V

VICM Input Common Mode Voltage B0.0, B0.1, BA0.0, BA0.1

0 AVDD 2 V

LIN Transceiver3)

VBUS LIN Bus Voltage LIN 0.5 18 V

twhi High Time after Wake Pulse LIN 1 / fSYS s

BVDD Supply

CBVDD External Buffer Capacitor BVDD 1 µF

1) Some analog parameters may be out of limits.2) If BVDD > VBATR the MOUT ports are switched into high impedance mode; after timeout of the load dump timer the device is

reset 3) Compliant with “LIN Physical Layer Specification Revision 2.1”



VDD Regulator, 5 V Digital Supply Voltage

CVDD External Buffer Capacitor VDD 1 15 µF

FVDD Regulator, 2.5 V Flash Supply Voltage

CFVDD External Buffer Capacitor FVDD 0.68 1 2.2 µF

VBAT Monitor

Rmon_ext External Resistor on MON Pin for Current Limitation

MON 4.7 27 k

Ports

Iout Continuous Output Current B0.x 1 +1 mA

BHx.y 15 +15 mA

Continuous Output Current (embedded amplifier)

BA0.2 +2 mA

Iout rms RMS output current MOUTx 300 300 mA

Iout peak Peak output current ton< 1 s MOUTx 600 600 mA

Vohod Port High Output Voltage in Open-drain Mode

B0.x, BHx.y BVDD V

Others

fXTC External input clock (NVC1.XTCEN=1)

B0.0 0.980 1 1.020 MHz

fadcclk ADC clock 1 16 MHz

MTCXREF Multi Threshold comparator external reference

BA0.4 0 BVDD V


Symbol Parameter Pin Name Min. Typ. Max. Unit



3.5. Characteristics

Table 3–5: VSS = BVSS = 0 V, 9 V < BVDD < 18 V, TJ = 40 °C to +140 °C, external components according toFig. 2–2: "Recommended external supply and connections for HVC 2480B" on page 14 (unless otherwise noted)

Symbol Parameter Pin Name

Min. Typ.* Max. Unit Test Conditions

Package

RthJC Thermal Resistance from Junction to Case

7 ** K/W PQFN40-2 1s1p PCB 1)

RthJA Thermal Resistance from Junction to Ambient

27 **29 **

K/W PQFN40-2 1s1p PCB 1)

PQFN40-2 2s2p PCB 1)

Supply Currents, CMOS level on all inputs, no loads on outputs

IDDP BVDD PLL Mode Supply Current

BVDD 17 mA fSYS = fIO = 16 MHz, all peripherals off

6 mA fSYS = fIO = 4 MHz, all peripherals off

IDDS BVDD SLOW Mode Supply Current

BVDD 7 mA fSYS = fIO/2 = 16 MHz/512

4 mA fSYS = fIO/2 = 4 MHz/512

IDDDS BVDD DEEP SLOW Mode Supply Current

BVDD 6.5 mA fSYS = fIO/2 = 16 MHz/512

3.5 mA fSYS = fIO/2 = 4 MHz/512

IDDI BVDD IDLE Mode Supply Current

BVDD 1 1.8 mA RAM off, 1 MHz osc. off

1.2 1.9 mA RAM off, 1 MHz osc. on

1.2 1.9 mA RAM on, 1 MHz osc. off

1.5 2.1 mA RAM off, 1 MHz osc. off, embedded amplifier on

IDDSB BVDD STANDBY Mode Supply Current (see Fig. 3–1 on page 30)

BVDD 54 µA RAM off, RCOSC on

57 µA RAM on, RCOSC on

IDDSL BVDD SLEEP Mode Supply Current(see Fig. 3–2 on page 30)

BVDD 48 µA RAM off, RCOSC off

51 µA RAM on, RCOSC off

System Startup

tPU Power-up Time 500 s BVDD = 5.4 V, CVDD = 15.4 µF, CFVDD = 1.0 µF, time until the first code execution 1)

tWU Wake-up Time 600 s CVDD = 15.4 µF, CFVDD = 1.0 µF, time until the first code execution 1)

* Typical values describe typical behavior at room temperature (25 °C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.

** Values valid if the exposed pad is soldered onto the PCB.1) Not tested, characterized only.



Port Input Levels (B-port, BA-port, BH-Port, S5VE)

Vilh CMOS Input Low to High Threshold Voltage

3.5 V

Vihl CMOS Input High to LowThreshold Voltage

1.5 V

Vilh-Vihl CMOS Input Hysteresis 1.0 V

S5VE Regulator, External Auxiliary 5 V Supply Voltage

S5VERO Regulator Output Voltage S5VE 4.5 AVDD 5.5 V IS5VE = 20 mA

IOCS Overcurrent Shutdown S5VE 20 40 80 mA

tD,DEGL Overcurrent Deglitching Delay

S5VE 91 134 µs

ton,off Switching Time S5VE 18 µs @CS5VE = 680 nF, IS5VE = 0

40 75 µs @CS5VE = 1.5 µF, IS5VE = 0

Ii Input Leakage Current S5VE 1 1 µA 0 < Vi < VDD

1 1.5 µA VDD < Vi < BVDD

B-Port

Vol Port Low Output Voltage B0.x 0.6 V IO = 1 mA

Vohpp Port High Output Voltage B0.x BVDD 0.5

V IO = 1 mA, push-pull

Iocshi Overcurrent Shutdown in high state

B0.x 2 mA

Iocslo Overcurrent Shutdown in low state

B0.x 2 mA

td,degl Overcurrent Deglitching Delay

B0.x 9 µs

td,ocs Overcurrent Shutdown Delay

B0.x 18 µs short circuit to VBAT (@Vol) or GND (@Voh)

Ii Input Leakage Current B0.x 1 1 µA 0 V < Vi < BVDD

B0.5 1 3 µA 0 V < Vi < BVDD

ton,off pp Switching Time Push-Pull B0.x 1 3 µs Rload=14 k

ton,off od Switching Time Open Drain

B0.x 500 ns 4 k pull-up resistor to VDD 1)


1) Not tested, characterized only.






MOUT-Ports

Vol Port Low Output Voltage MOUTx 0.525 V IO = 300 mA, MVSS=BVSS

Voh Port High Output Voltage MOUTx MVDD 0.675

V IO = 300 mA, MVSS=BVSS


MOUTx 0.6 A


MOUTx 0.6 A


MOUTx 9 µs


MOUTx 19 µs short circuit to VBAT (@Vol) or GND (@Voh)

tr P-CH Switching time of P Channel MOSFET

MOUTx 4.5 µs in open-drain configuration

tf N-CH Switching time of N Channel MOSFET

MOUTx 4.5 µs in open-drain configuration

Ii Input Leakage Current MOUTx 1 20 µA 0 < Vi < BVDD

BH-Ports

Vol Port Low Output Voltage BHx.y 0.7 V IO = 10 mA

Vohpp Port High Output Voltage BHx.y BVDD 0.5

V IO = 10 mA, push-pull


BHx.y -20 mA


BHx.y 20 mA


BHx.y 9 µs


BHx.y 18 µs short circuit to VBAT (@Vol) or GND (@Voh)

ton,off pp Switching Time Push-Pull BHx.y 1 3 µs

ton,off od Switching Time Open Drain high to low

BHx.y 100 ns 4 k pull-up resistor to VDD 1)

Ii Input Leakage Current BHx.y 1 1 µA 0 < Vi < BVDD

BA-Port

Ii Input Leakage Current BAx.y 1 1 µA 0 < Vi < (VDD0.5V)

3 µA (VDD0.5V) < Vi < BVDD








Multi-Threshold Comparator

MTCthlh Multi-Threshold comparator thresholds low to high programmable thresholds

MOUTx MTCREF/10*n0.4 V

MTCREF/10*n

MTCREF/10*n+0.4 V

V MTCREF = MTCXREF and n=1, 2, 3, 5, 7, 8, 9 for CIT = 1, 2, 3, 4, 5, 6, 7

fixed threshold (CIT=0) MOUTx MTCREF 200mV

MTCREF MTCREF +200mV

V MTCREF = MTCXREF or MTCREF = VSTAR

MTCthhl Multi-Threshold comparator thresholds high to low programmable thresholds

MOUTx MTCREF/10*n0.4V

MTCREF/10*n

MTCREF/10*n+

0.4V

V MTCREF = MTCXREF and n=1, 2, 3, 5, 7, 8, 9 for CIT = 1, 2, 3, 4, 5, 6, 7

fixed threshold (CIT=0) MOUTx MTCREF 200mV

MTCREF MTCREF +200mV

V MTCREF = MTCXREF or MTCREF = VSTAR

MTChyst Multi-Threshold Comparator Hysteresis

MOUTx 20 mV

MTCdly Multi-Threshold Comparator Reaction Time

MOUTx 1 µs full-scale voltage jump on MTC input from 0 V to BVDD or vice versa

MTCdegl Multi-Threshold Comparator Deglitching Delay

3 µs

Integrated star point resistor network

VSTAR Voltage of internal virtual starpoint

BVDD/2 V MOUT0=BVDD, MOUT1=MVSS, MOUT2 open

Rssp Resistance of single star point resistor

25 50 k

Rssp matching Star point resistor matching

2 2 %







ADC **

LSB LSB Value VADC-REF

/ 1024

V

INL Integral Non-Linearity:difference between the output of an actual ADC and the line best fitting the output function (best-fit line)

2 2 LSB VADC-REF = VREFVADC-REF = AVDD

DNL Differential Non-Linearity: difference between the real code width and the ideal code width of 1 LSB


ZE Zero Error:difference between the output of an ideal and an actual ADC for zero input voltage


FSE Full-Scale Error:difference between the output of an ideal and an actual ADC for full-scale input voltage


QE Quantization Error:uncertainty because of ADC resolution

0.5 0.5 LSB VADC-REF = VREFVADC-REF = AVDD

R Conversion Range BA-Ports

AVSS VADC-REF

V Vin < VADC-REF

A Nominal Conversion Result

INT(Vin/LSB)

hex AVSS < Vin < VREF

000 hex Vin AVSS

3FF hex Vin VADC-REF

tc Conversion Time (including Sample Time)

2.56 µs 2)

ts Sample Time 1.25 µs 2)

Ci Input Capacitance during Sampling Period

15 pF

Ri Serial Input Resistance during Sampling Period

5 k


** Limited function if S5VE is used as ADC reference (VADC-REF = VS5VE) for BVDD<9 V.2) Not tested, guaranteed by design.






LIN Pin (7 V < BVDD < 18 V)

VBUSL Output Low Voltage LIN 0.8 1.0 V ILIN = 20 mA

RSLAVE Internal pull-up Resistance at Output

LIN 20 30 60 k

VSerDiode Voltage drop at the serial diode in the pull-up path

LIN 0.4 0.7 1.0 V

IBUS_LIM Current shutdown for driver dominant state

LIN 40 200 mA VBUS = 18 VDriver on

IBUS_PAS_dom Input leakage current at the receiver inclusive pull-up resistor as specified

LIN 1 mA VBUS = 0 VVBAT = 12 VDriver off

IBUS_PAS_rec Leakage current at the receiver inclusive pull-up resistor as specified

LIN 20 µA 8 V < VBUS < 18 V8 V < VBAT < 18 VVBUS VBAT Driver off

IBUS_NO_GND Leakage current at ground loss

LIN 1 1 mA GND = BVDD0 V < VBUS < 18 VVBAT =12 V

IBUS_NO_BAT Leakage current at BVDD loss

LIN 30 µA BVDD = GND0 V < VBUS < 18 VVBAT =disconnected

VBUSdom Receiver dominant state LIN 0.4 BVDD Without external diode

VBUSrec Receiver recessive state LIN 0.6 BVDD

VBUS_CNT Center of receiver threshold

LIN 0.475 0.525 BVDD VBUS_CNT = (Vth_dom + Vth_rec) / 2

VHYS Hysteresis of receiver threshold

LIN 0.175 BVDD VHYS = Vth_rec Vth_dom

LIN Driver, 20.0 kbps (tBit = 50 µs), SLEW = 2, Bus load conditions (CBUS; RBUS): 1 nF; 1 k / 6.8 nF; 660 / 10 nF; 500 ; 7 V < BVDD < 18 V

D1 Duty cycle 1 LIN 0.396 THREC(max) = 0.744 x BVDD;THDOM(max) = 0.581 x BVDD;BVDD = 7.0 V to 18 V;D1 = tBus_rec(min) / (2 x tBit)

D2 Duty cycle 2 LIN 0.581 THREC(min) = 0.422 x BVDD;THDOM(min) = 0.284 x BVDD;BVDD = 7.6 V to 18 V;D2 = tBus_rec(max) / (2 x tBit)







LIN Driver, 10.4 kbps (tBit = 96 s), SLEW = 3, Bus load conditions (CBUS; RBUS): 1 nF; 1 k / 6.8 nF; 660 / 10 nF; 500 ; 7 V < BVDD < 18 V

D3 Duty Cycle 3 LIN 0.417 THREC(max) = 0.778 x BVDD;THDOM(max) = 0.616 x BVDD;BVDD = 7.0 V to 18 V;D3 = tBus_rec(min) / (2 x tBit)

D4 Duty Cycle 4 LIN 0.590 THREC(min) = 0.389 x BVDD;THDOM(min) = 0.251 x BVDD;BVDD = 7.6 V to 18 V;D4 = tBus_rec(max) / (2 x tBit)

LIN Transceiver (7V < BVDD < 18V)

trx_pd Receiver Propagation Delay

LIN 6 s

trx_sym Receiver Propagation Delay Symmetry

LIN 2 2 s

Cslave Slave Capacitance LIN 250 pF 2)

DV/Dtfall Falling Edge Slew Rate LIN 0.8 V/µs SLEW = 3

1.6 SLEW = 2

8 SLEW = 1

depending on external load SLEW = 0

DV/Dtrise_max Maximum Rising Edge Slew Rate

LIN 1.6 V/µs SLEW = 3

2.3 SLEW = 2

6 SLEW = 1

depending on external load SLEW = 0

twup Low Pulse Time for Wake-Up

LIN 20 60 100 s VBUS < BVDD / 2 360 mV

tocsm Minimum Detectable Overcurrent Duration

LIN 5/fOCC 6/fOCC s

tocsd Overcurrent Shutdown Delay Time

LIN tocsm + 1/fOCC s


2) Not tested, guaranteed by design.






SPI

tsi Data In Setup Time to External Clock In

SPI-D-IN

1/ fIO + 25 ns

s 1)

thi Data In Hold Time from External Clock In

SPI-D-IN

1/ fIO s 1)

VREF Voltage Reference

VREF Voltage Reference Output Voltage

2% 2.44 +2% V

Linear Temperature Sensor

DT Temperature Error 15 +15 °C

AVDD Regulator, 5 V Analog Supply Voltage

AVDD Internal Analog Supply Voltage

4.75 5 5.25 V

VDD Regulator, 5 V Digital Supply Voltage

VDDRO Regulator Output Voltage VDD 4.5 5 5.5 V

FVDD Regulator, 2.5 V Flash Supply Voltage

FVDDRO Regulator Output Voltage FVDD 2.5 V

Embedded Amplifier

VOffs Input Offset Voltage B0.0, B0.1, BA0.0, BA0.1

3 11 mV

DV/Dt Slew Rate BA0.2 10 V/µs

VOH Output High Voltage BA0.2 AVDD 0.3

AVDD V IO = 2 mA

VOL Output Low Voltage BA0.2 0 0.25 V IO = 2 mA

Supply Supervision

VVDDUV VDD Undervoltage Reset Threshold

3.5 4.5 V

VFVDDUV FVDD Undervoltage Reset Threshold

2.25 V








VBAT Monitor

VBATU Battery Undervoltage Level

MON 7 9 V

VBATUHYST Battery Undervoltage Hysteresis

MON 220 mV

VBATO Battery Overvoltage Level MON 16 18 V

VBATOHYST Battery Overvoltage Hysteresis

MON 300 mV

VBATR Battery Reset Voltage Level

MON 28 33 V

tovrd Load Dump Timer Overvoltage Reset Delay

MON 524 ms

VMON_ratio Nominal Ratio between VMON input Voltage and ADC Input

MON 7

VMON_tol VMON_ratio Accuracy MON 2 2 % 5.4 V< Vi < 18 V 3)

no external resistor connected to MON

Imon Input Current MON 1 6 µA BVDD < 18 V during PLL mode

1 1 µA BVDD < 18 V during power-saving mode

1 MHz Oscillator

F1MHz Oscillator Output Frequency

980 1000 1020 kHz

F1MHz Short-Term Stability ±0.5 % <154 ms 1)

Internal RC Oscillator

FRC Oscillator Output Frequency

20 35 45 kHz

Clock Supervision

fSUP Clock Supervision Threshold Frequency

180 kHz


1) Not tested, characterized only.3) Indirectly tested.






PLL and ERM

tSUPLL PLL Locking Time 200 µs fPLL = 16 MHz

dtPLL Clock Uncertainty due toPLL Jitter

±2.5 ns ERM off

dtERM Clock Phase Shift due to ERM Action, Short Term and Long Term

000

7.512.520

ns ERM on, WEAK setting 1)

ERM on, NORMAL setting 1)

ERM on, STRONG setting 1)

NVRAM

NNVwe Number of write accesses for each NVRAM byte

100 cycles 4)

- Data Retention 16 years 4)

EEPROM

tPROG Programming Time for EEPROM

5.4 ms 4-byte programming time

NEwe Number of write accesses for each EEPROM word

100 k cycles 4)


Flash

NFwe Flash Write/Erase Cycles 1000 cycles 4)

10 k cycles 5)



1) Not tested, characterized only.4) Qualified according to AEC-Q100 for temperature grade 1.5) Qualified according to AEC-Q100 for temperature grade 2.






Fig. 3–1: Normalized BVDD STANDBY mode supply current versus ambient temperature

Fig. 3–2: Normalized BVDD SLEEP mode supply current versus ambient temperature

0

1

2

3

4

5

6

40 20 0 20 40 60 80 100 120 140

I DDS

B(T A)/

I DDS

B(T

A=25

°C)

TA [°C]

IDDSB(TA) normalized

RAM on (NVC0.PXC=1)

RAM off (NVC0.PXC=0)

0

1

2

3

4

5

6

40 20 0 20 40 60 80 100 120 140

I DDS

L(TA)/I

DDSL(T

A=25

°C)

TA [°C]

IDDSL(TA) normalized

RAM on (NVC0.PXC=1)

RAM off (NVC0.PXC=0)



4. Functional Summary

4.1. Power Supply

The device can be directly connected to the 12 V bat-tery power supply via protection diode. The IC is capa-ble to withstand all disturbances appearing on the car’s supply specified in ISO 7637-2:2004. An external volt-age regulator for the supply of the device is not required.

4.2. Voltage Regulators

Four voltage regulators are implemented, which pro-vide regulated supply voltages out of the noisy car supply to meet the requirements for the internal volt-age supply.

The AVDD regulator supplies the analog circuits. The output voltage of this regulator is more accurate than the supply of the digital logic. Therefore, this voltage can also be used as a reference for the ADC.

The VDD regulator supplies the internal digital logic. This regulator is equipped with an external pin to con-nect a capacitor to the regulator to absorb distur-bances caused by internal operations.

The FVDD regulator generates the supply voltage for the CPU and the Flash memory. Also this regulator is provided with an external pin to apply a buffer capaci-tor.

The S5VE regulator can be used to supply external hardware with regulated 5 V. This regulator can be controlled by software.

All regulators, except the S5VE regulator for the exter-nal supply, are supervised, and a reset is generated if a voltages fall below the specified values.

All regulated voltages are referred from the internal voltage reference (VREF). This reference can also be used as reference voltage for the ADC.

4.3. CPU

The CPU is based on an enhanced 8-bit 8051 core with 8-bit registers/accumulator, 8-bit data bus, 16-bit address bus, two-clock period machine cycle, and built-in “On-Chip-Debug-Support” (OCDS) accessible via a single-wire debug interface.

It is equipped with an interrupt logic of up to 14 mask-able and one non-maskable interrupt sources. Each interrupt source has its own enable flag and program-mable priority level of 0 to 3.

4.4. CPU Modes

Several CPU modes offer high flexibility in terms of available features and power consumption.

The typical application mode is the PLL mode, which is entered after reset. The IC starts clocked by the 1 MHz oscillator and, after configuration of the PLL, by the output of the PLL.

During power-saving modes, the power consumption is minimized depending on the enabled features of the system. The system can be woken up by several sources, event or time based.



Table 4–1: Operating modes

Activated System ModulesCPU Active Modes Power-Saving Modes

PLL, SLOW, DEEP SLOW IDLE STANDBY SLEEP

B, BH port outputs, over current protection

onWake subsystem- wake inputs- LIN transceiver wake input- Supply supervision

RAM on (opt.)2)

RC oscillatoron on2) off

Wake timer, clocked by: RC oscillator

1 MHz oscillatoron (opt.)2)

off1 MHz oscillator

VBAT-Mon. on

Embedded Amplifier (opt.)1)

Temp. protection, LIN transceiver output protection

on off

MTC, MOUT ports

Main system- CPU- 8051 interrupts- core logic, Flash/ROM- clock system

watchdog, window watchdog (opt.)2)

offS5VE(opt.)1)

Peripherals and FSD modules

8051 Power-Saving Modes3) off

1) Can be enabled by standby register flags.2) Can be enabled by NVRAM register flags.3) It is not recommended to use the 8051 built-in power-saving modes “Power-Down” (PCON.PD = 1) or “Idle” (PCON.IDL = 1).



4.5. Clock Supply

4.5.1. 1 MHz IC Oscillator

– Factory trimmed

– Low temperature coefficient

– Low power consumption

– High precision

The IC oscillator supplies the device with a fixed clock. This internal or the external clock is used as source for the PLL and is multiplied to a CPU frequency of up to 24 MHz.

As this oscillator is used for time-critical operations such as the transmission and reception of LIN frames, it shows a high initial accuracy by factory trimming, a high temperature stability, and a low short-time drift.

During power-saving modes, the oscillator is disabled and the power consumption minimized, but it can be enabled in IDLE mode to clock the wake timer.

4.5.2. Internal Low-Power RC-Oscillator

The internal low power oscillator supplies the window watchdog and the wake timer. This independent clock can be used as supervisory clock for the IC oscillator. It does not rely on the internal reference voltage and bias generators.

During CPU active mode, this oscillator may clock the window watchdog, and during power-saving modesthe wake timer.

4.5.3. Clock Supervision

The clock supervision monitors the IC clock fCLK. As fCLK depends on the IC oscillator, the PLL and the ERM, this supervision checks the functionality of the complete chain. If fCLK falls below the clock supervi-sion threshold of fSUP, the IC will be reset (fCLK = fSYSin PLL mode and fCLK = fSYS /512 in SLOW mode). The system is held in reset until the clock fCLK exceeds this threshold again.

4.5.4. PLL/ERM

The PLL is used to multiply the frequency of the IC oscillator (1 MHz) to a system frequency of up to 24 MHz.

An EMI reduction module (ERM) decreases the elec-tromagnetic influence on other components in the application by minimizing energy peaks in the spec-trum of the system frequency.



4.6. Memory

4.6.1. Memory Map

The 32 kbyte of flash memory and the 1.5 kbyte of XRAM are accessible via two busses, the PROG and XDATA bus. Code fetches and constant data read commands (MOVC), but also external data memory instructions (MOVX) are applicable. Hence the flash memory may not only contain program code, but also flexible accessible constant data, and program code may also be executed in the XRAM.

4.6.2. Program Memory (Flash)

The Flash consists of a main memory block, which is organized as a 32768-word by 8-bit array, divided in 64 sectors of 512 byte each. The Flash can be accessed either via the “Program Memory Bus” or the “External Data Memory Bus” starting at address 0x0.

4.6.3. EEPROM

This memory retains data non-volatile.

4.6.4. NVRAM

The NVRAM is a non-volatile memory used to define the behavior of ports and peripherals during and after reset. The ports can be configured as high or low out-put or as high-impedance input.

4.6.5. I/O Registers

There are two areas reserved for I/O registers, used for the configuration of the system and the peripherals. These registers are accessed by a MOVX command.

4.6.6. XRAM

The XRAM is usually used to store volatile application data at run time. Data stored in XRAM may be kept valid during power-saving modes. It may also be loaded with executable code.

The XRAM is accessed either by using the MOVX or the MOVC command.

4.6.7. IRAM / (E)SFR

0x0000

0xC000

0xD000

PROG XRAM

0.5 kbyte

128byte

0x00FF

0x0080

128byte

(E)SFR

128byte2)

0xE000

0xE600

fast

I/O

1.5 kbyte RAM

32 kbyte flash

I/O

0x8000

0xC200

0xC400

0xC600

registers

registers

EEPROM

10 byte

Customer

IRAM

1) Accessed using MOVX instructions

bus bus1)

2) Accessed only by indirect addressing instructions3) Accessed only by direct addressing instructions

bus3)bus

NVRAM

0xC406

0xC4C0

0xC4CA

ManufacturerNVRAM

6 byte

These are 8051 internal memory areas which hold registers, the stack memory, and (extended) special function registers. They are accessed by 8051 specific memory addressing modes.

Fig. 4–1: HVC 2480B memory map



4.7. Peripherals

4.7.1. Wake-up Logic

– Edge and level-triggered wake ports for an event-triggered wake-up.

– Leaving power-saving modes by reset

– Wake ports and the LIN wake signal can be used to generate interrupts during CPU active modes

– Wake timer for time-dependent wake-up, clocked either by the 1 MHz clock or the 35 kHz oscillator clock

During power-saving modes, the wake ports, the wake timer and the LIN transceiver wake input can be used to reset the IC in order to leave the power-saving mode. During non-power-saving modes (CPU active modes), the wake ports and the LIN transceiver wake input can be used to generate interrupts, and the wake timer can work as window watchdog.

4.7.2. Window Watchdog / Wake Timer

– Using the RC oscillator as clock source

– Generates a reset, if the watchdog is triggered too early, too late, or if wrong trigger values are written

– Trigger window adjustable from 100% to 0% of the counter period

– Counter clock selectable

– Wake timer during power-saving modes

– An NVRAM setting defines whether the watchdog is automatically enabled after reset or if the software must enable it.

The window watchdog in addition to the digital watch-dog offers a second possibility to supervise the pro-gram flow. The window watchdog is capable to detect if its trigger is set too early or too late. In both cases, a reset is generated. The cause for a faulty trigger mightbe, for example, a failure in scheduling the trigger or a software hang up.

The window watchdog is also a simple way to super-vise the IC oscillator. If the two device clocks drift too much a reset will be generated.

The window watchdog can be used as wake timer dur-ing the power-saving modes.

4.7.3. Digital Watchdog

The digital watchdog offers a possibility to supervise the program flow. The watchdog counter is clocked with a fixed clock and the period can be adjusted by a reload value for the counter. An NVRAM setting defines whether the digital watchdog is automatically enabled after reset or if the software must enable it.

4.7.4. LIN UART and LIN Physical Interface

– Minimized interrupt load for the CPU because of automatic break/sync detection, automatic bit rate adjustment and transmit/receive FIFO

– Full duplex (non LIN mode)

– 8-bit frames

– Odd, even or no parity bit

– One or two stop bits

– Programmable inverters at transmit output and receive input

– Baud rate pre-scaler for <0.5% adjustment accuracy within LIN bit rate range

– Interrupts: transmitted, form error, data lost, parity error, transmit error, sync detected, fifo fill status

– Programmable bit sample logic

– 9-byte FIFO for transmission or reception, e.g. the LIN response with up to 8 data bytes + checksum

– Automatic bit rate adjustment to the baud rate by break/sync detection without CPU interaction

For basics of the LIN protocol, refer to the LIN 2.1 Spec., “Protocol Specification”.



4.7.5. Fast Shutdown Logic (FSD)

– Protection of external half-bridges by an external feedback signal

– Programmable feedback signal polarity

– Input deglitcher for feedback signal

– Programmable compare window delay

– Interrupt source for fast reaction to the faulty condi-tion

– Programmable shutdown of two BH ports

– Programmable active command polarity

– Reference signal selectable from two ports

The fast shutdown logic provides a way to switch the BH ports into reset state automatically. This feature is useful to protect external power driver against short circuits without CPU interaction.

A feedback signal is connected to one of the multi-threshold comparators and compared to a reference signal. The reference signal can be selected from one of the command input signals (digital input signals) of one of the assigned ports. If the comparator signals a failure, the selected ports are switched into reset state. A programmable delay can be used to blank out the undefined feedback level during the switching time of the external hardware.

Protection of PMOS and NMOS drivers is possible.The levels are selected by adjusting the input levels of the multi-threshold comparators. The output of the comparator can be inverted to detect an exceeding or an undershooting of a certain level according to the requirements of the external hardware.

4.7.6. Multi-Threshold Comparator (MTC)

– Center of embedded star point or external voltage selectable as reference

– Interrupt generation with every change on the com-parator output

– Invertible comparator output

Input comparators can be used to acquire analog or digital input signals. For each comparator, the internal virtual star point resistor network can be used as refer-ence. Alternatively the reference can be derived from one BA port. Each change of the input can generate an interrupt. The output signals are the FSD feedback and EPC inputs.

4.7.7. External Port Control (EPC)

– Forces the outputs of the ports BH0.0 and BH0.1 to high or low level, depending on a selectable MTC output

The external port control offers the possibility to force the outputs of the ports BH0.0 and BH0.1 depending on a selectable MTC output. Therefore, an analog sig-nal, e.g. the motor current, can switch the ports on or off, according to the configuration of the MTC and the EPC.

4.7.8. A/D Converter (ADC)

– 8-bit or 10-bit resolution

– Short conversion time up to 2.56 µs

– Input multiplexer for several internal and external analog channels

– Programmable conversion time to optimize through-put/accuracy balance

– VREF, AVDD or S5VE selectable as reference

– Acquisition queue for automatic acquisition of up to four entries

– Selectable trigger source for event-driven or time-dependent start of the acquisition

– Four 16-bit registers deliver the results of the acqui-sition queue

– Four 8-bit registers deliver the most significant bits of the results of the acquisition queue

– Interrupt generation at end of conversion

This analog-to-digital converter allows the conversion of an analog voltage in the range from 0 to VREF or from 0 to AVDD, or in the range of the external refer-ence voltage applied to the S5VE pin to a digital value. The minimum value is represented by AVSS and the maximum input value by the selected reference volt-age minus 1 LSB.

An input queue holds up to four entries of input chan-nels. This queue is executed after a defined start con-dition. The entries contain the channel-number, the ref-erence voltage to be used, and a flag signaling whether the entry shall be executed. The converted values are stored in the dedicated result registers. After all entries of the input queue have been exe-cuted, an interrupt indicates the end of the conversion.

An analog multiplexer connects the ADC to one of the analog inputs. A sample and hold circuit holds the ana-log voltage during conversion. The duration of the sampling time is selectable.

The module supports both 8-bit and 10-bit data output for either fast access or high resolution.



4.7.9. Internal Temperature Sensor

– Measurement of the IC’s junction temperature

– Disabled in power-saving modes

– Temperature readable by ADC

The IC is provided with a linear temperature sensor to measure the junction temperature of the chip.

The temperature is detected by executing an A/D con-version of the analog output value of the temperature sensor, which is connected to the ADC multiplexer.

4.7.10.Embedded Amplifier

– Internal low-power operational amplifier adapt exter-nal analog signals

– Output of the amplifier connected to the ADC

– All pins available externally for arbitrary external cir-cuit configuration

– Gain and behavior selectable by external connec-tions and components

– Large DC-voltage gain (>80 dB)

– Low offset voltage

It can be used to boost external signals either for the input of the ADC or for external circuitry. The embed-ded amplifier can function as transducer or AC- and DC-amplifier comparable to all conventional opera-tional amplifier circuits.

The output of the amplifier is connected to one of the inputs of the ADC. This enables amplification of exter-nal signals which have to be acquired by the ADC.

4.7.11.16-Bit Timers T0, T1

– 16-bit auto-reload down counter

– Counter value readable

– 16-bit reload register

– Different counter clocks selectable

– Interrupt output

The 16-bit timer consists of a 16-bit down counter and a 16-bit reload register. The counter is automatically reloaded at underflow which also generates an inter-rupt.

4.7.12.8-Bit Timer T2, T3

– 8-bit auto-reload down counter

– 8-bit reload register

– Different counter clocks selectable

– Interrupt output

– Frequency output

The 8-bit timer consists of an 8-bit down counter and an 8-bit reload register. The counter is automatically reloaded at underflow which also generates an inter-rupt. The timers also feature output pins and an output divider. With this option, it is possible to output a clock signal with programmable frequency.

4.7.13.Capture Compare Unit

– 16-bit free running counter

– Counter value readable

– 16-bit capture register

– 16-bit compare register

– Input trigger on rising, falling, or both edges

– Output action: toggle, low, or high level

– Generates three different kind of interrupts: over-flow, input, compare

– Designed to detect asynchronous external events

The IC contains a Capture Compare Module (CAP-COM) with three subunits.

It comprises a free-running, readable 16-bit Capture Compare Counter (CCC) and three subunits (SU).

A subunit is able to capture the relative time of an external event input and to generate an output signal when the CCC exceeds a predefined timer value. Three types of interrupts enable interaction with soft-ware. Special functionality provides an interface to the asynchronous external world.



4.7.14.SPI

– 8- or 9-bit frames

– Usable as master or as slave

– Programmable data valid edge

– Programmable clock polarity

– Different master mode clocks selectable

– Input deglitcher for clock and data in slave mode

The SPI module provides a serial input and output link to external hardware. An 8- or 9-bit data frame can be transmitted/received synchronously to an internal or external clock.

4.7.15.Enhanced Pulse Width Modulator (EPWM)

– Two independent EPWM outputs with 12-bit resolu-tion for each EPWM module

– EPWM output period selectable

– Interrupt generation at the start of the period

– Center-aligned and edge-aligned EPWM signals possible

– Occurrence of the ADC interrupt terminable within the range of the EPWM period

– Inversion of both output signals selectable

– Two independent EPWM output signals are pro-grammable to control non-overlapping switching to avoid shortcuts when switching both drivers of a half-bridge.

– Defined output level in standby mode

An EPWM is an up/down-counter with programmable compare values for generating the EPWM output sig-nals. It serves as a generator of a frequency signal with variable pulse width or, with an external low-pass filter, as a digital-to-analog converter.

This module is implemented as a 12-bit up/down-coun-ter with two compare registers to generate the EPWM output signals.

An interrupt can be generated within the period of the EPWM signal. This source can either be used to trig-ger the start of an A/D-conversion or to generate an interrupt synchronized to a given state of the EPWM output signals.

Each EPWM module provides two independent EPWM signals. These outputs can be combined to operate the transistors of a half-bridge in non-overlapping mode, inserting a programmable dead-band.

The period of the EPWM output signal can be selected by an additional period register.

4.7.16.Pulse-Width Modulator

– 15-bit PWM or two 8-bit PWM

– Period and clock frequencies selectable by clock multiplexer

– The clock-divider interrupt can be used to detect the start of the period

– Inversion of the output signal selectable

– Defined output level in standby mode

This PWM is an auto-reload down-counter with pro-grammable reload interval. It serves as a generator for a frequency signal with variable pulse width or, with an external low-pass filter connected to its output, as a digital-to-analog converter.

This module consists of a 15-bit PWM module which can be split into two independently operable 8-bit PWM modules.




5. Differences

This chapter describes difference of this document to predecessor document „HVC 2480B-B4 8-Bit Microcon-troller for Direct 12V-Operation“ (PD000212_003EN).

Section Description

no changes



Micronas GmbHHans-Bunte-Strasse 19 D-79108 Freiburg P.O. Box 840 D-79008 Freiburg, Germany

Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: www.micronas.com

6. Data Sheet History

1. Advance Information: “HVC 2480B-B3 8-Bit Micro-controller for Direct 12V-Operation”, Oct. 5, 2012, AI000167_001EN. First release of the advance information.

2. Preliminary Data Sheet: “HVC 2480B-B4 8-Bit Microcontroller for Direct 12V-Operation”, July 2, 2013, PD000212_001EN. First release of the pre-liminary data sheet.

3. Preliminary Data Sheet: “HVC 2480B-B4 8-Bit Microcontroller for Direct 12V-Operation”, July 2, 2013, PD000212_002EN. Second release of the preliminary data sheet.

4. Preliminary Data Sheet: “HVC 2480B-B4 8-Bit Microcontroller for Direct 12V-Operation”, Feb. 3, 2015, PD000212_003EN. Third release of the pre-liminary data sheet.Major change: Package drawing updated

5. Data Sheet: “HVC 2480B-B4 8-Bit Microcontroller for Direct 12V-Operation”, Feb. 2, 2016, PD000176_001EN. First release of the data sheet.Major change: conversion into data sheet.

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